From patchwork Thu Sep 14 12:36:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Marchand X-Patchwork-Id: 131420 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2848842597; Thu, 14 Sep 2023 14:37:21 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5389A40A7A; Thu, 14 Sep 2023 14:36:57 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mails.dpdk.org (Postfix) with ESMTP id CF54140A80 for ; Thu, 14 Sep 2023 14:36:55 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1694695015; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=n6S9CWiD4/E0jbTjcsimyWx30UNa2czs98GLKh6XV54=; b=e3gP2GtW7qKY9SjtrZ2E6nZd26P1bcN/wl87YgmZls9ozY2yvpMU5CvCCjLtJ4aF0uj8t6 xrGa+1deLie0OFExqYe3v1BTyKg6kDdGJ2TwsqwFIYf1X6+6TpY7kIXmmJewXXmz/X8qRU 4QwkhawE28UJkXnwNYd29vf5s/Afbxs= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-687-cBlSODHEMD6CpUOJHhmZHw-1; Thu, 14 Sep 2023 08:36:51 -0400 X-MC-Unique: cBlSODHEMD6CpUOJHhmZHw-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 7702B18056AA; Thu, 14 Sep 2023 12:36:50 +0000 (UTC) Received: from dmarchan.redhat.com (unknown [10.45.225.25]) by smtp.corp.redhat.com (Postfix) with ESMTP id D95CE7B62; Thu, 14 Sep 2023 12:36:48 +0000 (UTC) From: David Marchand To: dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@amd.com, chenbo.xia@intel.com, nipun.gupta@amd.com, bruce.richardson@intel.com, Anatoly Burakov , Abdullah Sevincer , Gaetan Rivet Subject: [PATCH v3 07/15] pci: define some command constants Date: Thu, 14 Sep 2023 14:36:06 +0200 Message-ID: <20230914123615.1705654-8-david.marchand@redhat.com> In-Reply-To: <20230914123615.1705654-1-david.marchand@redhat.com> References: <20230803075038.307012-1-david.marchand@redhat.com> <20230914123615.1705654-1-david.marchand@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.5 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Define some PCI command constants and use them in existing drivers. Signed-off-by: David Marchand Acked-by: Bruce Richardson Reviewed-by: Chenbo Xia --- drivers/bus/pci/linux/pci_vfio.c | 8 ++++---- drivers/event/dlb2/pf/dlb2_main.c | 8 +++----- lib/pci/rte_pci.h | 6 ++++-- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c index 7881b7a946..bf91492dd9 100644 --- a/drivers/bus/pci/linux/pci_vfio.c +++ b/drivers/bus/pci/linux/pci_vfio.c @@ -156,18 +156,18 @@ pci_vfio_enable_bus_memory(struct rte_pci_device *dev, int dev_fd) return -1; } - ret = pread64(dev_fd, &cmd, sizeof(cmd), offset + PCI_COMMAND); + ret = pread64(dev_fd, &cmd, sizeof(cmd), offset + RTE_PCI_COMMAND); if (ret != sizeof(cmd)) { RTE_LOG(ERR, EAL, "Cannot read command from PCI config space!\n"); return -1; } - if (cmd & PCI_COMMAND_MEMORY) + if (cmd & RTE_PCI_COMMAND_MEMORY) return 0; - cmd |= PCI_COMMAND_MEMORY; - ret = pwrite64(dev_fd, &cmd, sizeof(cmd), offset + PCI_COMMAND); + cmd |= RTE_PCI_COMMAND_MEMORY; + ret = pwrite64(dev_fd, &cmd, sizeof(cmd), offset + RTE_PCI_COMMAND); if (ret != sizeof(cmd)) { RTE_LOG(ERR, EAL, "Cannot write command to PCI config space!\n"); diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index c6606a9bee..6dbaa2ff97 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -33,7 +33,6 @@ #define DLB2_PCI_EXP_DEVCTL2 40 #define DLB2_PCI_LNKCTL2 48 #define DLB2_PCI_SLTCTL2 56 -#define DLB2_PCI_CMD 4 #define DLB2_PCI_EXP_DEVSTA 10 #define DLB2_PCI_EXP_DEVSTA_TRPND 0x20 #define DLB2_PCI_EXP_DEVCTL_BCR_FLR 0x8000 @@ -47,7 +46,6 @@ #define DLB2_PCI_ERR_ROOT_STATUS 0x30 #define DLB2_PCI_ERR_COR_STATUS 0x10 #define DLB2_PCI_ERR_UNCOR_STATUS 0x4 -#define DLB2_PCI_COMMAND_INTX_DISABLE 0x400 #define DLB2_PCI_ACS_CAP 0x4 #define DLB2_PCI_ACS_CTRL 0x6 #define DLB2_PCI_ACS_SV 0x1 @@ -286,7 +284,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) /* clear the PCI command register before issuing the FLR */ - off = DLB2_PCI_CMD; + off = RTE_PCI_COMMAND; cmd = 0; if (rte_pci_write_config(pdev, &cmd, 2, off) != 2) { DLB2_LOG_ERR("[%s()] failed to write the pci command\n", @@ -468,9 +466,9 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) } } - off = DLB2_PCI_CMD; + off = RTE_PCI_COMMAND; if (rte_pci_read_config(pdev, &cmd, 2, off) == 2) { - cmd &= ~DLB2_PCI_COMMAND_INTX_DISABLE; + cmd &= ~RTE_PCI_COMMAND_INTX_DISABLE; if (rte_pci_write_config(pdev, &cmd, 2, off) != 2) { DLB2_LOG_ERR("[%s()] failed to write the pci command\n", __func__); diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index 650dbb7645..8bf60b9fb7 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -37,8 +37,10 @@ extern "C" { #define RTE_PCI_STATUS 0x06 /* 16 bits */ #define RTE_PCI_CAPABILITY_LIST 0x34 /* 32 bits */ -/* PCI Command Register */ -#define RTE_PCI_COMMAND_MASTER 0x4 /* Bus Master Enable */ +/* PCI Command Register (RTE_PCI_COMMAND) */ +#define RTE_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ +#define RTE_PCI_COMMAND_MASTER 0x4 /* Bus Master Enable */ +#define RTE_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ /* PCI Status Register (RTE_PCI_STATUS) */ #define RTE_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */