From patchwork Fri Sep 22 09:37:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Marchand X-Patchwork-Id: 131830 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2FE8A42616; Fri, 22 Sep 2023 11:37:50 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 21B60406B8; Fri, 22 Sep 2023 11:37:50 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mails.dpdk.org (Postfix) with ESMTP id 99AED402DC for ; Fri, 22 Sep 2023 11:37:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1695375468; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3L6AS3AHRPXVfZvexDGVDqkoJm9XSjTn2EnCH8qosk8=; b=XzCD4pGVXqUg++YsU5Yv7uX0mUXo6H6pk0dvncIHgySxzo2a1Q5ryPNYisVdA3PTeVfuQ7 55aPyYfcz4GRIGbiUZa96HNYAmJ3Nh/3QR1nBper48Vu0RfZmNcCumTXFPabcAYRv23M7d z0mOrpReM6FQjA+WAtf+B7Srfxy5res= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-378-bLpJrWJUNfaN9lSUcJ2U0g-1; Fri, 22 Sep 2023 05:37:43 -0400 X-MC-Unique: bLpJrWJUNfaN9lSUcJ2U0g-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 69D03800962; Fri, 22 Sep 2023 09:37:42 +0000 (UTC) Received: from dmarchan.redhat.com (unknown [10.45.224.128]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2B21210005D4; Fri, 22 Sep 2023 09:37:40 +0000 (UTC) From: David Marchand To: dev@dpdk.org Cc: ferruh.yigit@amd.com, thomas@monjalon.net, bruce.richardson@intel.com, konstantin.v.ananyev@yandex.ru, ruifeng.wang@arm.com, zhoumin@loongson.cn, drc@linux.vnet.ibm.com, kda@semihalf.com, roretzla@linux.microsoft.com, Matan Azrad , Viacheslav Ovsiienko , Ori Kam , Suanming Mou Subject: [PATCH 2/2] common/mlx5: use EAL x86 processor identification Date: Fri, 22 Sep 2023 11:37:21 +0200 Message-ID: <20230922093722.2057688-3-david.marchand@redhat.com> In-Reply-To: <20230922093722.2057688-1-david.marchand@redhat.com> References: <20230922093722.2057688-1-david.marchand@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Rather than use an ugly asm thing, use newly introduced EAL x86 API. Signed-off-by: David Marchand --- drivers/common/mlx5/mlx5_common.c | 81 ++++++++----------------------- 1 file changed, 21 insertions(+), 60 deletions(-) diff --git a/drivers/common/mlx5/mlx5_common.c b/drivers/common/mlx5/mlx5_common.c index 0ad14a48c7..99adcd960e 100644 --- a/drivers/common/mlx5/mlx5_common.c +++ b/drivers/common/mlx5/mlx5_common.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -52,29 +53,6 @@ uint8_t haswell_broadwell_cpu; */ #define MLX5_SQ_DB_NC "sq_db_nc" -/* In case this is an x86_64 intel processor to check if - * we should use relaxed ordering. - */ -#ifdef RTE_ARCH_X86_64 -/** - * This function returns processor identification and feature information - * into the registers. - * - * @param eax, ebx, ecx, edx - * Pointers to the registers that will hold cpu information. - * @param level - * The main category of information returned. - */ -static inline void mlx5_cpu_id(unsigned int level, - unsigned int *eax, unsigned int *ebx, - unsigned int *ecx, unsigned int *edx) -{ - __asm__("cpuid\n\t" - : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) - : "0" (level)); -} -#endif - RTE_LOG_REGISTER_DEFAULT(mlx5_common_logtype, NOTICE) /* Head of list of drivers. */ @@ -1246,46 +1224,29 @@ mlx5_common_init(void) RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, LOG) { #ifdef RTE_ARCH_X86_64 - unsigned int broadwell_models[4] = {0x3d, 0x47, 0x4F, 0x56}; - unsigned int haswell_models[4] = {0x3c, 0x3f, 0x45, 0x46}; - unsigned int i, model, family, brand_id, vendor; - unsigned int signature_intel_ebx = 0x756e6547; - unsigned int extended_model; - unsigned int eax = 0; - unsigned int ebx = 0; - unsigned int ecx = 0; - unsigned int edx = 0; - int max_level; - - mlx5_cpu_id(0, &eax, &ebx, &ecx, &edx); - vendor = ebx; - max_level = eax; - if (max_level < 1) { - haswell_broadwell_cpu = 0; + uint8_t broadwell_models[] = {0x3d, 0x47, 0x4f, 0x56}; + uint8_t haswell_models[] = {0x3c, 0x3f, 0x45, 0x46}; + unsigned int i; + uint8_t model; + + if (!rte_cpu_is_x86() || !rte_cpu_x86_is_intel() || rte_cpu_x86_brand() != 0x0 || + rte_cpu_x86_family() != 0x6) + goto out; + + model = rte_cpu_x86_model(); + for (i = 0; i < RTE_DIM(broadwell_models); i++) { + if (model != broadwell_models[i]) + continue; + haswell_broadwell_cpu = 1; return; } - mlx5_cpu_id(1, &eax, &ebx, &ecx, &edx); - model = (eax >> 4) & 0x0f; - family = (eax >> 8) & 0x0f; - brand_id = ebx & 0xff; - extended_model = (eax >> 12) & 0xf0; - /* Check if the processor is Haswell or Broadwell */ - if (vendor == signature_intel_ebx) { - if (family == 0x06) - model += extended_model; - if (brand_id == 0 && family == 0x6) { - for (i = 0; i < RTE_DIM(broadwell_models); i++) - if (model == broadwell_models[i]) { - haswell_broadwell_cpu = 1; - return; - } - for (i = 0; i < RTE_DIM(haswell_models); i++) - if (model == haswell_models[i]) { - haswell_broadwell_cpu = 1; - return; - } - } + for (i = 0; i < RTE_DIM(haswell_models); i++) { + if (model != haswell_models[i]) + continue; + haswell_broadwell_cpu = 1; + return; } +out: #endif haswell_broadwell_cpu = 0; }