[v5,5/5] doc: add generic flow doc for ice PMD
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Commit Message
Add some document about how to use rte_flow on ice PMD.
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
doc/guides/nics/ice.rst | 45 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
Comments
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, September 26, 2023 7:30 PM
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Zeng, ZhichaoX <zhichaox.zeng@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>
> Subject: [PATCH v5 5/5] doc: add generic flow doc for ice PMD
>
> Add some document about how to use rte_flow on ice PMD.
>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> doc/guides/nics/ice.rst | 45
> +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
Series-Reviewed-by: Zhichao Zeng <zhichaox.zeng@intel.com>
> -----Original Message-----
> From: Zeng, ZhichaoX <zhichaox.zeng@intel.com>
> Sent: Wednesday, September 27, 2023 10:42 AM
> To: Zhang, Qi Z <qi.z.zhang@intel.com>; Yang, Qiming
> <qiming.yang@intel.com>
> Cc: dev@dpdk.org
> Subject: RE: [PATCH v5 5/5] doc: add generic flow doc for ice PMD
>
> > -----Original Message-----
> > From: Zhang, Qi Z <qi.z.zhang@intel.com>
> > Sent: Tuesday, September 26, 2023 7:30 PM
> > To: Yang, Qiming <qiming.yang@intel.com>
> > Cc: Zeng, ZhichaoX <zhichaox.zeng@intel.com>; dev@dpdk.org; Zhang, Qi
> > Z <qi.z.zhang@intel.com>
> > Subject: [PATCH v5 5/5] doc: add generic flow doc for ice PMD
> >
> > Add some document about how to use rte_flow on ice PMD.
> >
> > Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> > ---
> > doc/guides/nics/ice.rst | 45
> > +++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 45 insertions(+)
> >
> Series-Reviewed-by: Zhichao Zeng <zhichaox.zeng@intel.com>
Applied to dpdk-next-net-intel.
Thanks
Qi
26/09/2023 13:29, Qi Zhang:
> +Generic Flow Support
> +~~~~~~~~~~~~~~~~~~~~
> +
> +The ice PMD provides support for the Generic Flow API (RTE_FLOW), enabling
> +users to offload various flow classification tasks to the E810 NIC.
> +The E810 NIC's packet processing pipeline consists of the following stages:
> +
> +Switch: Supports exact match and limited wildcard matching with a large flow
> +capacity.
> +
> +ACL: Supports wildcard matching with a smaller flow capacity (DCF mode only).
> +
> +FDIR: Supports exact match with a large flow capacity (PF mode only).
> +
> +Hash: Supports RSS (PF mode only)
> +
> +The ice PMD utilizes the ice_flow_engine structure to represent each of these
> +stages and leverages the rte_flow rule's ``group`` attribute for selecting the
> +appropriate engine for Switch, ACL, and FDIR operations:
> +
> +Group 0 maps to Switch
> +Group 1 maps to ACL
> +Group 2 maps to FDIR
> +
> +In the case of RSS, it will only be selected if a ``RTE_FLOW_ACTION_RSS`` action
> +is targeted to no queue group, and the group attribute is ignored.
> +
> +For each engine, a list of supported patterns is maintained in a global array
> +named ``ice_<engine>_supported_pattern``. The Ice PMD will reject any rule with
> +a pattern that is not included in the supported list.
Why not choosing the right engine automatically?
You are defining an API (group number specialization)
which is specific to this driver.
Don't you care about portability of DPDK applications?
Sorry for late response... comment inline
> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: Friday, October 13, 2023 9:17 PM
> To: Zhang, Qi Z <qi.z.zhang@intel.com>
> Cc: Yang, Qiming <qiming.yang@intel.com>; Zeng, ZhichaoX
> <zhichaox.zeng@intel.com>; dev@dpdk.org; orika@nvidia.com;
> david.marchand@redhat.com; Mcnamara, John
> <john.mcnamara@intel.com>
> Subject: Re: [PATCH v5 5/5] doc: add generic flow doc for ice PMD
>
> 26/09/2023 13:29, Qi Zhang:
> > +Generic Flow Support
> > +~~~~~~~~~~~~~~~~~~~~
> > +
> > +The ice PMD provides support for the Generic Flow API (RTE_FLOW),
> > +enabling users to offload various flow classification tasks to the E810 NIC.
> > +The E810 NIC's packet processing pipeline consists of the following stages:
> > +
> > +Switch: Supports exact match and limited wildcard matching with a
> > +large flow capacity.
> > +
> > +ACL: Supports wildcard matching with a smaller flow capacity (DCF mode
> only).
> > +
> > +FDIR: Supports exact match with a large flow capacity (PF mode only).
> > +
> > +Hash: Supports RSS (PF mode only)
> > +
> > +The ice PMD utilizes the ice_flow_engine structure to represent each
> > +of these stages and leverages the rte_flow rule's ``group`` attribute
> > +for selecting the appropriate engine for Switch, ACL, and FDIR operations:
> > +
> > +Group 0 maps to Switch
> > +Group 1 maps to ACL
> > +Group 2 maps to FDIR
> > +
> > +In the case of RSS, it will only be selected if a
> > +``RTE_FLOW_ACTION_RSS`` action is targeted to no queue group, and the
> group attribute is ignored.
> > +
> > +For each engine, a list of supported patterns is maintained in a
> > +global array named ``ice_<engine>_supported_pattern``. The Ice PMD
> > +will reject any rule with a pattern that is not included in the supported list.
>
> Why not choosing the right engine automatically?
>
> You are defining an API (group number specialization) which is specific to this
> driver.
OK, let me know if my understanding is correct or not.
I think the implementation somehow broken below description in rte_flow document.
"Groups are not linked by default, so the logical hierarchy of groups must be explicitly defined by flow rules themselves in each group using the JUMP action to define the next group to redirect to. "
Could a fix like below works ? Or any better suggestion?
1. Initially, map the switch to group 0, as it represents the first stage in the hardware pipeline.
2. For ACL usage, users should create a rule in group 0 with a JUMP action that includes an arbitrarily group ID. then, the driver will associate this group with ACL engine.
3. For FDIR usage, users should create a rule within group <ACL> with a JUMP action, utilizing a distinct group ID. then, the driver will link this group with FDIR engine.
Thanks
Qi
> Don't you care about portability of DPDK applications?
>
@@ -301,6 +301,51 @@ The DCF PMD needs to advertise and acquire DCF capability which allows DCF to
send AdminQ commands that it would like to execute over to the PF and receive
responses for the same from PF.
+Generic Flow Support
+~~~~~~~~~~~~~~~~~~~~
+
+The ice PMD provides support for the Generic Flow API (RTE_FLOW), enabling
+users to offload various flow classification tasks to the E810 NIC.
+The E810 NIC's packet processing pipeline consists of the following stages:
+
+Switch: Supports exact match and limited wildcard matching with a large flow
+capacity.
+
+ACL: Supports wildcard matching with a smaller flow capacity (DCF mode only).
+
+FDIR: Supports exact match with a large flow capacity (PF mode only).
+
+Hash: Supports RSS (PF mode only)
+
+The ice PMD utilizes the ice_flow_engine structure to represent each of these
+stages and leverages the rte_flow rule's ``group`` attribute for selecting the
+appropriate engine for Switch, ACL, and FDIR operations:
+
+Group 0 maps to Switch
+Group 1 maps to ACL
+Group 2 maps to FDIR
+
+In the case of RSS, it will only be selected if a ``RTE_FLOW_ACTION_RSS`` action
+is targeted to no queue group, and the group attribute is ignored.
+
+For each engine, a list of supported patterns is maintained in a global array
+named ``ice_<engine>_supported_pattern``. The Ice PMD will reject any rule with
+a pattern that is not included in the supported list.
+
+One notable feature is the ice PMD's ability to leverage the Raw pattern,
+enabling protocol-agnostic flow offloading. Here is an example of creating
+a rule that matches an IPv4 destination address of 1.2.3.4 and redirects it to
+queue 3 using a raw pattern:
+
+flow create 0 ingress group 2 pattern raw \
+pattern spec \
+00000000000000000000000008004500001400004000401000000000000001020304 \
+pattern mask \
+000000000000000000000000000000000000000000000000000000000000ffffffff \
+end actions queue index 3 / mark id 3 / end
+
+Currently, raw pattern support is limited to the FDIR and Hash engines.
+
Additional Options
++++++++++++++++++