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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS2PEPF0000343E.mail.protection.outlook.com (10.167.18.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.14 via Frontend Transport; Mon, 9 Oct 2023 16:37:02 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 9 Oct 2023 09:36:44 -0700 Received: from pegasus01.mtr.labs.mlnx (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 9 Oct 2023 09:36:41 -0700 From: Alexander Kozyrev To: CC: , , , , , Subject: [PATCH 4/5] net/mlx5/hws: remove csum check from L3 ok check Date: Mon, 9 Oct 2023 19:36:16 +0300 Message-ID: <20231009163617.3999365-5-akozyrev@nvidia.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20231009163617.3999365-1-akozyrev@nvidia.com> References: <20231009163617.3999365-1-akozyrev@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343E:EE_|BL1PR12MB5971:EE_ X-MS-Office365-Filtering-Correlation-Id: 21efe41a-f908-4090-0986-08dbc8e5f76f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2023 16:37:02.5653 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21efe41a-f908-4090-0986-08dbc8e5f76f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5971 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Michael Baum This patch changes the integrity item behavior for HW steering. Old behavior: the "ipv4_csum_ok" checks only IPv4 checksum and "l3_ok" checks everything is ok including IPv4 checksum. New behavior: the "l3_ok" checks everything is ok excluding IPv4 checksum. This change enables matching "l3_ok" in IPv6 packets since for IPv6 packets "ipv4_csum_ok" is always miss. For SW steering the old behavior is kept as same as for L4 ok. Signed-off-by: Michael Baum --- doc/guides/nics/mlx5.rst | 19 ++++++++++++------- drivers/net/mlx5/hws/mlx5dr_definer.c | 6 ++---- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 26cf310e8e..ddec84a9bb 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -667,18 +667,23 @@ Limitations - Integrity: - - Integrity offload is enabled starting from **ConnectX-6 Dx**. - Verification bits provided by the hardware are ``l3_ok``, ``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``. - ``level`` value 0 references outer headers. - Negative integrity item verification is not supported. - - Multiple integrity items not supported in a single flow rule. - - Flow rule items supplied by application must explicitly specify network headers referred by integrity item. - For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits, reference to L4 network header, - TCP or UDP, must be in the rule pattern as well:: + - With SW steering (``dv_flow_en=1``) + - Integrity offload is enabled starting from **ConnectX-6 Dx**. + - Multiple integrity items not supported in a single flow rule. + - Flow rule items supplied by application must explicitly specify network headers referred by integrity item. + For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits, reference to L4 network header, + TCP or UDP, must be in the rule pattern as well:: - flow create 0 ingress pattern integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end … + flow create 0 ingress pattern integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end … - flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec l4_ok / eth / ipv4 proto is udp / end … + flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec l4_ok / eth / ipv4 proto is udp / end … + + - With HW steering (``dv_flow_en=2``) + - The ``l3_ok`` field represents all L3 checks, but nothing about whether IPv4 checksum ok. + - The ``l4_ok`` field represents all L4 checks including L4 checksum ok. - Connection tracking: diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index b2c0655790..84d15a41df 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -384,10 +384,8 @@ mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc, uint32_t ok1_bits = 0; if (v->l3_ok) - ok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) | - BIT(MLX5DR_DEFINER_OKS1_SECOND_IPV4_CSUM_OK) : - BIT(MLX5DR_DEFINER_OKS1_FIRST_L3_OK) | - BIT(MLX5DR_DEFINER_OKS1_FIRST_IPV4_CSUM_OK); + ok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) : + BIT(MLX5DR_DEFINER_OKS1_FIRST_L3_OK); if (v->ipv4_csum_ok) ok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_IPV4_CSUM_OK) :