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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF0002BA4B.mail.protection.outlook.com (10.167.242.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6933.15 via Frontend Transport; Mon, 23 Oct 2023 21:07:58 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 23 Oct 2023 14:07:54 -0700 Received: from pegasus01.mtr.labs.mlnx (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 23 Oct 2023 14:07:47 -0700 From: Alexander Kozyrev To: CC: , , , , , Subject: [PATCH v2 4/7] doc: add PMD ptype item limitations Date: Tue, 24 Oct 2023 00:07:04 +0300 Message-ID: <20231023210707.1344241-5-akozyrev@nvidia.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20231023210707.1344241-1-akozyrev@nvidia.com> References: <20231009163617.3999365-1-akozyrev@nvidia.com> <20231023210707.1344241-1-akozyrev@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4B:EE_|SA1PR12MB6870:EE_ X-MS-Office365-Filtering-Correlation-Id: a6c40c0e-f788-484f-53a1-08dbd40c223e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2023 21:07:58.0856 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a6c40c0e-f788-484f-53a1-08dbd40c223e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6870 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Michael Baum Add limitations for ptype item support in "mlx5.rst" file. Signed-off-by: Michael Baum --- doc/guides/nics/features/mlx5.ini | 1 + doc/guides/nics/mlx5.rst | 15 +++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini index fc67415c6c..e3927ab4df 100644 --- a/doc/guides/nics/features/mlx5.ini +++ b/doc/guides/nics/features/mlx5.ini @@ -86,6 +86,7 @@ nsh = Y nvgre = Y port_id = Y port_representor = Y +ptype = Y quota = Y tag = Y tcp = Y diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 7086f3d1d4..c9e74948cc 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -646,6 +646,21 @@ Limitations - When using HWS flow engine (``dv_flow_en`` = 2), only meter mark action is supported. +- Ptype: + + - Only supports HW steering (``dv_flow_en=2``). + - The supported values are: + L2: ``RTE_PTYPE_L2_ETHER``, ``RTE_PTYPE_L2_ETHER_VLAN``, ``RTE_PTYPE_L2_ETHER_QINQ`` + L3: ``RTE_PTYPE_L3_IPV4``, ``RTE_PTYPE_L3_IPV6`` + L4: ``RTE_PTYPE_L4_TCP``, ``RTE_PTYPE_L4_UDP``, ``RTE_PTYPE_L4_ICMP`` + and their ``RTE_PTYPE_INNER_XXX`` counterparts as well as ``RTE_PTYPE_TUNNEL_ESP``. + Any other values are not supported. Using them as a value will cause unexpected behavior. + - Matching on both outer and inner IP fragmented is supported using ``RTE_PTYPE_L4_FRAG`` and + ``RTE_PTYPE_INNER_L4_FRAG`` values. They are not part of L4 types, so they should be provided + explicitly as a mask value during pattern template creation. Providing ``RTE_PTYPE_L4_MASK`` + during pattern template creation and ``RTE_PTYPE_L4_FRAG`` during flow rule creation + will cause unexpected behavior. + - Integrity: - Integrity offload is enabled starting from **ConnectX-6 Dx**.