From patchwork Fri Oct 27 14:23:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ciara Power X-Patchwork-Id: 133504 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A4D2743217; Fri, 27 Oct 2023 16:23:15 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 723A840291; Fri, 27 Oct 2023 16:23:15 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id 3AE9640279; Fri, 27 Oct 2023 16:23:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698416593; x=1729952593; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=GbYc2aJ//s1L7Ki9hf3PMWDBOUQv64T5mUtjT2UY1mg=; b=KK4Ho3AXA/GclxAd1p4gjZPirEnq977kyjpfyTEGLdPq2KCAH8yuop1n T4vuWguFZSd82fVRisSO7j3Vw5dr6xlpkDoQzQDe8QfwnJMAkZB9giV77 85D1c6G6ZI8pBbrX97sdpMf+GLF6Ds26ElgDF125zFeQ3LAeRocPyuEK4 J5omNRr28s+x4k1WJyUAp+h4f1rAqDar9gp+71Pz//pr9BrtUj5XoHsuR wWYZD2ysmNuMu82SqjNSbbrYncd9AIioEa0PBLY+4/EUu+ElphEqS5Z2w iwSr/303jn0dSicrKVnvqYrT7oz6roiETcmpYJ3j95X7KbxR+6fYnkAdS A==; X-IronPort-AV: E=McAfee;i="6600,9927,10876"; a="386667603" X-IronPort-AV: E=Sophos;i="6.03,256,1694761200"; d="scan'208";a="386667603" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2023 07:23:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,256,1694761200"; d="scan'208";a="811043" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.80]) by orviesa002.jf.intel.com with ESMTP; 27 Oct 2023 07:22:34 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , brian.dooley@intel.com, stable@dpdk.org, Kai Ji Subject: [PATCH] crypto/qat: fix build when no openssl exists Date: Fri, 27 Oct 2023 14:23:05 +0000 Message-Id: <20231027142305.2328017-1-ciara.power@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Previously some compilation errors existed when no openssl was installed on the system, and intel-ipsec-mb was installed, due to missing headers and macros. This patch fixes the issue by adding in extra ifdefs around openssl specific code paths, and by adding the relevant macros explicitly in QAT code so it does not depend on openssl at all. Fixes: ca0ba0e48129 ("crypto/qat: default to IPsec MB for computations") Cc: brian.dooley@intel.com Cc: stable@dpdk.org Signed-off-by: Ciara Power Acked-by: Kai Ji > Acked-by: Brian Dooley --- drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 2 ++ drivers/crypto/qat/qat_sym.c | 2 ++ drivers/crypto/qat/qat_sym.h | 6 ++++-- drivers/crypto/qat/qat_sym_session.c | 13 ++++++------- drivers/crypto/qat/qat_sym_session.h | 3 +++ 5 files changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h index 37647374d5..eebf2e6eb8 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h @@ -24,6 +24,7 @@ (ICP_QAT_FW_COMN_STATUS_FLAG_OK == \ ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(resp->comn_hdr.comn_status)) +#ifdef RTE_QAT_OPENSSL static __rte_always_inline int op_bpi_cipher_decrypt(uint8_t *src, uint8_t *dst, uint8_t *iv, int ivlen, int srclen, @@ -48,6 +49,7 @@ op_bpi_cipher_decrypt(uint8_t *src, uint8_t *dst, QAT_DP_LOG(ERR, "libcrypto ECB cipher decrypt for BPI IV failed"); return -EINVAL; } +#endif static __rte_always_inline uint32_t qat_bpicipher_preprocess(struct qat_sym_session *ctx, diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c index 936c2615e4..6e03bde841 100644 --- a/drivers/crypto/qat/qat_sym.c +++ b/drivers/crypto/qat/qat_sym.c @@ -2,7 +2,9 @@ * Copyright(c) 2015-2023 Intel Corporation */ +#ifdef RTE_QAT_OPENSSL #include +#endif #include #include diff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h index d19cadde86..b4e19e3015 100644 --- a/drivers/crypto/qat/qat_sym.h +++ b/drivers/crypto/qat/qat_sym.h @@ -9,7 +9,9 @@ #include #ifdef BUILD_QAT_SYM +#ifdef RTE_QAT_OPENSSL #include +#endif #include #include "qat_common.h" @@ -133,6 +135,7 @@ uint16_t qat_sym_dequeue_burst(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops); +#ifdef RTE_QAT_OPENSSL /** Encrypt a single partial block * Depends on openssl libcrypto * Uses ECB+XOR to do CFB encryption, same result, more performant @@ -161,8 +164,7 @@ bpi_cipher_encrypt(uint8_t *src, uint8_t *dst, QAT_DP_LOG(ERR, "libcrypto ECB cipher encrypt failed"); return -EINVAL; } - -#ifndef RTE_QAT_OPENSSL +#else static __rte_always_inline void bpi_cipher_ipsec(uint8_t *src, uint8_t *dst, uint8_t *iv, int srclen, uint64_t *expkey, IMB_MGR *m, uint8_t docsis_key_len) diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index 7831a677d0..9f4f6c3d93 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -4,10 +4,12 @@ #define OPENSSL_API_COMPAT 0x10100000L +#ifdef RTE_QAT_OPENSSL #include /* Needed to calculate pre-compute values */ #include /* Needed to calculate pre-compute values */ #include /* Needed to calculate pre-compute values */ #include /* Needed for bpi runt block processing */ +#endif #ifndef RTE_QAT_OPENSSL #ifndef RTE_ARCH_ARM @@ -1272,24 +1274,21 @@ static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg) { switch (qat_hash_alg) { case ICP_QAT_HW_AUTH_ALGO_SHA1: - return SHA_CBLOCK; case ICP_QAT_HW_AUTH_ALGO_SHA224: - return SHA256_CBLOCK; case ICP_QAT_HW_AUTH_ALGO_SHA256: - return SHA256_CBLOCK; + return QAT_SHA_CBLOCK; case ICP_QAT_HW_AUTH_ALGO_SHA384: - return SHA512_CBLOCK; case ICP_QAT_HW_AUTH_ALGO_SHA512: - return SHA512_CBLOCK; + return QAT_SHA512_CBLOCK; case ICP_QAT_HW_AUTH_ALGO_GALOIS_128: return 16; case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC: return ICP_QAT_HW_AES_BLK_SZ; case ICP_QAT_HW_AUTH_ALGO_MD5: - return MD5_CBLOCK; + return QAT_MD5_CBLOCK; case ICP_QAT_HW_AUTH_ALGO_DELIMITER: /* return maximum block size in this case */ - return SHA512_CBLOCK; + return QAT_SHA512_CBLOCK; case ICP_QAT_HW_AUTH_ALGO_SM3: return QAT_SM3_BLOCK_SIZE; default: diff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h index 674a62ee12..9209e2e8df 100644 --- a/drivers/crypto/qat/qat_sym_session.h +++ b/drivers/crypto/qat/qat_sym_session.h @@ -69,6 +69,9 @@ (!!((flags) & (flag))) #define QAT_SM3_BLOCK_SIZE 64 +#define QAT_SHA_CBLOCK 64 +#define QAT_SHA512_CBLOCK 128 +#define QAT_MD5_CBLOCK 64 enum qat_sym_proto_flag { QAT_CRYPTO_PROTO_FLAG_NONE = 0,