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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by MN1PEPF0000ECDA.mail.protection.outlook.com (10.167.242.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6954.19 via Frontend Transport; Tue, 31 Oct 2023 12:26:04 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 31 Oct 2023 05:25:49 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 31 Oct 2023 05:25:46 -0700 From: Gregory Etelson To: CC: , , , "Hamdan Igbaria" , Alex Vesker , Matan Azrad , Viacheslav Ovsiienko , Ori Kam , Suanming Mou Subject: [PATCH 05/10] net/mlx5/hws: support ASO first hit action Date: Tue, 31 Oct 2023 14:25:07 +0200 Message-ID: <20231031122512.434686-6-getelson@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231031122512.434686-1-getelson@nvidia.com> References: <20231031122512.434686-1-getelson@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECDA:EE_|DS7PR12MB6095:EE_ X-MS-Office365-Filtering-Correlation-Id: 1dc81f5d-054d-44e2-eb2d-08dbda0c8d77 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2023 12:26:04.8778 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1dc81f5d-054d-44e2-eb2d-08dbda0c8d77 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECDA.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6095 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Hamdan Igbaria Support ASO first hit action. This action allows tracking if a rule gets hit by a packet. Signed-off-by: Hamdan Igbaria Reviewed-by: Alex Vesker Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 5 +++++ drivers/net/mlx5/hws/mlx5dr.h | 25 +++++++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_action.c | 33 ++++++++++++++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_debug.c | 1 + 4 files changed, 64 insertions(+) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 793fc1a674..40e461cb82 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3541,6 +3541,7 @@ enum { MLX5_ASO_CT_NUM_PER_OBJ = 1, MLX5_ASO_METER_NUM_PER_OBJ = 2, MLX5_ASO_IPSEC_NUM_PER_OBJ = 1, + MLX5_ASO_FIRST_HIT_NUM_PER_OBJ = 512, }; struct mlx5_ifc_stc_ste_param_execute_aso_bits { @@ -5371,6 +5372,10 @@ enum { MLX5_FLOW_COLOR_UNDEFINED, }; +enum { + MLX5_ASO_FIRST_HIT_SET = 1, +}; + /* Maximum value of srTCM & trTCM metering parameters. */ #define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F)) #define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF) diff --git a/drivers/net/mlx5/hws/mlx5dr.h b/drivers/net/mlx5/hws/mlx5dr.h index e425a8803a..e7d89ad7ec 100644 --- a/drivers/net/mlx5/hws/mlx5dr.h +++ b/drivers/net/mlx5/hws/mlx5dr.h @@ -47,6 +47,7 @@ enum mlx5dr_action_type { MLX5DR_ACTION_TYP_ASO_METER, MLX5DR_ACTION_TYP_ASO_CT, MLX5DR_ACTION_TYP_ASO_IPSEC, + MLX5DR_ACTION_TYP_ASO_FIRST_HIT, MLX5DR_ACTION_TYP_CRYPTO_ENCRYPT, MLX5DR_ACTION_TYP_CRYPTO_DECRYPT, MLX5DR_ACTION_TYP_DEST_ROOT, @@ -256,6 +257,11 @@ struct mlx5dr_rule_action { uint32_t offset; } aso_ipsec; + struct { + uint32_t offset; + bool set; + } aso_first_hit; + struct { uint32_t offset; } crypto; @@ -714,6 +720,25 @@ mlx5dr_action_create_aso_ipsec(struct mlx5dr_context *ctx, uint8_t return_reg_id, uint32_t flags); +/* Create direct rule ASO FIRST HIT action. + * + * @param[in] ctx + * The context in which the new action will be created. + * @param[in] devx_obj + * The DEVX ASO object. + * @param[in] return_reg_id + * When a packet hits a flow connected to this object, a flag is set indicating this event, + * copy the original value of this flag into this reg_id. + * @param[in] flags + * Action creation flags. (enum mlx5dr_action_flags) + * @return pointer to mlx5dr_action on success NULL otherwise. + */ +struct mlx5dr_action * +mlx5dr_action_create_aso_first_hit(struct mlx5dr_context *ctx, + struct mlx5dr_devx_obj *devx_obj, + uint8_t return_reg_id, + uint32_t flags); + /* Create direct rule pop vlan action. * @param[in] ctx * The context in which the new action will be created. diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c index f8de3d8d98..fe9c39b207 100644 --- a/drivers/net/mlx5/hws/mlx5dr_action.c +++ b/drivers/net/mlx5/hws/mlx5dr_action.c @@ -7,6 +7,7 @@ #define WIRE_PORT 0xFFFF #define MLX5DR_ACTION_METER_INIT_COLOR_OFFSET 1 +#define MLX5DR_ACTION_ASO_FIRST_HIT_SET_OFFSET 9 /* This is the maximum allowed action order for each table type: * TX: POP_VLAN, CTR, ASO, PUSH_VLAN, MODIFY, ENCAP, TRAILER, ENCRYPT, @@ -29,6 +30,7 @@ static const uint32_t action_order_arr[MLX5DR_TABLE_TYPE_MAX][MLX5DR_ACTION_TYP_ BIT(MLX5DR_ACTION_TYP_ASO_METER), BIT(MLX5DR_ACTION_TYP_ASO_CT), BIT(MLX5DR_ACTION_TYP_ASO_IPSEC), + BIT(MLX5DR_ACTION_TYP_ASO_FIRST_HIT), BIT(MLX5DR_ACTION_TYP_PUSH_VLAN), BIT(MLX5DR_ACTION_TYP_PUSH_VLAN), BIT(MLX5DR_ACTION_TYP_MODIFY_HDR), @@ -49,6 +51,7 @@ static const uint32_t action_order_arr[MLX5DR_TABLE_TYPE_MAX][MLX5DR_ACTION_TYP_ BIT(MLX5DR_ACTION_TYP_ASO_METER), BIT(MLX5DR_ACTION_TYP_ASO_CT), BIT(MLX5DR_ACTION_TYP_ASO_IPSEC), + BIT(MLX5DR_ACTION_TYP_ASO_FIRST_HIT), BIT(MLX5DR_ACTION_TYP_PUSH_VLAN), BIT(MLX5DR_ACTION_TYP_PUSH_VLAN), BIT(MLX5DR_ACTION_TYP_MODIFY_HDR), @@ -73,6 +76,7 @@ static const uint32_t action_order_arr[MLX5DR_TABLE_TYPE_MAX][MLX5DR_ACTION_TYP_ BIT(MLX5DR_ACTION_TYP_ASO_METER), BIT(MLX5DR_ACTION_TYP_ASO_CT), BIT(MLX5DR_ACTION_TYP_ASO_IPSEC), + BIT(MLX5DR_ACTION_TYP_ASO_FIRST_HIT), BIT(MLX5DR_ACTION_TYP_PUSH_VLAN), BIT(MLX5DR_ACTION_TYP_PUSH_VLAN), BIT(MLX5DR_ACTION_TYP_MODIFY_HDR), @@ -672,6 +676,13 @@ static void mlx5dr_action_fill_stc_attr(struct mlx5dr_action *action, attr->aso.devx_obj_id = obj->id; attr->aso.return_reg_id = action->aso.return_reg_id; break; + case MLX5DR_ACTION_TYP_ASO_FIRST_HIT: + attr->action_offset = MLX5DR_ACTION_OFFSET_DW6; + attr->action_type = MLX5_IFC_STC_ACTION_TYPE_ASO; + attr->aso.aso_type = ASO_OPC_MOD_FLOW_HIT; + attr->aso.devx_obj_id = obj->id; + attr->aso.return_reg_id = action->aso.return_reg_id; + break; case MLX5DR_ACTION_TYP_VPORT: attr->action_offset = MLX5DR_ACTION_OFFSET_HIT; attr->action_type = MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT; @@ -1123,6 +1134,16 @@ mlx5dr_action_create_aso_ipsec(struct mlx5dr_context *ctx, devx_obj, return_reg_id, flags); } +struct mlx5dr_action * +mlx5dr_action_create_aso_first_hit(struct mlx5dr_context *ctx, + struct mlx5dr_devx_obj *devx_obj, + uint8_t return_reg_id, + uint32_t flags) +{ + return mlx5dr_action_create_aso(ctx, MLX5DR_ACTION_TYP_ASO_FIRST_HIT, + devx_obj, return_reg_id, flags); +} + struct mlx5dr_action * mlx5dr_action_create_counter(struct mlx5dr_context *ctx, struct mlx5dr_devx_obj *obj, @@ -2185,6 +2206,7 @@ static void mlx5dr_action_destroy_hws(struct mlx5dr_action *action) case MLX5DR_ACTION_TYP_ASO_METER: case MLX5DR_ACTION_TYP_ASO_CT: case MLX5DR_ACTION_TYP_ASO_IPSEC: + case MLX5DR_ACTION_TYP_ASO_FIRST_HIT: case MLX5DR_ACTION_TYP_PUSH_VLAN: case MLX5DR_ACTION_TYP_CRYPTO_ENCRYPT: case MLX5DR_ACTION_TYP_CRYPTO_DECRYPT: @@ -2601,6 +2623,15 @@ mlx5dr_action_setter_aso(struct mlx5dr_actions_apply_data *apply, offset = rule_action->aso_ipsec.offset / MLX5_ASO_IPSEC_NUM_PER_OBJ; exe_aso_ctrl = 0; break; + case MLX5DR_ACTION_TYP_ASO_FIRST_HIT: + /* exe_aso_ctrl FIRST HIT format: + * [STC only and reserved bits 22b][set 1b][offset 9b] + */ + offset = rule_action->aso_first_hit.offset / MLX5_ASO_FIRST_HIT_NUM_PER_OBJ; + exe_aso_ctrl = rule_action->aso_first_hit.offset % MLX5_ASO_FIRST_HIT_NUM_PER_OBJ; + exe_aso_ctrl |= rule_action->aso_first_hit.set << + MLX5DR_ACTION_ASO_FIRST_HIT_SET_OFFSET; + break; default: DR_LOG(ERR, "Unsupported ASO action type: %d", rule_action->action->type); rte_errno = ENOTSUP; @@ -2803,6 +2834,8 @@ int mlx5dr_action_template_process(struct mlx5dr_action_template *at) case MLX5DR_ACTION_TYP_ASO_METER: case MLX5DR_ACTION_TYP_ASO_CT: case MLX5DR_ACTION_TYP_ASO_IPSEC: + case MLX5DR_ACTION_TYP_ASO_FIRST_HIT: + /* Double ASO action */ setter = mlx5dr_action_setter_find_first(last_setter, ASF_DOUBLE); setter->flags |= ASF_DOUBLE; setter->set_double = &mlx5dr_action_setter_aso; diff --git a/drivers/net/mlx5/hws/mlx5dr_debug.c b/drivers/net/mlx5/hws/mlx5dr_debug.c index 976a1993e3..552dba5e63 100644 --- a/drivers/net/mlx5/hws/mlx5dr_debug.c +++ b/drivers/net/mlx5/hws/mlx5dr_debug.c @@ -24,6 +24,7 @@ const char *mlx5dr_debug_action_type_str[] = { [MLX5DR_ACTION_TYP_ASO_METER] = "ASO_METER", [MLX5DR_ACTION_TYP_ASO_CT] = "ASO_CT", [MLX5DR_ACTION_TYP_ASO_IPSEC] = "ASO_IPSEC", + [MLX5DR_ACTION_TYP_ASO_FIRST_HIT] = "ASO_FIRST_HIT", [MLX5DR_ACTION_TYP_DEST_ROOT] = "DEST_ROOT", [MLX5DR_ACTION_TYP_DEST_ARRAY] = "DEST_ARRAY", [MLX5DR_ACTION_TYP_CRYPTO_ENCRYPT] = "CRYPTO_ENCRYPT",