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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by MWH0EPF000971E6.mail.protection.outlook.com (10.167.243.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6954.19 via Frontend Transport; Tue, 31 Oct 2023 14:28:30 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 31 Oct 2023 07:28:08 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 31 Oct 2023 07:28:06 -0700 From: Dariusz Sosnowski To: Matan Azrad , Viacheslav Ovsiienko , Ori Kam , Suanming Mou CC: , Raslan Darawsheh Subject: [PATCH 7/8] net/mlx5: sort port spawn data with uplink ports first Date: Tue, 31 Oct 2023 16:27:32 +0200 Message-ID: <20231031142733.2009166-8-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231031142733.2009166-1-dsosnowski@nvidia.com> References: <20231031142733.2009166-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E6:EE_|CH3PR12MB8535:EE_ X-MS-Office365-Filtering-Correlation-Id: a9b1553b-42bd-4928-172c-08dbda1da7a1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2023 14:28:30.2753 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a9b1553b-42bd-4928-172c-08dbda1da7a1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8535 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch changes the behavior of the comparator used to sort mlx5_dev_spawn_data structures, to put them in a more user friendly order Before this patch, ports were sorted assuming there is only a single master port. It resulted in an order where master port first comes second, then representors in ascending order of IDs. This approach however is not desirable with devices configured for Multiport E-Switch, since uplink ports which do not correspond to the owning PCI device are representors as well and they will be mixed with VF/SF representors. To change that, this patch amends the comparator to force uplink ports to be first. If there are many uplink ports, the master port will come first and the rest will be sorted by port index. Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/linux/mlx5_os.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 8ddf38288e..07f31de5ae 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1797,9 +1797,15 @@ mlx5_dev_spawn_data_cmp(const void *a, const void *b) &((const struct mlx5_dev_spawn_data *)a)->info; const struct mlx5_switch_info *si_b = &((const struct mlx5_dev_spawn_data *)b)->info; + int uplink_a = si_a->name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK; + int uplink_b = si_b->name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK; int ret; - /* Master device first. */ + /* Uplink ports first. */ + ret = uplink_b - uplink_a; + if (ret) + return ret; + /* Then master devices. */ ret = si_b->master - si_a->master; if (ret) return ret;