net/cpfl: fix coverity issues

Message ID 20231106095933.962565-1-wenjing.qiao@intel.com (mailing list archive)
State Accepted, archived
Delegated to: Qi Zhang
Headers
Series net/cpfl: fix coverity issues |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/github-robot: build success github build: passed
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-compile-amd64-testing success Testing PASS
ci/iol-sample-apps-testing success Testing PASS
ci/iol-unit-amd64-testing success Testing PASS
ci/iol-unit-arm64-testing success Testing PASS
ci/iol-compile-arm64-testing success Testing PASS

Commit Message

Wenjing Qiao Nov. 6, 2023, 9:59 a.m. UTC
  From: Wenjing Qiao <wenjing.qiao@intel.com>

Fix integer handling issues, tainted_scalar issues, uninit issues,
overrun issues and control flow issues reported by coverity scan.

Coverity issue: 403259
Coverity issue: 403261
Coverity issue: 403266
Coverity issue: 403267
Coverity issue: 403271
Coverity issue: 403274
Fixes: db042ef09d26 ("net/cpfl: implement FXP rule creation and destroying")
Fixes: 03f976012304 ("net/cpfl: adapt FXP to flow engine")

Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
 drivers/net/cpfl/cpfl_ethdev.c          |  2 +-
 drivers/net/cpfl/cpfl_flow_engine_fxp.c | 12 +++---------
 drivers/net/cpfl/cpfl_fxp_rule.c        |  6 +++---
 drivers/net/cpfl/cpfl_rules.c           |  3 +--
 4 files changed, 8 insertions(+), 15 deletions(-)
  

Comments

Qi Zhang Nov. 7, 2023, 12:18 a.m. UTC | #1
> -----Original Message-----
> From: Qiao, Wenjing <wenjing.qiao@intel.com>
> Sent: Monday, November 6, 2023 6:00 PM
> To: Wu, Jingjing <jingjing.wu@intel.com>; Xing, Beilei <beilei.xing@intel.com>;
> Zhang, Qi Z <qi.z.zhang@intel.com>
> Cc: dev@dpdk.org; Zhang, Yuying <yuying.zhang@intel.com>; Qiao, Wenjing
> <wenjing.qiao@intel.com>
> Subject: [PATCH] net/cpfl: fix coverity issues
> 
> From: Wenjing Qiao <wenjing.qiao@intel.com>
> 
> Fix integer handling issues, tainted_scalar issues, uninit issues, overrun issues
> and control flow issues reported by coverity scan.
> 
> Coverity issue: 403259
> Coverity issue: 403261
> Coverity issue: 403266
> Coverity issue: 403267
> Coverity issue: 403271
> Coverity issue: 403274
> Fixes: db042ef09d26 ("net/cpfl: implement FXP rule creation and destroying")
> Fixes: 03f976012304 ("net/cpfl: adapt FXP to flow engine")

Acked-by: Qi Zhang <qi.z.zhang@intel.com>

Applied to dpdk-next-net-intel.

Thanks
Qi
  
Thomas Monjalon Nov. 12, 2023, 5:42 p.m. UTC | #2
07/11/2023 01:18, Zhang, Qi Z:
> From: Qiao, Wenjing <wenjing.qiao@intel.com>
> > From: Wenjing Qiao <wenjing.qiao@intel.com>
> > 
> > Fix integer handling issues, tainted_scalar issues, uninit issues, overrun issues
> > and control flow issues reported by coverity scan.
> > 
> > Coverity issue: 403259
> > Coverity issue: 403261
> > Coverity issue: 403266
> > Coverity issue: 403267
> > Coverity issue: 403271
> > Coverity issue: 403274
> > Fixes: db042ef09d26 ("net/cpfl: implement FXP rule creation and destroying")
> > Fixes: 03f976012304 ("net/cpfl: adapt FXP to flow engine")
> 
> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
> 
> Applied to dpdk-next-net-intel.

cpfl is still new, but please in future,
try to group fixes logically with an explanation of the fix.
  

Patch

diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index eb168eee51..7697aea0ce 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -2478,7 +2478,7 @@  cpfl_alloc_dma_mem_batch(struct idpf_dma_mem *orig_dma, struct idpf_dma_mem *dma
 {
 	int i;
 
-	if (!idpf_alloc_dma_mem(NULL, orig_dma, size * (1 + batch_size))) {
+	if (!idpf_alloc_dma_mem(NULL, orig_dma, (uint64_t)size * (1 + batch_size))) {
 		PMD_INIT_LOG(ERR, "Could not alloc dma memory");
 		return -ENOMEM;
 	}
diff --git a/drivers/net/cpfl/cpfl_flow_engine_fxp.c b/drivers/net/cpfl/cpfl_flow_engine_fxp.c
index ddede2f553..4d3cdf813e 100644
--- a/drivers/net/cpfl/cpfl_flow_engine_fxp.c
+++ b/drivers/net/cpfl/cpfl_flow_engine_fxp.c
@@ -107,13 +107,6 @@  cpfl_fxp_create(struct rte_eth_dev *dev,
 	return ret;
 }
 
-static inline void
-cpfl_fxp_rule_free(struct rte_flow *flow)
-{
-	rte_free(flow->rule);
-	flow->rule = NULL;
-}
-
 static int
 cpfl_fxp_destroy(struct rte_eth_dev *dev,
 		 struct rte_flow *flow,
@@ -128,7 +121,7 @@  cpfl_fxp_destroy(struct rte_eth_dev *dev,
 	struct cpfl_vport *vport;
 	struct cpfl_repr *repr;
 
-	rim = flow->rule;
+	rim = (struct cpfl_rule_info_meta *)flow->rule;
 	if (!rim) {
 		rte_flow_error_set(error, EINVAL,
 				   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
@@ -164,7 +157,8 @@  cpfl_fxp_destroy(struct rte_eth_dev *dev,
 	for (i = rim->pr_num; i < rim->rule_num; i++)
 		cpfl_fxp_mod_idx_free(ad, rim->rules[i].mod.mod_index);
 err:
-	cpfl_fxp_rule_free(flow);
+	rte_free(rim);
+	flow->rule = NULL;
 	return ret;
 }
 
diff --git a/drivers/net/cpfl/cpfl_fxp_rule.c b/drivers/net/cpfl/cpfl_fxp_rule.c
index ea65e20507..ba3a036e7a 100644
--- a/drivers/net/cpfl/cpfl_fxp_rule.c
+++ b/drivers/net/cpfl/cpfl_fxp_rule.c
@@ -76,8 +76,8 @@  cpfl_receive_ctlq_msg(struct idpf_hw *hw, struct idpf_ctlq_info *cq, u16 num_q_m
 		rte_delay_us_sleep(10);
 		ret = cpfl_vport_ctlq_recv(cq, &num_q_msg, &q_msg[0]);
 
-		if (ret && ret != CPFL_ERR_CTLQ_NO_WORK &&
-		    ret != CPFL_ERR_CTLQ_ERROR) {
+		if (ret && ret != CPFL_ERR_CTLQ_NO_WORK && ret != CPFL_ERR_CTLQ_ERROR &&
+		    ret != CPFL_ERR_CTLQ_EMPTY) {
 			PMD_INIT_LOG(ERR, "failed to recv ctrlq msg. err: 0x%4x\n", ret);
 			retries++;
 			continue;
@@ -165,7 +165,7 @@  cpfl_default_rule_pack(struct cpfl_rule_info *rinfo, struct idpf_dma_mem *dma,
 {
 	union cpfl_rule_cfg_pkt_record *blob = NULL;
 	enum cpfl_ctlq_rule_cfg_opc opc;
-	struct cpfl_rule_cfg_data cfg;
+	struct cpfl_rule_cfg_data cfg = {0};
 	uint16_t cfg_ctrl;
 
 	if (!dma->va) {
diff --git a/drivers/net/cpfl/cpfl_rules.c b/drivers/net/cpfl/cpfl_rules.c
index 3d259d3da8..6c0e435b1d 100644
--- a/drivers/net/cpfl/cpfl_rules.c
+++ b/drivers/net/cpfl/cpfl_rules.c
@@ -116,8 +116,7 @@  cpfl_prep_sem_rule_blob(const uint8_t *key,
 	uint32_t i;
 
 	idpf_memset(rule_blob, 0, sizeof(*rule_blob), IDPF_DMA_MEM);
-	idpf_memcpy(rule_blob->sem_rule.key, key, key_byte_len,
-		    CPFL_NONDMA_TO_DMA);
+	memcpy(rule_blob->sem_rule.key, key, key_byte_len);
 
 	for (i = 0; i < act_byte_len / sizeof(uint32_t); i++)
 		*act_dst++ = CPU_TO_LE32(*act_src++);