[v7,2/2] bus/pci: fix legacy device missing region info
Checks
Commit Message
If the legacy device in the primary process does not support mapping the
io port bar, the secondary process needs to proactively get the device
information and fil the region information.
Fixes: 4b741542ecde ("bus/pci: avoid depending on private kernel value")
Signed-off-by: Mingjin Ye <mingjinx.ye@intel.com>
---
v7: Modify commit log
---
v6:
- split patch
v5:
- adding checks to vfio setup
v4:
- adjusting commit log
v3:
- adjusting variable settings
v2:
- add release of device in pci_vfio_ioport_unmap
---
drivers/bus/pci/linux/pci_vfio.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
Comments
On 11/22/2023 3:52 PM, Mingjin Ye wrote:
> If the legacy device in the primary process does not support mapping the
> io port bar, the secondary process needs to proactively get the device
> information and fil the region information.
>
> Fixes: 4b741542ecde ("bus/pci: avoid depending on private kernel value")
>
> Signed-off-by: Mingjin Ye <mingjinx.ye@intel.com>
I have already sent my Acked-by on v6. Once you receive an Ack, you need
to add it in the subsequent versions.
For this one I am again doing for the committer.
Acked-by: Nipun Gupta <nipun.gupta@amd.com>
24/11/2023 11:47, Gupta, Nipun:
>
> On 11/22/2023 3:52 PM, Mingjin Ye wrote:
> > If the legacy device in the primary process does not support mapping the
> > io port bar, the secondary process needs to proactively get the device
> > information and fil the region information.
> >
> > Fixes: 4b741542ecde ("bus/pci: avoid depending on private kernel value")
> >
> > Signed-off-by: Mingjin Ye <mingjinx.ye@intel.com>
>
> I have already sent my Acked-by on v6. Once you receive an Ack, you need
> to add it in the subsequent versions.
>
> For this one I am again doing for the committer.
>
> Acked-by: Nipun Gupta <nipun.gupta@amd.com>
Series applied with a bit of rebase and styling fixes, thanks.
@@ -1230,6 +1230,32 @@ pci_vfio_ioport_map(struct rte_pci_device *dev, int bar,
return -1;
}
+ if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
+ struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
+ char pci_addr[PATH_MAX];
+ int vfio_dev_fd;
+ struct rte_pci_addr *loc = &dev->addr;
+
+ /* store PCI address string */
+ snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
+ loc->domain, loc->bus, loc->devid, loc->function);
+
+ vfio_dev_fd = rte_intr_dev_fd_get(dev->intr_handle);
+ if (vfio_dev_fd < 0) {
+ return -1;
+ } else if (vfio_dev_fd == 0) {
+ if (rte_vfio_get_device_info(rte_pci_get_sysfs_path(), pci_addr,
+ &vfio_dev_fd, &device_info) != 0)
+ return -1;
+ /* we need save vfio_dev_fd, so it can be used during release */
+ if (rte_intr_dev_fd_set(dev->intr_handle, vfio_dev_fd) != 0)
+ return -1;
+
+ if (pci_vfio_fill_regions(dev, vfio_dev_fd, &device_info) != 0)
+ return -1;
+ }
+ }
+
if (pci_vfio_get_region(dev, bar, &size, &offset) != 0) {
RTE_LOG(ERR, EAL, "Cannot get offset of region %d.\n", bar);
return -1;