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Sun, 3 Dec 2023 03:26:27 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Alex Vesker Subject: [PATCH v1 16/23] net/mlx5/hws: increase hl size for future compatibility Date: Sun, 3 Dec 2023 13:25:36 +0200 Message-ID: <20231203112543.844014-17-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231203112543.844014-1-michaelba@nvidia.com> References: <20231203112543.844014-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709B:EE_|LV8PR12MB9134:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f94b61b-6b40-4b29-56d3-08dbf3f2b7d8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: I1lhrrSj7lqSKqUndpJb9A39csFhLd2AoJrfHSMSbo9OheyzRBnB6Y/2OuvD4hM4fg+RfK+wyWbC3HOAACebMlXhkMZLBIZ1Hee8y23oToIsXXDCRHSY1nd2Wdq5oxMc17wdLXTfhCDI0/s8ZV3KuwIEfne910291VgxBibbRmrth5NUvcUm3eYQHA0TqOy25jRCUdA9zuXriQsyj5FuYYnc99TfLaBLPfAtwbLM4Q2j6aM40Qw5fve8NJG0E+47WYBJx7QFNUkli8dsZWiytkpNUPY/+jHmIC6V6D+M9GASJqRSaFARGXUyRIJrL/VisL+oyrI0sfS4nCGBHv4GEprYWfNM+cEuSUQLu7HG6TeNLzkY9i/yb8GTIACPGlZkSGCmmZ6l6jRieGTfAZHH92l2DKQtd/8Jf62wOz7x837vQHRJWlB8q2Z4P6HdNC3rrais3R3yhDRFzvkdQ9+GMnfIXx9Z/ntli6E/VrXosmrDZ+S7XhfkTYVVK3vn6zScZ/bueijaMDaB6lx0uR9FeCESJzA2dx8AFtvIhrjZFjOAI/BsYNNht1sPISLoERsLMB0Pg4MuJe8RiYVk3lf0+w4nyxSfR8lmm+t9yAiEkruoeQVyGqD6TIyuNkeo1DdHWoGHXLTOTGogHXCqPuBXmzTD9re+1+3SR9K2reWNcZznMjEZ52A/lMHZsUsNZ+X7TS3RM66umHJNxmspTwJOqwMl7DQe24Gki5+zaKEi6RRO+thx/VZwSrRPmRJGT6QO X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230031)(4636009)(136003)(39860400002)(346002)(396003)(376002)(230922051799003)(1800799012)(64100799003)(82310400011)(186009)(451199024)(40470700004)(46966006)(36840700001)(54906003)(6916009)(70586007)(70206006)(4326008)(8676002)(8936002)(316002)(478600001)(40460700003)(6666004)(5660300002)(36756003)(41300700001)(2906002)(86362001)(40480700001)(47076005)(356005)(82740400003)(426003)(83380400001)(2616005)(26005)(336012)(6286002)(107886003)(1076003)(7636003)(55016003)(36860700001)(7696005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Dec 2023 11:26:39.3694 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f94b61b-6b40-4b29-56d3-08dbf3f2b7d8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9134 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alex Vesker In some cases we rely on header layout DW offset from FW caps, this is done in case of future HW which may support current flex fields natively, for this we must increase header layout to 255 DWs, which is the limit in current definer creation. Signed-off-by: Alex Vesker --- drivers/net/mlx5/hws/mlx5dr_definer.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index 6f1c99e37a..e2be579303 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -523,10 +523,8 @@ struct mlx5_ifc_definer_hl_bits { u8 unsupported_free_running_timestamp[0x40]; struct mlx5_ifc_definer_hl_flex_parser_bits flex_parser; struct mlx5_ifc_definer_hl_registers_bits registers; - /* struct x ib_l3_extended; */ - /* struct x rwh */ - /* struct x dcceth */ - /* struct x dceth */ + /* Reserved in case header layout on future HW */ + u8 unsupported_reserved[0xd40]; }; enum mlx5dr_definer_gtp {