From patchwork Sun Dec 3 11:25:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 134752 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A4D944365F; Sun, 3 Dec 2023 12:27:03 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F3012406A2; Sun, 3 Dec 2023 12:26:27 +0100 (CET) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2087.outbound.protection.outlook.com [40.107.93.87]) by mails.dpdk.org (Postfix) with ESMTP id 1A0A740685 for ; Sun, 3 Dec 2023 12:26:26 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nA15OAHjxxSlPWcjp0v8C28E6heX5BVRKHFWz3N7LhmgUqbh4yOvXAJeTefb3Wpne3+MD/WJ+iNh66CPsi98o3ypZF6249xht4Ke39ZUhq5GScWxBTAzwubOCKh1cWshsRjYEYdOkyv+iYg2il6DEtjmnPpYoPABOsaS7KpqPettfNhdQU5NTVOMsKvgTpNmNKaJF3UDtECTP/g66ULde4zFia5W7vR+6QkdkpC/fviBZxhKL8Ugyw68ja2IbTTTXCt7snFUChOunHlhDAdVkwoOE2NL9iyLTyRaxV1QAk2cQkoccN3Gs5L7GCLYIzCjXrG3ZwEIbvTwsyvzFRGM/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=nwodTV+DYJQlrHc/1RB7QN3X43GdzAeWIyIYfW/TFFU=; b=QHWhmtzMB6JYIfluECrQ/qLgcMnv2CKdGwS3rWPC7nYQSjHllpuSHA4EeRel6/m2WQNVzNK9t1g7S4ZZTSKQoo4XNVq+MVqgFSG7+ExhM6fESb9sRKysMO6ADI4srozUEie1JBEs8zrGhf7vJntVnpZ1VTc5OUykW0I5tjcqtqdBDI8sl0KB6RmXMOsXe/zVt7Hm6Y90hXR/6ocRg0ykYcCuGpRxGeY0aTwgIcnV6lc6L+toAZsjP7QdVuZJBO6Xs373FczlEizjrHXQpbh4fF55dp/MtlwKS2TMCvo5k5d7PIA55Cn+xx3jkx0/hiTMwkMiuoL68Pnv2HxncHRqtg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nwodTV+DYJQlrHc/1RB7QN3X43GdzAeWIyIYfW/TFFU=; b=UHqUeKnIqqJw/rwflRTIZhoymsRT1WAVvPiqKxgqDk3RqeUdJtu8bL2DxdSuSEIzvX0BMKwyRQGsyiEVHXC33F+cWjtfLpNXlfYcyQ+aOZy1R8h99O6LVvcS1u57Qj/oBHemTHFLXEW99gjeglnOd0IGGlwocUFwXlsV1OKHPjnv/I2EUNdxxpH39TpdnFmNS89WP4Ahraz3xeJxlt+LkCENm8MFVQOebU627h7Tx5s40HmvMpACGPbeKFaflrL2Bs7f/CX4opSL8RPsJWeQXbQmypQTBzj00OFKkgpPoZxPzPTXKwigByibz9VyuzpuzYPqo4xXPjCn8MXFzLNeSw== Received: from MW4P222CA0026.NAMP222.PROD.OUTLOOK.COM (2603:10b6:303:114::31) by SJ0PR12MB5635.namprd12.prod.outlook.com (2603:10b6:a03:42a::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.32; Sun, 3 Dec 2023 11:26:19 +0000 Received: from CO1PEPF000042AC.namprd03.prod.outlook.com (2603:10b6:303:114:cafe::12) by MW4P222CA0026.outlook.office365.com (2603:10b6:303:114::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.32 via Frontend Transport; Sun, 3 Dec 2023 11:26:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CO1PEPF000042AC.mail.protection.outlook.com (10.167.243.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.20 via Frontend Transport; Sun, 3 Dec 2023 11:26:19 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Sun, 3 Dec 2023 03:26:03 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Sun, 3 Dec 2023 03:26:02 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41 via Frontend Transport; Sun, 3 Dec 2023 03:26:00 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou Subject: [PATCH v1 05/23] net/mlx5: fix GENEVE option item translation Date: Sun, 3 Dec 2023 13:25:25 +0200 Message-ID: <20231203112543.844014-6-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231203112543.844014-1-michaelba@nvidia.com> References: <20231203112543.844014-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AC:EE_|SJ0PR12MB5635:EE_ X-MS-Office365-Filtering-Correlation-Id: 0934e829-5331-44cb-2f61-08dbf3f2ac09 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: IzKCaUOyorSCCiibZdXVUK/Q2gOkayihtuZJNXs8XJ9vprDLc8NSh3R5YIIs63IvY1j62pItJLc25FAuitJhQFaD1wsuMpAVzGCsznh/2+NlaSIRXG/u9xC+ywYJ4jGk0r7z/KnLz1yMoaYLB8JkAwb+57sHDFsGyA6kPvP4kemKrre3LjDthbEdcAY+e8Z+ObbRGa25FQw6JqAoGFHXsn/catpFU63z0LAGbVVmBEf2H6EqgFAK7Vq/kySsvkgEBiQnfw/sn/EchwU6xLa6ZYbmDIfjZynVrpKoSp2JAm8Hray1zHbv2gwpax+JNYNrLbzvh2h5PLIw58cC89W0EC6yAf1/ezmx2xidlkLjGJqU89EG/lkjh4PybbosHM1ZfDHkHTqSB+fmW3JyHHpaWUA6AK19/PWeayqZVl1QFNYFOfIjQjv6wUGg/0SbTqAsMHz4y34xz3Ax3Hccegpvnke80PDv1GOsNvXh6WhhbCT8zvBJAqmhmgljU2Fo7geuArUI0QsNaODd5g/nn6OLW/JXjeQklOysPMdAEpvP1Z2PtxwYKr04D+1UpJjvLyY9NEctBIQBcPsWBfUdZHPBLvcuRfcVKqKd826XZhBkuyDecvsRyzSURkmQMn4HIh9nV1ZeCV4sBqPgnvxCN93RYSiowSsgh9cp8uswXba/UFzgh/Mq4bfY+4TEt1KsL0K0aSZR8sVkrfmN/NZWTnAyBEw6eCUQ5L0rsXE9JXOHZPct5p8v+6DvR4+QPq/v1e7OhA+VL2NAYYpf5IL6DEdqa4HhPCDB0MMFKeFCsOO3r3M= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230031)(4636009)(376002)(346002)(136003)(39860400002)(396003)(230922051799003)(451199024)(186009)(64100799003)(1800799012)(82310400011)(36840700001)(40470700004)(46966006)(6666004)(1076003)(2616005)(7696005)(107886003)(7636003)(356005)(47076005)(36860700001)(316002)(70206006)(70586007)(6916009)(54906003)(83380400001)(336012)(426003)(40480700001)(26005)(55016003)(6286002)(82740400003)(8676002)(4326008)(478600001)(8936002)(2906002)(41300700001)(5660300002)(40460700003)(36756003)(86362001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Dec 2023 11:26:19.5569 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0934e829-5331-44cb-2f61-08dbf3f2ac09 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5635 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The "flow_dv_translate_item_geneve_opt()" function is called twice per flow rule, for either matcher focusing the mask or value focusing the spec. The spec is always provided and its field "option_len" indicates the data size for both spec and mask. For using it, function has another pointer "geneve_opt_vv" representing the spec regardless to focusing while the "geneve_opt_v" pointer represents the mask for matcher and spec for rule creation. The current implementation has 2 issues: 1. geneve_opt_v get the spec in rule creation as sane as geneve_opt_vv, but function use if-else which is bacicly has same value. 2. function uses "option_len" from "geneve_opt_v" instead of "geneve_opt_v" even when the focus is on mask, for HWS the mask value may be 0 even data is valid. This patch refactors the function implementation to avoid those issues. Fixes: cd4ab742064a ("net/mlx5: split flow item matcher and value translation") Cc: suanmingm@nvidia.com Signed-off-by: Michael Baum --- drivers/net/mlx5/mlx5_flow_dv.c | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 62ca742654..f8e364dfdb 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -9985,13 +9985,13 @@ flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *key, { const struct rte_flow_item_geneve_opt *geneve_opt_m; const struct rte_flow_item_geneve_opt *geneve_opt_v; - const struct rte_flow_item_geneve_opt *geneve_opt_vv = item->spec; + const struct rte_flow_item_geneve_opt *orig_spec = item->spec; void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3); rte_be32_t opt_data_key = 0, opt_data_mask = 0; - uint32_t *data; + size_t option_byte_len; int ret = 0; - if (MLX5_ITEM_VALID(item, key_type)) + if (MLX5_ITEM_VALID(item, key_type) || !orig_spec) return -1; MLX5_ITEM_UPDATE(item, key_type, geneve_opt_v, geneve_opt_m, &rte_flow_item_geneve_opt_mask); @@ -10004,21 +10004,15 @@ flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *key, return ret; } } - /* Set the data. */ - if (key_type == MLX5_SET_MATCHER_SW_V) - data = geneve_opt_vv->data; - else - data = geneve_opt_v->data; - if (data) { - memcpy(&opt_data_key, data, - RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4), - sizeof(opt_data_key))); - memcpy(&opt_data_mask, geneve_opt_m->data, - RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4), - sizeof(opt_data_mask))); + /* Convert the option length from DW to bytes for using memcpy. */ + option_byte_len = RTE_MIN((size_t)(orig_spec->option_len * 4), + sizeof(rte_be32_t)); + if (geneve_opt_v->data) { + memcpy(&opt_data_key, geneve_opt_v->data, option_byte_len); + memcpy(&opt_data_mask, geneve_opt_m->data, option_byte_len); MLX5_SET(fte_match_set_misc3, misc3_v, - geneve_tlv_option_0_data, - rte_be_to_cpu_32(opt_data_key & opt_data_mask)); + geneve_tlv_option_0_data, + rte_be_to_cpu_32(opt_data_key & opt_data_mask)); } return ret; }