diff mbox series

[v2,04/18] net/bnxt: fix setting 50G and 100G forced speed

Message ID 20231222215659.64993-5-ajit.khaparde@broadcom.com (mailing list archive)
State Superseded, archived
Delegated to: Ajit Khaparde
Headers
Series bnxt patchset |

Checks

Context Check Description
ci/checkpatch warning coding style issues

Commit Message

Ajit Khaparde Dec. 22, 2023, 9:56 p.m. UTC 
  From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>

Thor based NICs can support PAM4 as well as NRZ link negotiation.
While PAM4 can negotiate speeds at 50G, 100G and 200G, the PMD will
use NRZ signaling for 50G and 100G speeds. PAM4 signaling will be
used only for 200G speed negotiations.

Driver has to check for NRZ speed support first while forcing speed.

Fixes: c23f9ded0391 ("net/bnxt: support 200G PAM4 link")
Cc: stable@dpdk.org

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/bnxt_hwrm.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 8f99582819..c31a5d4226 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -3158,6 +3158,8 @@  static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
 					  struct bnxt_link_info *link_info)
 {
+	uint16_t support_pam4_speeds = link_info->support_pam4_speeds;
+	uint16_t support_speeds = link_info->support_speeds;
 	uint16_t eth_link_speed = 0;
 
 	if (conf_link_speed == RTE_ETH_LINK_SPEED_AUTONEG)
@@ -3195,23 +3197,23 @@  static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
 			HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
 		break;
 	case RTE_ETH_LINK_SPEED_50G:
-		if (link_info->support_pam4_speeds &
-		    HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G) {
-			eth_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB;
-			link_info->link_signal_mode = BNXT_SIG_MODE_PAM4;
-		} else {
+		if (support_speeds & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) {
 			eth_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
 			link_info->link_signal_mode = BNXT_SIG_MODE_NRZ;
+		} else if (support_pam4_speeds &
+			   HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G) {
+			eth_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB;
+			link_info->link_signal_mode = BNXT_SIG_MODE_PAM4;
 		}
 		break;
 	case RTE_ETH_LINK_SPEED_100G:
-		if (link_info->support_pam4_speeds &
-		    HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G) {
-			eth_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB;
-			link_info->link_signal_mode = BNXT_SIG_MODE_PAM4;
-		} else {
+		if (support_speeds & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) {
 			eth_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
 			link_info->link_signal_mode = BNXT_SIG_MODE_NRZ;
+		} else if (support_pam4_speeds &
+			   HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G) {
+			eth_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB;
+			link_info->link_signal_mode = BNXT_SIG_MODE_PAM4;
 		}
 		break;
 	case RTE_ETH_LINK_SPEED_200G: