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[v2,16/23] net/mlx5/hws: increase hl size for future compatibility

Message ID 20240125133043.575860-17-michaelba@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5: support Geneve and options for HWS |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Michael Baum Jan. 25, 2024, 1:30 p.m. UTC 
  From: Alex Vesker <valex@nvidia.com>

In some cases we rely on header layout DW offset from FW caps,
this is done in case of future HW which may support current
flex fields natively, for this we must increase header layout to
255 DWs, which is the limit in current definer creation.

Signed-off-by: Alex Vesker <valex@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.h | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index 7b7463fc91..f6a3a7ec28 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -534,10 +534,8 @@  struct mlx5_ifc_definer_hl_bits {
 	u8 unsupported_free_running_timestamp[0x40];
 	struct mlx5_ifc_definer_hl_flex_parser_bits flex_parser;
 	struct mlx5_ifc_definer_hl_registers_bits registers;
-	/* struct x ib_l3_extended; */
-	/* struct x rwh */
-	/* struct x dcceth */
-	/* struct x dceth */
+	/* Reserved in case header layout on future HW */
+	u8 unsupported_reserved[0xd40];
 };
 
 enum mlx5dr_definer_gtp {