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Thu, 25 Jan 2024 05:30:56 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Dariusz Sosnowski , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Alex Vesker , , Subject: [PATCH v2 03/23] net/mlx5/hws: fix tunnel protocol checks Date: Thu, 25 Jan 2024 15:30:23 +0200 Message-ID: <20240125133043.575860-4-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240125133043.575860-1-michaelba@nvidia.com> References: <20231203112543.844014-1-michaelba@nvidia.com> <20240125133043.575860-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD0:EE_|SJ2PR12MB9192:EE_ X-MS-Office365-Filtering-Correlation-Id: 3ecbc7ee-9405-44c4-f6a4-08dc1da9e2d5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +5dHAS8Nv2l6BBXVUsF2snXQ4rbiDjXPDRj2X91yB3jMc2fewGHwremACwjn2p8lo9bGTZVr4zjVYT+35+wmxd+SX3GMBhrvQWLD8yt3o3JLc5fCgi1ZrEC52xNJdU8K6biCWLfzO/8oAxTtHfbNZEhPEQ8tt+6R4ZObnnRZ5pUeS3EMNFTeNEBZgCflQQky6/9i5JZw25v95xEnpnO/VH8XNF/gZGM2RY60AY497NPNwAX1Pi9fdm71Nm+Y5wEGyKezURLEmJphXEyDfVJIS5M3AhLODohcQFGuhxDJShaiF6MuTq4U2v1CQ5UfhPgmPNuLp2LcRuhJj7wV/P8OESghPazDnV7xXmL6jbhC4ZztUSJ8xMxxUVX3LG3XeqdUphT2fEXF/BGjVralLhd3HyGCAhnLSiSIF3fPV0rvtNfOE8ZbjI1/4cGTndbhAE1OPRb3t4d7KBToMtgXhAYGmHzFEmr20S5qHOLK+ZEdk8BmWABfl53/In4o9ge7K1hfiQILMiDAGBf01L1VzBCzOXNprcNXshXGgLuwppN7U9UBpgqRPuDlhFuWkK+lMTrvFpQIX+nz23Y60pFf/xuFyHE+s4Ok44AngbRs+zGRVQr0ClaO6xwt8bVzdFwN9NaeZOQ4+sirKr5Z2AtfKQheY1YOQKrH+zsBKdlKaHYRqeGNWDOOcw3pqa91Bd5yl9QQOYhmtu3coWAsuFkkCJ/Tp0aGEWINE4t5CItenHr7Aydn8Iwa05gLux8cYda89amBpKnXqQ/gxQsZPHFsqKR84Q== X-Forefront-Antispam-Report: CIP:216.228.118.233; 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Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9192 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alex Vesker Align GRE, GTPU and VXLAN tunnel protocols to fail in case the packet is already tunneled. Also use local defines for protocol UDP ports for better layering of mlx5dr API. Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer") Fixes: 5bf14a4beb1a ("net/mlx5/hws: support matching on MPLSoUDP") Cc: valex@nvidia.com Cc: erezsh@nvidia.com Cc: stable@dpdk.org Signed-off-by: Alex Vesker Acked-by: Suanming Mou --- drivers/net/mlx5/hws/mlx5dr_definer.c | 43 +++++++++++++-------------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 750eb9c7c6..219bffd3b5 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -8,9 +8,10 @@ #define BAD_PORT 0xBAD #define ETH_TYPE_IPV4_VXLAN 0x0800 #define ETH_TYPE_IPV6_VXLAN 0x86DD -#define ETH_VXLAN_DEFAULT_PORT 4789 -#define ETH_VXLAN_GPE_DEFAULT_PORT 4790 -#define IP_UDP_PORT_MPLS 6635 +#define UDP_VXLAN_PORT 4789 +#define UDP_VXLAN_GPE_PORT 4790 +#define UDP_GTPU_PORT 2152 +#define UDP_PORT_MPLS 6635 #define UDP_ROCEV2_PORT 4791 #define DR_FLOW_LAYER_TUNNEL_NO_MPLS (MLX5_FLOW_LAYER_TUNNEL & ~MLX5_FLOW_LAYER_MPLS) @@ -159,7 +160,7 @@ struct mlx5dr_definer_conv_data { X(SET, tcp_protocol, STE_TCP, rte_flow_item_tcp) \ X(SET_BE16, tcp_src_port, v->hdr.src_port, rte_flow_item_tcp) \ X(SET_BE16, tcp_dst_port, v->hdr.dst_port, rte_flow_item_tcp) \ - X(SET, gtp_udp_port, RTE_GTPU_UDP_PORT, rte_flow_item_gtp) \ + X(SET, gtp_udp_port, UDP_GTPU_PORT, rte_flow_item_gtp) \ X(SET_BE32, gtp_teid, v->hdr.teid, rte_flow_item_gtp) \ X(SET, gtp_msg_type, v->hdr.msg_type, rte_flow_item_gtp) \ X(SET, gtp_ext_flag, !!v->hdr.gtp_hdr_info, rte_flow_item_gtp) \ @@ -167,12 +168,12 @@ struct mlx5dr_definer_conv_data { X(SET, gtp_ext_hdr_pdu, v->hdr.type, rte_flow_item_gtp_psc) \ X(SET, gtp_ext_hdr_qfi, v->hdr.qfi, rte_flow_item_gtp_psc) \ X(SET, vxlan_flags, v->flags, rte_flow_item_vxlan) \ - X(SET, vxlan_udp_port, ETH_VXLAN_DEFAULT_PORT, rte_flow_item_vxlan) \ - X(SET, vxlan_gpe_udp_port, ETH_VXLAN_GPE_DEFAULT_PORT, rte_flow_item_vxlan_gpe) \ + X(SET, vxlan_udp_port, UDP_VXLAN_PORT, rte_flow_item_vxlan) \ + X(SET, vxlan_gpe_udp_port, UDP_VXLAN_GPE_PORT, rte_flow_item_vxlan_gpe) \ X(SET, vxlan_gpe_flags, v->flags, rte_flow_item_vxlan_gpe) \ X(SET, vxlan_gpe_protocol, v->protocol, rte_flow_item_vxlan_gpe) \ X(SET, vxlan_gpe_rsvd1, v->rsvd1, rte_flow_item_vxlan_gpe) \ - X(SET, mpls_udp_port, IP_UDP_PORT_MPLS, rte_flow_item_mpls) \ + X(SET, mpls_udp_port, UDP_PORT_MPLS, rte_flow_item_mpls) \ X(SET, source_qp, v->queue, mlx5_rte_flow_item_sq) \ X(SET, tag, v->data, rte_flow_item_tag) \ X(SET, metadata, v->data, rte_flow_item_meta) \ @@ -1198,6 +1199,12 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, const struct rte_flow_item_gtp *m = item->mask; struct mlx5dr_definer_fc *fc; + if (cd->tunnel) { + DR_LOG(ERR, "Inner GTPU item not supported"); + rte_errno = ENOTSUP; + return rte_errno; + } + /* Overwrite GTPU dest port if not present */ fc = &cd->fc[DR_CALC_FNAME(L4_DPORT, false)]; if (!fc->tag_set && !cd->relaxed) { @@ -1372,9 +1379,13 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd, struct mlx5dr_definer_fc *fc; bool inner = cd->tunnel; - /* In order to match on VXLAN we must match on ether_type, ip_protocol - * and l4_dport. - */ + if (inner) { + DR_LOG(ERR, "Inner VXLAN item not supported"); + rte_errno = ENOTSUP; + return rte_errno; + } + + /* In order to match on VXLAN we must match on ip_protocol and l4_dport */ if (!cd->relaxed) { fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)]; if (!fc->tag_set) { @@ -1397,12 +1408,6 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd, return 0; if (m->flags) { - if (inner) { - DR_LOG(ERR, "Inner VXLAN flags item not supported"); - rte_errno = ENOTSUP; - return rte_errno; - } - fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_FLAGS]; fc->item_idx = item_idx; fc->tag_set = &mlx5dr_definer_vxlan_flags_set; @@ -1412,12 +1417,6 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd, } if (!is_mem_zero(m->vni, 3)) { - if (inner) { - DR_LOG(ERR, "Inner VXLAN vni item not supported"); - rte_errno = ENOTSUP; - return rte_errno; - } - fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_VNI]; fc->item_idx = item_idx; fc->tag_set = &mlx5dr_definer_vxlan_vni_set;