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Thu, 25 Jan 2024 05:31:01 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Dariusz Sosnowski , Viacheslav Ovsiienko , Ori Kam , Suanming Mou Subject: [PATCH v2 05/23] net/mlx5: fix GENEVE option item translation Date: Thu, 25 Jan 2024 15:30:25 +0200 Message-ID: <20240125133043.575860-6-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240125133043.575860-1-michaelba@nvidia.com> References: <20231203112543.844014-1-michaelba@nvidia.com> <20240125133043.575860-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD4:EE_|CYYPR12MB8702:EE_ X-MS-Office365-Filtering-Correlation-Id: 7acb1136-2d06-441f-59ad-08dc1da9e592 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wFX62L829vdEmdXwaokn5wBJqOqNx/xdZ9hlbIBqpv4jZHqczZAkWhSGivSG5OFwIcEWmyHN3RluhB8vGrx3bF3Ez7DmfIab9F3GJHQazRb26emyEHxPsWF/6vNFoK5BuUKlfQ+uQ7KuRxgfvG6HBGIBP2Mnu0JKw6mLT8Qd3cYjLm9yMyy12lnmq/WuSWmXx1GkkBcagh8LoUQdGblQZjjCnaHwWs9P/9FkFZYaAVLLrswczsE1RgmLPTWsoZHK8FC9KIhWSYH02ctBqL3uzmlcQMKJWnB3vMDshpm4WSvVlVzmbXm9aPHqEkDb3KNvni93hY40EbBFpXiGBKommNyJ12V1VBATmTtukefMO+OTrp6D1kcQ7UjgujMcgTXJxtK6GdaSl0ilGOUy1wSoxxHIrCWyykvi6QbMY/CICYfbPDFWthpM1yFQlyo98+zlfw1loVT87pGV7FaA7EDFM2m8n3aQYmZCujvjAUxPXYxLMeLdX3SVIBs0LABglWx2FeafDqzILX8DwmQOFyvHr7MkvpKOuZ6lW9iHU7PG2JtgQjWUnPCVs9B4Yf9922sx5UovRhckgvn2bYbXBURUAyrv6o3+F8c7e7JCKaXUtpTz/kK8aZrun/1qkoFksMmbLyjq2+rYFKVOSJ9uhrJn3DenFPJl49yvOXFhR2p09GKV7c6aoEKHHHQyKqnib4CkmqLfAuZ7lWsL499U+ERhU4q5jtbLXx/VLZrVB4QiPs5G8/jEvN+aQDs+asK/7/6J X-Forefront-Antispam-Report: CIP:216.228.118.233; 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Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8702 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The "flow_dv_translate_item_geneve_opt()" function is called twice per flow rule, for either matcher focusing the mask or value focusing the spec. The spec is always provided and its field "option_len" indicates the data size for both spec and mask. For using it, function has another pointer "geneve_opt_vv" representing the spec regardless to focusing while the "geneve_opt_v" pointer represents the mask for matcher and spec for rule creation. The current implementation has 2 issues: 1. geneve_opt_v get the spec in rule creation as sane as geneve_opt_vv, but function use if-else which is bacicly has same value. 2. function uses "option_len" from "geneve_opt_v" instead of "geneve_opt_v" even when the focus is on mask, for HWS the mask value may be 0 even data is valid. This patch refactors the function implementation to avoid those issues. Fixes: cd4ab742064a ("net/mlx5: split flow item matcher and value translation") Cc: suanmingm@nvidia.com Signed-off-by: Michael Baum Acked-by: Suanming Mou --- drivers/net/mlx5/mlx5_flow_dv.c | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index b091eb9d11..cc5549f9ce 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -10103,13 +10103,13 @@ flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *key, { const struct rte_flow_item_geneve_opt *geneve_opt_m; const struct rte_flow_item_geneve_opt *geneve_opt_v; - const struct rte_flow_item_geneve_opt *geneve_opt_vv = item->spec; + const struct rte_flow_item_geneve_opt *orig_spec = item->spec; void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3); rte_be32_t opt_data_key = 0, opt_data_mask = 0; - uint32_t *data; + size_t option_byte_len; int ret = 0; - if (MLX5_ITEM_VALID(item, key_type)) + if (MLX5_ITEM_VALID(item, key_type) || !orig_spec) return -1; MLX5_ITEM_UPDATE(item, key_type, geneve_opt_v, geneve_opt_m, &rte_flow_item_geneve_opt_mask); @@ -10122,21 +10122,15 @@ flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *key, return ret; } } - /* Set the data. */ - if (key_type == MLX5_SET_MATCHER_SW_V) - data = geneve_opt_vv->data; - else - data = geneve_opt_v->data; - if (data) { - memcpy(&opt_data_key, data, - RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4), - sizeof(opt_data_key))); - memcpy(&opt_data_mask, geneve_opt_m->data, - RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4), - sizeof(opt_data_mask))); + /* Convert the option length from DW to bytes for using memcpy. */ + option_byte_len = RTE_MIN((size_t)(orig_spec->option_len * 4), + sizeof(rte_be32_t)); + if (geneve_opt_v->data) { + memcpy(&opt_data_key, geneve_opt_v->data, option_byte_len); + memcpy(&opt_data_mask, geneve_opt_m->data, option_byte_len); MLX5_SET(fte_match_set_misc3, misc3_v, - geneve_tlv_option_0_data, - rte_be_to_cpu_32(opt_data_key & opt_data_mask)); + geneve_tlv_option_0_data, + rte_be_to_cpu_32(opt_data_key & opt_data_mask)); } return ret; }