[v2,3/7] common/mlx5: add inner PRM fields

Message ID 20240207155533.1582031-4-michaelba@nvidia.com (mailing list archive)
State New
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5: support copy from inner fields |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Michael Baum Feb. 7, 2024, 3:55 p.m. UTC
  This patch adds inner values into PRM modify field list for each
existing outer field.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
---
 drivers/common/mlx5/mlx5_prm.h | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)
  

Patch

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index b758557ef9..c6d409833a 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -829,14 +829,17 @@  enum mlx5_modification_field {
 	MLX5_MODI_OUT_TCP_SEQ_NUM,
 	MLX5_MODI_IN_TCP_SEQ_NUM,
 	MLX5_MODI_OUT_TCP_ACK_NUM,
-	MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
+	MLX5_MODI_IN_TCP_ACK_NUM,
 	MLX5_MODI_OUT_ESP_SPI = 0x5E,
+	MLX5_MODI_IN_ESP_SPI,
 	MLX5_MODI_GTP_TEID = 0x6E,
 	MLX5_MODI_OUT_IP_ECN = 0x73,
-	MLX5_MODI_TUNNEL_HDR_DW_1 = 0x75,
+	MLX5_MODI_IN_IP_ECN,
+	MLX5_MODI_TUNNEL_HDR_DW_1,
 	MLX5_MODI_GTPU_FIRST_EXT_DW_0,
 	MLX5_MODI_HASH_RESULT = 0x81,
 	MLX5_MODI_OUT_ESP_SEQ_NUM,
+	MLX5_MODI_IN_ESP_SEQ_NUM,
 	MLX5_MODI_IN_MPLS_LABEL_0 = 0x8a,
 	MLX5_MODI_IN_MPLS_LABEL_1,
 	MLX5_MODI_IN_MPLS_LABEL_2,
@@ -855,7 +858,12 @@  enum mlx5_modification_field {
 	MLX5_MODI_OUT_IPV6_PAYLOAD_LEN,
 	MLX5_MODI_OUT_IPV4_IHL,
 	MLX5_MODI_OUT_TCP_DATA_OFFSET,
-	MLX5_MODI_OUT_IPSEC_NEXT_HDR = 0x126,
+	MLX5_MODI_IN_IPV6_TRAFFIC_CLASS,
+	MLX5_MODI_IN_IPV4_TOTAL_LEN,
+	MLX5_MODI_IN_IPV6_PAYLOAD_LEN,
+	MLX5_MODI_IN_IPV4_IHL,
+	MLX5_MODI_IN_TCP_DATA_OFFSET,
+	MLX5_MODI_OUT_IPSEC_NEXT_HDR,
 	MLX5_MODI_INVALID = INT_MAX,
 };