From patchwork Wed Feb 7 16:14:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 136496 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AD19943AA0; Wed, 7 Feb 2024 17:15:08 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B129042E01; Wed, 7 Feb 2024 17:15:03 +0100 (CET) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2057.outbound.protection.outlook.com [40.107.94.57]) by mails.dpdk.org (Postfix) with ESMTP id 6C59E42DD5 for ; Wed, 7 Feb 2024 17:15:01 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dwg56KAm8MCZoutsuEnDlIoNeXFdE4Tr/2tgd1iXeUfjmy1YfKjRg6/GEFNWv1u+3c5IpxWiJhgzMtqqWo2wp0hNQTOj6xoaXgJaz+nEjUkaBY4j2H+BUA+2Qm5zv6cLZzYmeoVpksD47UYBdon4DxYO53hAbiG8BQme5jQivR3rUWvBSEXOG28dOPNhh5ZdDqmY+DpEbrUe9e9t/AUlkHkLu4vEHNUsnRM8cz+Bt6ocmjkx2wnd44H5oqR29cf1J4ZYuUbTyvkLkRr9FxMThy3YwX/qa93jWRXCSbbt17R9ZI4fzw6BphlApAj/qcP0byYJuZb9nNjiudCoV6POdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=v2VSdEwMj6tihEgWamVgZr6s1ZIU1ndaoQygnGfy8+w=; b=MxGw8+9yYQtraMtQaQKau3wQDzE9bH2PfHxi9vvLrOKaiW2Mu2RqItUl6dhE1UUnFrROb1Sh1NH+DsQQgkXH4TbDPVBQ/g9Ur250j7ZdD5B+EeL3nBOnt4bpy3kgDy+3ekAMoWAnuCWriAh5UcbAHWtZ6N2bpInw+ZRwxtopTLrkES0xE5Z/0UV6H/DtADaIhhH8pCnSwuczYtduQUzQ0fQTGGR6YSydlDwy+Of8Wdd8hbDA4SR5Qm/CHI/2KuGkU2IJQ6nol2wm+Vg+1DmASSwSKoEqzVi0h/0paO1QwmEcPNVPr3f1A6yMpA7rgXwCMkeXkRMkzA3boLbyW+pSNg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=v2VSdEwMj6tihEgWamVgZr6s1ZIU1ndaoQygnGfy8+w=; b=kCrA/P+fIotujl1vBL40+tA9x915VpTCBfoiTYeWR3bLg/+Vdnay/Tpw4MBjIDldssucvUL7y0BXtp4mzJUGueJFHlGHOgetA1dsA6ySuiWcovj8o83/UiC7Q3y2raLFzYXiIQelfThWMd4SLA8ThKn2fLMb3fKLtCHJD7GPEsk8olATZjSFQxrriDiKa9yF3w5x0jd2z2AIi7UAgqmQdyPw79OhiIiU9R7v1umRfoBUFo38hfYsiz/I5Z6enuoapQBd5JFkS7gZNO4WbES0QS+NV/K5Ap0VP3jmOdsWnIpH7Lg1u76DSzD3uws8NPDzXM0tzjU7JMw3QG/RW008SA== Received: from PH7PR10CA0013.namprd10.prod.outlook.com (2603:10b6:510:23d::9) by PH0PR12MB5403.namprd12.prod.outlook.com (2603:10b6:510:eb::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7270.14; Wed, 7 Feb 2024 16:14:56 +0000 Received: from SA2PEPF000015CA.namprd03.prod.outlook.com (2603:10b6:510:23d:cafe::d9) by PH7PR10CA0013.outlook.office365.com (2603:10b6:510:23d::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7249.38 via Frontend Transport; Wed, 7 Feb 2024 16:14:56 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SA2PEPF000015CA.mail.protection.outlook.com (10.167.241.200) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7249.19 via Frontend Transport; Wed, 7 Feb 2024 16:14:56 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 7 Feb 2024 08:14:31 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Wed, 7 Feb 2024 08:14:30 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12 via Frontend Transport; Wed, 7 Feb 2024 08:14:28 -0800 From: Michael Baum To: CC: Matan Azrad , Dariusz Sosnowski , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou Subject: [PATCH v4 2/2] net/mlx5: add support to compare random value Date: Wed, 7 Feb 2024 18:14:14 +0200 Message-ID: <20240207161414.1583125-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240207161414.1583125-1-michaelba@nvidia.com> References: <20240129134410.885145-1-michaelba@nvidia.com> <20240207161414.1583125-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CA:EE_|PH0PR12MB5403:EE_ X-MS-Office365-Filtering-Correlation-Id: 92216d84-d5f0-487d-265c-08dc27f7ecd9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NL3d+8vjSWc6d5zyfz0e+KLYjsxhT4VbKNVZqKbUXApYpyFuKfFTinREwxgymTYXM3J1ltZGpWnmR1StAZp/klBqf6hNDRkdOUG7Ub5wJEx6WXCq1m0cQAVbi9TVnzwphlm+SL6mzHhzwO3tH0AIS1GWcHw0jh19OYMOzliwOgee4lcxBSUxk0oLDcCnkaYhxae/KnFhqG/cvfD3Bc8j8lF2XdBs5EUZ79UVMZKLfPdO5L7O/QGVEfXaTkmxUCMK0rpVq5b5SAIllWvVbUVB0FtLprAG/60ruQtJQlFjBQrWUpOs3k5gNTyhAfY5qptSFBsoLcNASWhcwJMPgT3wmPDrG2E9x9HFhBk2HqnkUU5kl5NbA9785jxq1zA9xmj8BU1N9WYA7vTyZQ6xUpt28HotWpBfVGfj6Kcd0BoVG+TvP4pHdHc4TjYoSvo9LPl5ZPWk4ozso5olaCNISQW/nqtWiDbfJtAXW3nNT7RaIsd+8p1pbCGi4K1sWL3Qxqo3HufKgBRkVlwQZfgBB4APImo6rfogmPJKlSJd9UDef7pfkX9zcwbWo4pVNZ1P5kYV0384poDJ5PBHhjgtuJUU9rnLPoI6vMcJakF9lerQLptbaggEnxH2yaGup/KGohDVo7DsU51Jq1NiCG2RIuDEEUoqbfwDmoha/Iq8I9tLyCl84Psc45Etk/nKtWYMT+/sDARTZLSyr34EmecHu2z54J31ZQCd52FfQANqm+mfkmYsQjhi20/v3FPj/tl7ydMz X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230031)(4636009)(396003)(346002)(376002)(136003)(39860400002)(230922051799003)(1800799012)(451199024)(64100799003)(186009)(82310400011)(36840700001)(40470700004)(46966006)(1076003)(4326008)(8676002)(8936002)(36756003)(2906002)(5660300002)(41300700001)(2616005)(336012)(107886003)(6666004)(86362001)(7696005)(36860700001)(55016003)(478600001)(426003)(356005)(70206006)(26005)(7636003)(6286002)(83380400001)(82740400003)(6916009)(316002)(40480700001)(70586007)(54906003)(47076005)(40460700003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Feb 2024 16:14:56.2421 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92216d84-d5f0-487d-265c-08dc27f7ecd9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5403 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support to use "RTE_FLOW_ITEM_TYPE_COMPARE" with "RTE_FLOW_FIELD_RAMDOM" as an argument. The random field is supported only when base is an immediate value, random field cannot be compared with enother field. Signed-off-by: Michael Baum --- doc/guides/nics/mlx5.rst | 9 ++++- drivers/net/mlx5/mlx5_flow_hw.c | 70 ++++++++++++++++++++++++--------- 2 files changed, 59 insertions(+), 20 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index fa013b03bb..43ef8a99dc 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -820,8 +820,13 @@ Limitations - Only supported in HW steering(``dv_flow_en`` = 2) mode. - Only single flow is supported to the flow table. - - Only 32-bit comparison is supported. - - Only match with compare result between packet fields is supported. + - Only single item is supported per pattern template. + - Only 32-bit comparison is supported or 16-bits for random field. + - Only supported for ``RTE_FLOW_FIELD_META``, ``RTE_FLOW_FIELD_TAG``, + ``RTE_FLOW_FIELD_RANDOM`` and ``RTE_FLOW_FIELD_VALUE``. + - The field type ``RTE_FLOW_FIELD_VALUE`` must be the base (``b``) field. + - The field type ``RTE_FLOW_FIELD_RANDOM`` can only be compared with + ``RTE_FLOW_FIELD_VALUE``. Statistics diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 3af5e1f160..b5741f0817 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -6717,18 +6717,55 @@ flow_hw_prepend_item(const struct rte_flow_item *items, return copied_items; } -static inline bool -flow_hw_item_compare_field_supported(enum rte_flow_field_id field) +static int +flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field, + enum rte_flow_field_id base_field, + struct rte_flow_error *error) { - switch (field) { + switch (arg_field) { + case RTE_FLOW_FIELD_TAG: + case RTE_FLOW_FIELD_META: + break; + case RTE_FLOW_FIELD_RANDOM: + if (base_field == RTE_FLOW_FIELD_VALUE) + return 0; + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "compare random is supported only with immediate value"); + default: + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "compare item argument field is not supported"); + } + switch (base_field) { case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: case RTE_FLOW_FIELD_VALUE: - return true; + break; + default: + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "compare item base field is not supported"); + } + return 0; +} + +static inline uint32_t +flow_hw_item_compare_width_supported(enum rte_flow_field_id field) +{ + switch (field) { + case RTE_FLOW_FIELD_TAG: + case RTE_FLOW_FIELD_META: + return 32; + case RTE_FLOW_FIELD_RANDOM: + return 16; default: break; } - return false; + return 0; } static int @@ -6737,6 +6774,7 @@ flow_hw_validate_item_compare(const struct rte_flow_item *item, { const struct rte_flow_item_compare *comp_m = item->mask; const struct rte_flow_item_compare *comp_v = item->spec; + int ret; if (unlikely(!comp_m)) return rte_flow_error_set(error, EINVAL, @@ -6748,19 +6786,13 @@ flow_hw_validate_item_compare(const struct rte_flow_item *item, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, "compare item only support full mask"); - if (!flow_hw_item_compare_field_supported(comp_m->a.field) || - !flow_hw_item_compare_field_supported(comp_m->b.field)) - return rte_flow_error_set(error, ENOTSUP, - RTE_FLOW_ERROR_TYPE_UNSPECIFIED, - NULL, - "compare item field not support"); - if (comp_m->a.field == RTE_FLOW_FIELD_VALUE && - comp_m->b.field == RTE_FLOW_FIELD_VALUE) - return rte_flow_error_set(error, EINVAL, - RTE_FLOW_ERROR_TYPE_UNSPECIFIED, - NULL, - "compare between value is not valid"); + ret = flow_hw_item_compare_field_validate(comp_m->a.field, + comp_m->b.field, error); + if (ret < 0) + return ret; if (comp_v) { + uint32_t width; + if (comp_v->operation != comp_m->operation || comp_v->a.field != comp_m->a.field || comp_v->b.field != comp_m->b.field) @@ -6768,7 +6800,9 @@ flow_hw_validate_item_compare(const struct rte_flow_item *item, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, "compare item spec/mask not matching"); - if ((comp_v->width & comp_m->width) != 32) + width = flow_hw_item_compare_width_supported(comp_v->a.field); + MLX5_ASSERT(width > 0); + if ((comp_v->width & comp_m->width) != width) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,