From patchwork Fri Feb 9 19:43:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Prakash Shukla X-Patchwork-Id: 136576 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E9E7643AC4; Fri, 9 Feb 2024 20:44:17 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7151C4067A; Fri, 9 Feb 2024 20:44:17 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 23686402AF for ; Fri, 9 Feb 2024 20:44:15 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 419DgEbi001827 for ; Fri, 9 Feb 2024 11:44:14 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=4e41CApiy/S6VnHcFuCcRh2LHWqn5aP4q5vuMrWk6yY=; b=DrE r3uygK8xQsBD/8qPqPezhSHk7xQhe8lmxpgDQZpuds7VHAvLZVnc0CjHs9WSwFEq EkuY4knQXVp0zAlCGqYGR7+CYC68TjKa8I2KrFifw750gHdIRXJgEh4ggrwKkB6G 7XkXLWrHTyXc6yZ1NbuhEOMSVWh3bk3iugJGmqmTXN1FfFbgXvbN93VfBaex1Uok Ksa+k1jwZU1iQq4w2dhg/qJ0XkxTOPgSHJGk6AQx2UvqsvlcyBjsEfTkoI1OtudD SsoNk4BCXj5U1NpNvbAMChAYTk8WezeJkmpWgaKf+vX7KNkmS1VOR8mhsaAv7ReC cilNdGAspVGpCSlM2Wg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3w4qsq6t0d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 09 Feb 2024 11:44:14 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 9 Feb 2024 11:44:12 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 9 Feb 2024 11:44:12 -0800 Received: from cavium-OptiPlex-5090-BM14.. (unknown [10.28.36.157]) by maili.marvell.com (Postfix) with ESMTP id 4C5333F704B; Fri, 9 Feb 2024 11:44:09 -0800 (PST) From: Amit Prakash Shukla To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , , , , Subject: [PATCH v2 1/3] common/cnxk: dma result to an offset of the event Date: Sat, 10 Feb 2024 01:13:45 +0530 Message-ID: <20240209194347.2734024-1-amitprakashs@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231208082835.2817601-1-amitprakashs@marvell.com> References: <20231208082835.2817601-1-amitprakashs@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: GXp9lHzY-UaaY7vDQM6xYj1H8t9kjsFt X-Proofpoint-GUID: GXp9lHzY-UaaY7vDQM6xYj1H8t9kjsFt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-09_17,2024-02-08_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adds support to configure writing result to offset of the DMA response event. Signed-off-by: Amit Prakash Shukla --- v2: - Added dual workslot enqueue support. - Fixed compilation error. drivers/common/cnxk/roc_dpi.c | 6 +++++- drivers/common/cnxk/roc_dpi.h | 2 +- drivers/common/cnxk/roc_dpi_priv.h | 4 ++++ drivers/common/cnxk/roc_idev.c | 20 ++++++++++++++++++++ drivers/common/cnxk/roc_idev_priv.h | 3 +++ 5 files changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/roc_dpi.c b/drivers/common/cnxk/roc_dpi.c index c241168294..1ee777d779 100644 --- a/drivers/common/cnxk/roc_dpi.c +++ b/drivers/common/cnxk/roc_dpi.c @@ -83,6 +83,9 @@ roc_dpi_configure(struct roc_dpi *roc_dpi, uint32_t chunk_sz, uint64_t aura, uin mbox_msg.s.aura = aura; mbox_msg.s.sso_pf_func = idev_sso_pffunc_get(); mbox_msg.s.npa_pf_func = idev_npa_pffunc_get(); + mbox_msg.s.wqecsoff = idev_dma_cs_offset_get(); + if (mbox_msg.s.wqecsoff) + mbox_msg.s.wqecs = 1; rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg, sizeof(dpi_mbox_msg_t)); @@ -94,7 +97,7 @@ roc_dpi_configure(struct roc_dpi *roc_dpi, uint32_t chunk_sz, uint64_t aura, uin } int -roc_dpi_dev_init(struct roc_dpi *roc_dpi) +roc_dpi_dev_init(struct roc_dpi *roc_dpi, uint8_t offset) { struct plt_pci_device *pci_dev = roc_dpi->pci_dev; uint16_t vfid; @@ -103,6 +106,7 @@ roc_dpi_dev_init(struct roc_dpi *roc_dpi) vfid = ((pci_dev->addr.devid & 0x1F) << 3) | (pci_dev->addr.function & 0x7); vfid -= 1; roc_dpi->vfid = vfid; + idev_dma_cs_offset_set(offset); return 0; } diff --git a/drivers/common/cnxk/roc_dpi.h b/drivers/common/cnxk/roc_dpi.h index 4ebde5b8a6..978e2badb2 100644 --- a/drivers/common/cnxk/roc_dpi.h +++ b/drivers/common/cnxk/roc_dpi.h @@ -11,7 +11,7 @@ struct roc_dpi { uint16_t vfid; } __plt_cache_aligned; -int __roc_api roc_dpi_dev_init(struct roc_dpi *roc_dpi); +int __roc_api roc_dpi_dev_init(struct roc_dpi *roc_dpi, uint8_t offset); int __roc_api roc_dpi_dev_fini(struct roc_dpi *roc_dpi); int __roc_api roc_dpi_configure(struct roc_dpi *dpi, uint32_t chunk_sz, uint64_t aura, diff --git a/drivers/common/cnxk/roc_dpi_priv.h b/drivers/common/cnxk/roc_dpi_priv.h index 518a3e7351..52962c8bc0 100644 --- a/drivers/common/cnxk/roc_dpi_priv.h +++ b/drivers/common/cnxk/roc_dpi_priv.h @@ -31,6 +31,10 @@ typedef union dpi_mbox_msg_t { uint64_t sso_pf_func : 16; /* NPA PF function */ uint64_t npa_pf_func : 16; + /* WQE queue DMA completion status enable */ + uint64_t wqecs : 1; + /* WQE queue DMA completion status offset */ + uint64_t wqecsoff : 8; } s; } dpi_mbox_msg_t; diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c index e6c6b34d78..7b922c8bae 100644 --- a/drivers/common/cnxk/roc_idev.c +++ b/drivers/common/cnxk/roc_idev.c @@ -301,6 +301,26 @@ idev_sso_set(struct roc_sso *sso) __atomic_store_n(&idev->sso, sso, __ATOMIC_RELEASE); } +void +idev_dma_cs_offset_set(uint8_t offset) +{ + struct idev_cfg *idev = idev_get_cfg(); + + if (idev != NULL) + idev->dma_cs_offset = offset; +} + +uint8_t +idev_dma_cs_offset_get(void) +{ + struct idev_cfg *idev = idev_get_cfg(); + + if (idev != NULL) + return idev->dma_cs_offset; + + return 0; +} + uint64_t roc_idev_nix_inl_meta_aura_get(void) { diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h index 80f8465e1c..cf63c58d92 100644 --- a/drivers/common/cnxk/roc_idev_priv.h +++ b/drivers/common/cnxk/roc_idev_priv.h @@ -37,6 +37,7 @@ struct idev_cfg { struct roc_nix_list roc_nix_list; plt_spinlock_t nix_inl_dev_lock; plt_spinlock_t npa_dev_lock; + uint8_t dma_cs_offset; }; /* Generic */ @@ -55,6 +56,8 @@ void idev_sso_pffunc_set(uint16_t sso_pf_func); uint16_t idev_sso_pffunc_get(void); struct roc_sso *idev_sso_get(void); void idev_sso_set(struct roc_sso *sso); +void idev_dma_cs_offset_set(uint8_t offset); +uint8_t idev_dma_cs_offset_get(void); /* idev lmt */ uint16_t idev_lmt_pffunc_get(void);