From patchwork Tue Feb 13 16:57:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Dumitrescu X-Patchwork-Id: 136649 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9BEA643B0C; Tue, 13 Feb 2024 17:58:58 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2D71842E20; Tue, 13 Feb 2024 17:58:51 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) by mails.dpdk.org (Postfix) with ESMTP id 560CA42E0E for ; Tue, 13 Feb 2024 17:58:47 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1707843527; x=1739379527; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=oafySCeKjAc9kLr9+t0dl6lvpHcxU07qhL+D6rE6zOs=; b=QDiHI6KKa0qmuJK4JRzy/GtHLnAFdluE59UAOUQqBh5nIR/6dDwE8P8N scipvt7vLGqGp9OEzJrzTPGCWLJdLrM20isn6LOTRPdsc9/sn+B1pAR/0 aCrqGM/brILXbkLBt1fbhwzv7bi38jc51MqDcXkmNvfDbPzEwGoRqVosZ pCE8zHkf+RHl+8MWW7XcyNcjvg88Ruz9G25AFz2eMbhKJEzAyE4Wa6yYm kOR7EmZb2dEtzHyhTF9FfIMpv0mXBp2ldyaWnoWDgRbG/Mve9ekizDbXg GpwJqKxq2Oyq8MfS1tW4sSWh8ZmShFZf8Y/zBKJ8USkJLIOCM8ELT9USM A==; X-IronPort-AV: E=McAfee;i="6600,9927,10982"; a="2000498" X-IronPort-AV: E=Sophos;i="6.06,157,1705392000"; d="scan'208";a="2000498" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Feb 2024 08:57:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,157,1705392000"; d="scan'208";a="2855753" Received: from silpixa00400573.ir.intel.com (HELO silpixa00400573.ger.corp.intel.com) ([10.237.223.184]) by fmviesa007.fm.intel.com with ESMTP; 13 Feb 2024 08:57:39 -0800 From: Cristian Dumitrescu To: dev@dpdk.org Subject: [PATCH 1/3] pipeline: add new instruction for upper half of IPv6 address Date: Tue, 13 Feb 2024 16:57:35 +0000 Message-Id: <20240213165737.1534180-2-cristian.dumitrescu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240213165737.1534180-1-cristian.dumitrescu@intel.com> References: <20240213165737.1534180-1-cristian.dumitrescu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added new instruction called "movh" to read/write the upper half of an IPv6 address, i.e. bits 127-64 of a 128-bit field. Signed-off-by: Cristian Dumitrescu --- lib/pipeline/rte_swx_pipeline.c | 99 ++++++++++++++++++++++++ lib/pipeline/rte_swx_pipeline_internal.h | 52 ++++++++++++- 2 files changed, 147 insertions(+), 4 deletions(-) diff --git a/lib/pipeline/rte_swx_pipeline.c b/lib/pipeline/rte_swx_pipeline.c index da37eda231..12f335005d 100644 --- a/lib/pipeline/rte_swx_pipeline.c +++ b/lib/pipeline/rte_swx_pipeline.c @@ -3359,6 +3359,61 @@ instr_mov_i_exec(struct rte_swx_pipeline *p) thread_ip_inc(p); } +/* + * movh. + */ +static int +instr_movh_translate(struct rte_swx_pipeline *p, + struct action *action, + char **tokens, + int n_tokens, + struct instruction *instr, + struct instruction_data *data __rte_unused) +{ + char *dst = tokens[1], *src = tokens[2]; + struct field *fdst, *fsrc; + uint32_t dst_struct_id = 0, src_struct_id = 0; + + CHECK(n_tokens == 3, EINVAL); + + fdst = struct_field_parse(p, NULL, dst, &dst_struct_id); + CHECK(fdst, EINVAL); + CHECK(!fdst->var_size, EINVAL); + + fsrc = struct_field_parse(p, action, src, &src_struct_id); + CHECK(fsrc, EINVAL); + CHECK(!fsrc->var_size, EINVAL); + + /* MOVH_64_128, MOVH_128_64. */ + if ((dst[0] == 'h' && fdst->n_bits == 64 && fsrc->n_bits == 128) || + (fdst->n_bits == 128 && src[0] == 'h' && fsrc->n_bits == 64)) { + instr->type = INSTR_MOVH; + + instr->mov.dst.struct_id = (uint8_t)dst_struct_id; + instr->mov.dst.n_bits = fdst->n_bits; + instr->mov.dst.offset = fdst->offset / 8; + + instr->mov.src.struct_id = (uint8_t)src_struct_id; + instr->mov.src.n_bits = fsrc->n_bits; + instr->mov.src.offset = fsrc->offset / 8; + return 0; + } + + CHECK(0, EINVAL); +} + +static inline void +instr_movh_exec(struct rte_swx_pipeline *p) +{ + struct thread *t = &p->threads[p->thread_id]; + struct instruction *ip = t->ip; + + __instr_movh_exec(p, t, ip); + + /* Thread. */ + thread_ip_inc(p); +} + /* * dma. */ @@ -6427,6 +6482,14 @@ instr_translate(struct rte_swx_pipeline *p, instr, data); + if (!strcmp(tokens[tpos], "movh")) + return instr_movh_translate(p, + action, + &tokens[tpos], + n_tokens - tpos, + instr, + data); + if (!strcmp(tokens[tpos], "add")) return instr_alu_add_translate(p, action, @@ -7463,6 +7526,8 @@ static instr_exec_t instruction_table[] = { [INSTR_MOV_128_32] = instr_mov_128_32_exec, [INSTR_MOV_I] = instr_mov_i_exec, + [INSTR_MOVH] = instr_movh_exec, + [INSTR_DMA_HT] = instr_dma_ht_exec, [INSTR_DMA_HT2] = instr_dma_ht2_exec, [INSTR_DMA_HT3] = instr_dma_ht3_exec, @@ -11788,6 +11853,8 @@ instr_type_to_name(struct instruction *instr) case INSTR_MOV_128_32: return "INSTR_MOV_128_32"; case INSTR_MOV_I: return "INSTR_MOV_I"; + case INSTR_MOVH: return "INSTR_MOVH"; + case INSTR_DMA_HT: return "INSTR_DMA_HT"; case INSTR_DMA_HT2: return "INSTR_DMA_HT2"; case INSTR_DMA_HT3: return "INSTR_DMA_HT3"; @@ -12181,6 +12248,34 @@ instr_mov_export(struct instruction *instr, FILE *f) instr->mov.src_val); } +static void +instr_movh_export(struct instruction *instr, FILE *f) +{ + fprintf(f, + "\t{\n" + "\t\t.type = %s,\n" + "\t\t.mov = {\n" + "\t\t\t.dst = {\n" + "\t\t\t\t.struct_id = %u,\n" + "\t\t\t\t.n_bits = %u,\n" + "\t\t\t\t.offset = %u,\n" + "\t\t\t},\n" + "\t\t\t.src = {\n" + "\t\t\t\t.struct_id = %u,\n" + "\t\t\t\t.n_bits = %u,\n" + "\t\t\t\t.offset = %u,\n" + "\t\t\t},\n" + "\t\t},\n" + "\t},\n", + instr_type_to_name(instr), + instr->mov.dst.struct_id, + instr->mov.dst.n_bits, + instr->mov.dst.offset, + instr->mov.src.struct_id, + instr->mov.src.n_bits, + instr->mov.src.offset); +} + static void instr_dma_ht_export(struct instruction *instr, FILE *f) { @@ -12829,6 +12924,8 @@ static instruction_export_t export_table[] = { [INSTR_MOV_128_32] = instr_mov_export, [INSTR_MOV_I] = instr_mov_export, + [INSTR_MOVH] = instr_movh_export, + [INSTR_DMA_HT] = instr_dma_ht_export, [INSTR_DMA_HT2] = instr_dma_ht_export, [INSTR_DMA_HT3] = instr_dma_ht_export, @@ -13058,6 +13155,8 @@ instr_type_to_func(struct instruction *instr) case INSTR_MOV_128_32: return "__instr_mov_128_32_exec"; case INSTR_MOV_I: return "__instr_mov_i_exec"; + case INSTR_MOVH: return "__instr_movh_exec"; + case INSTR_DMA_HT: return "__instr_dma_ht_exec"; case INSTR_DMA_HT2: return "__instr_dma_ht2_exec"; case INSTR_DMA_HT3: return "__instr_dma_ht3_exec"; diff --git a/lib/pipeline/rte_swx_pipeline_internal.h b/lib/pipeline/rte_swx_pipeline_internal.h index 8ec12263b9..7ae7622329 100644 --- a/lib/pipeline/rte_swx_pipeline_internal.h +++ b/lib/pipeline/rte_swx_pipeline_internal.h @@ -244,20 +244,34 @@ struct header_out_runtime { * Instruction. */ -/* Packet headers are always in Network Byte Order (NBO), i.e. big endian. +/* Operand endianness conventions: + * + * Case 1: Small fields (i.e. fields with size <= 64 bits) + * + * Packet headers are always in Network Byte Order (NBO), i.e. big endian. * Packet meta-data fields are always assumed to be in Host Byte Order (HBO). * Table entry fields can be in either NBO or HBO; they are assumed to be in HBO * when transferred to packet meta-data and in NBO when transferred to packet * headers. - */ - -/* Notation conventions: + * + * Notation conventions: * -Header field: H = h.header.field (dst/src) * -Meta-data field: M = m.field (dst/src) * -Extern object mailbox field: E = e.field (dst/src) * -Extern function mailbox field: F = f.field (dst/src) * -Table action data field: T = t.field (src only) * -Immediate value: I = 32-bit unsigned value (src only) + * + * Case 2: Big fields (i.e. fields with size > 64 bits) + * + * The big fields are allowed in both headers and meta-data, but they are always + * stored in NBO. This is why the few instructions that accept a big field + * operand require that the other operand, in case it is a small operand, be + * stored in NBO as well, i.e. the small operand must be a header field + * (i.e. meta-data field not allowed in this case). + * + * Notation conventions: + * -Header or meta-data big field: HM-NBO. */ enum instruction_type { @@ -333,6 +347,17 @@ enum instruction_type { INSTR_MOV_128_32, /* dst and src in NBO format, size(dst) = 128 bits, size(src) = 32 b. */ INSTR_MOV_I, /* dst = HMEF, src = I; size(dst) <= 64 bits. */ + /* movh dst src + * Read/write the upper half (i.e. bits 127 .. 64) of a 128-bit field into/from a 64-bit + * header field: + * + * dst64 = src128[127:64], where: dst64 = H, src128 = HM-NBO. + * dst128[127:64] = src64, where: dst128 = HM-NBO, src64 = H. + * + * Typically required for operations involving IPv6 addresses. + */ + INSTR_MOVH, + /* dma h.header t.field * memcpy(h.header, t.field, sizeof(h.header)) */ @@ -2686,6 +2711,25 @@ __instr_mov_i_exec(struct rte_swx_pipeline *p __rte_unused, MOV_I(t, ip); } +/* + * movh. + */ +static inline void +__instr_movh_exec(struct rte_swx_pipeline *p __rte_unused, + struct thread *t, + const struct instruction *ip) +{ + uint8_t *dst = t->structs[ip->mov.dst.struct_id] + ip->mov.dst.offset; + uint8_t *src = t->structs[ip->mov.src.struct_id] + ip->mov.src.offset; + + uint64_t *dst64 = (uint64_t *)dst; + uint64_t *src64 = (uint64_t *)src; + + TRACE("[Thread %2u] movh\n", p->thread_id); + + dst64[0] = src64[0]; +} + /* * dma. */