From patchwork Tue Feb 20 11:04:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 136916 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B06A243B53; Tue, 20 Feb 2024 12:06:21 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 34F3542DC1; Tue, 20 Feb 2024 12:05:27 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id BDF43427E1; Tue, 20 Feb 2024 12:05:24 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41JMQxDU025082; Tue, 20 Feb 2024 03:05:24 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=TkJyml4dVWXS4OWwrIyyAyuZs10Siw0xhAWkkwv9rCg=; b=k6f Nf7Y3ph1W8px/RbqA8kMZ0ymsoS+8fmx2LEWflKRT8tFj/ahh0WKbcR4skTfwzjt yw8CScmursgQH1898txf4G6BdU9aa+09QBbXVTspZWHcE9AkH7+ve2WoY21M9A6r WdkmZMyiiqo+jYRnrnnJi3uM43O9fUsdlj1yj58s9ldfYT/sBXVkXkldRbWOVMT2 U8BoQEfamkNHJBHPGecmHWnsxCQQpsFULEtLnfZuZDIVze3WdsFkYI0zAp8VFTQq rQ/QEeWUMTyH5+9faO6w2qOMSUugoJ8A8niCWN5XP6mitLGunNvfzWDG6xSOnSrr zA8ihvEhbO7ItqxlfNw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3wcfsa1kwh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 20 Feb 2024 03:05:24 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 20 Feb 2024 03:05:21 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 20 Feb 2024 03:05:21 -0800 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id CB4F33F7089; Tue, 20 Feb 2024 03:05:19 -0800 (PST) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH v2 12/13] common/cnxk: add IO attribute to mbox structs Date: Tue, 20 Feb 2024 16:34:49 +0530 Message-ID: <20240220110450.2227277-12-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240220110450.2227277-1-ndabilpuram@marvell.com> References: <20240220110450.2227277-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: oqsszArH9dquZuQ-U7r5QN7jgWzQ59nH X-Proofpoint-ORIG-GUID: oqsszArH9dquZuQ-U7r5QN7jgWzQ59nH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-20_06,2024-02-20_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org IO attribute is needed to mbox structs to avoid unaligned or pair access causing by compiler optimization. Add them to structs where it is missing. Fixes: 503b82de2cbf ("common/cnxk: add mbox request and response definitions") Fixes: ddf955d3917e ("common/cnxk: support CPT second pass") Cc: stable@dpdk.org Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_mbox.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 3257a370bc..f1e9ad2893 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -1425,12 +1425,12 @@ struct nix_cn10k_aq_enq_req { struct nix_cn10k_aq_enq_rsp { struct mbox_msghdr hdr; union { - struct nix_cn10k_rq_ctx_s rq; - struct nix_cn10k_sq_ctx_s sq; - struct nix_cq_ctx_s cq; - struct nix_rsse_s rss; - struct nix_rx_mce_s mce; - struct nix_band_prof_s prof; + __io struct nix_cn10k_rq_ctx_s rq; + __io struct nix_cn10k_sq_ctx_s sq; + __io struct nix_cq_ctx_s cq; + __io struct nix_rsse_s rss; + __io struct nix_rx_mce_s mce; + __io struct nix_band_prof_s prof; }; }; @@ -1666,11 +1666,11 @@ struct nix_rq_cpt_field_mask_cfg_req { #define RQ_CTX_MASK_MAX 6 union { uint64_t __io rq_ctx_word_set[RQ_CTX_MASK_MAX]; - struct nix_cn10k_rq_ctx_s rq_set; + __io struct nix_cn10k_rq_ctx_s rq_set; }; union { uint64_t __io rq_ctx_word_mask[RQ_CTX_MASK_MAX]; - struct nix_cn10k_rq_ctx_s rq_mask; + __io struct nix_cn10k_rq_ctx_s rq_mask; }; struct nix_lf_rx_ipec_cfg1_req { uint32_t __io spb_cpt_aura;