From patchwork Thu Feb 22 10:05:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 137005 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C20F343B73; Thu, 22 Feb 2024 11:07:02 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9A2A840ED8; Thu, 22 Feb 2024 11:06:11 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 1616E40A76; Thu, 22 Feb 2024 11:06:06 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41M9BM46021869; Thu, 22 Feb 2024 02:06:06 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=p4ILww5cs9m2gytzehQEnXIPGv6ulsmyjsIaoCDn8mI=; b=QUC Wxffq/P8FOgVedWd7GTU1NuUjU8TQnlb3kVoRq1b0uJrCCIVGcfMOw0jx7Pqnm0J Q+qEntfpAe3NaWCa1RAt1DOiHuPKkn/RKetkocQ+YUchrVNmJnfm1DZ08+Tt0kgL A/RA0Hjwkc7E7x2zCvoxleUnR4TDUKr/FtEphA/AwUwN5H8jNXpsEfFy8Y2Djfmg k3JeO2wcELrj6K3Xaa037UBzEx9fbsaI/wd3hzcRhM9hB6exiZnPSzbJmXdRae5u 4egE0zsKxoMzNc2fZL1aZ6Ho3nuDlUCftK4wg4mlhMy37R+VGQblkiSQAFCtTSus MbOEjNQWxub4k3tobkA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3we3dw84bb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 22 Feb 2024 02:06:06 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 22 Feb 2024 02:06:04 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1258.12; Thu, 22 Feb 2024 02:06:04 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 22 Feb 2024 02:06:04 -0800 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 42F5E3F712C; Thu, 22 Feb 2024 02:06:02 -0800 (PST) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rahul Bhansali , Subject: [PATCH v3 11/14] net/cnxk: fix check cookies for multi-seg offload Date: Thu, 22 Feb 2024 15:35:27 +0530 Message-ID: <20240222100530.2266013-11-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240222100530.2266013-1-ndabilpuram@marvell.com> References: <20240222100530.2266013-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: -x_e1-AdPCr05oCmnZCPt8hGm5nwepYM X-Proofpoint-ORIG-GUID: -x_e1-AdPCr05oCmnZCPt8hGm5nwepYM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-22_08,2024-02-22_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rahul Bhansali Fix missing check cookies with multi-seg offload case Fixes: 3626d5195d49 ("net/cnxk: add multi-segment Tx for CN10K") Cc: stable@dpdk.org Signed-off-by: Rahul Bhansali --- drivers/net/cnxk/cn10k_tx.h | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index 9721b7584a..a995696e66 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -1863,6 +1863,9 @@ cn10k_nix_prepare_mseg_vec_list(struct rte_mbuf *m, uint64_t *cmd, len -= dlen; sg_u = sg_u | ((uint64_t)dlen); + /* Mark mempool object as "put" since it is freed by NIX */ + RTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0); + nb_segs = m->nb_segs - 1; m_next = m->next; m->next = NULL; @@ -1888,6 +1891,9 @@ cn10k_nix_prepare_mseg_vec_list(struct rte_mbuf *m, uint64_t *cmd, slist++; } m->next = NULL; + /* Mark mempool object as "put" since it is freed by NIX */ + RTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0); + m = m_next; } while (nb_segs); @@ -1911,8 +1917,11 @@ cn10k_nix_prepare_mseg_vec(struct rte_mbuf *m, uint64_t *cmd, uint64x2_t *cmd0, union nix_send_hdr_w0_u sh; union nix_send_sg_s sg; - if (m->nb_segs == 1) + if (m->nb_segs == 1) { + /* Mark mempool object as "put" since it is freed by NIX */ + RTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0); return; + } sh.u = vgetq_lane_u64(cmd0[0], 0); sg.u = vgetq_lane_u64(cmd1[0], 0); @@ -1972,6 +1981,11 @@ cn10k_nix_prep_lmt_mseg_vector(struct cn10k_eth_txq *txq, *data128 |= ((__uint128_t)7) << *shift; *shift += 3; + /* Mark mempool object as "put" since it is freed by NIX */ + RTE_MEMPOOL_CHECK_COOKIES(mbufs[0]->pool, (void **)&mbufs[0], 1, 0); + RTE_MEMPOOL_CHECK_COOKIES(mbufs[1]->pool, (void **)&mbufs[1], 1, 0); + RTE_MEMPOOL_CHECK_COOKIES(mbufs[2]->pool, (void **)&mbufs[2], 1, 0); + RTE_MEMPOOL_CHECK_COOKIES(mbufs[3]->pool, (void **)&mbufs[3], 1, 0); return 1; } } @@ -1990,6 +2004,11 @@ cn10k_nix_prep_lmt_mseg_vector(struct cn10k_eth_txq *txq, vst1q_u64(lmt_addr + 10, cmd2[j + 1]); vst1q_u64(lmt_addr + 12, cmd1[j + 1]); vst1q_u64(lmt_addr + 14, cmd3[j + 1]); + + /* Mark mempool object as "put" since it is freed by NIX */ + RTE_MEMPOOL_CHECK_COOKIES(mbufs[j]->pool, (void **)&mbufs[j], 1, 0); + RTE_MEMPOOL_CHECK_COOKIES(mbufs[j + 1]->pool, + (void **)&mbufs[j + 1], 1, 0); } else if (flags & NIX_TX_NEED_EXT_HDR) { /* EXT header take 3 each, space for 2 segs.*/ cn10k_nix_prepare_mseg_vec(mbufs[j],