From patchwork Thu Feb 22 10:05:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 137001 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1963E43B73; Thu, 22 Feb 2024 11:06:33 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2F40840DFB; Thu, 22 Feb 2024 11:05:58 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 98FC7406B8 for ; Thu, 22 Feb 2024 11:05:56 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41M9BLWA021847 for ; Thu, 22 Feb 2024 02:05:55 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=SVG3OGxMfdQbvjclZmQ0itusqHjtbMGiJMspPR1US9g=; b=cQE MBtOCxugg+yLNVbWp22MgeDtLdrJIKH9vYs0/9hgTAgC56BSe9YnmSbtoRnEFDmd v3lQhVjA0gpgrtaGwUKZYNSFY3kIy7645Jkd1lr5L4NaQYnsnQCT4EPf1jfI304d hS4AaafuZzi0Fac1fCB9WtSEk2ZOKph7cOoH5ay1u/+vsWp8oB3h+RakPO/M+oVf NghBs/jczyfvm5wKfOVs5rx5zl2g4SgG8ZLo6v3Q6lpREi1wd3Z0pmPF174j4PjE 3W6ZIx5w06im9oQadtK1G5qzkr9smNXB0FIha9WFG4Pk4JVrRa0Oa7fpp8KJjQNi N1JnvPk+j7znDwXL2WA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3we3dw84ab-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 22 Feb 2024 02:05:55 -0800 (PST) Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 22 Feb 2024 02:05:53 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 22 Feb 2024 02:05:53 -0800 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id EF1C73F712C; Thu, 22 Feb 2024 02:05:51 -0800 (PST) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Subject: [PATCH v3 07/14] common/cnxk: skip setting Tx MTU separately Date: Thu, 22 Feb 2024 15:35:23 +0530 Message-ID: <20240222100530.2266013-7-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240222100530.2266013-1-ndabilpuram@marvell.com> References: <20240222100530.2266013-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: J1WeuvgzGNYpGl58MA9se5P9PEc6bLOp X-Proofpoint-ORIG-GUID: J1WeuvgzGNYpGl58MA9se5P9PEc6bLOp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-22_08,2024-02-22_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Skip setting Tx MTU separately as now the Tx credit configuration is based on max MTU possible for that link. Also init MTU with max value for that port. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_nix.c | 2 +- drivers/common/cnxk/roc_nix.h | 2 -- drivers/net/cnxk/cnxk_ethdev_ops.c | 12 +----------- 3 files changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index f64933a1d9..afbc3eb901 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -482,7 +482,7 @@ roc_nix_dev_init(struct roc_nix *roc_nix) sdp_lbk_id_update(pci_dev, nix); nix->pci_dev = pci_dev; nix->reta_sz = reta_sz; - nix->mtu = ROC_NIX_DEFAULT_HW_FRS; + nix->mtu = roc_nix_max_pkt_len(roc_nix); nix->dmac_flt_idx = -1; /* Register error and ras interrupts */ diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 9d57ca0be7..3799b551f2 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -267,8 +267,6 @@ struct roc_nix_eeprom_info { #define ROC_NIX_RSS_KEY_LEN 48 /* 352 Bits */ #define ROC_NIX_RSS_MCAM_IDX_DEFAULT (-1) -#define ROC_NIX_DEFAULT_HW_FRS 1514 - #define ROC_NIX_VWQE_MAX_SIZE_LOG2 11 #define ROC_NIX_VWQE_MIN_SIZE_LOG2 2 diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c index e816884d47..4962f3bced 100644 --- a/drivers/net/cnxk/cnxk_ethdev_ops.c +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -610,19 +610,9 @@ cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) frame_size -= RTE_ETHER_CRC_LEN; - /* Update mtu on Tx */ - rc = roc_nix_mac_mtu_set(nix, frame_size); - if (rc) { - plt_err("Failed to set MTU, rc=%d", rc); - goto exit; - } - - /* Sync same frame size on Rx */ + /* Set frame size on Rx */ rc = roc_nix_mac_max_rx_len_set(nix, frame_size); if (rc) { - /* Rollback to older mtu */ - roc_nix_mac_mtu_set(nix, - old_frame_size - RTE_ETHER_CRC_LEN); plt_err("Failed to max Rx frame length, rc=%d", rc); goto exit; }