From patchwork Mon Feb 26 13:35:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 137225 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E9F9643BED; Mon, 26 Feb 2024 14:37:21 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9D7C642EAC; Mon, 26 Feb 2024 14:36:25 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 1DC4942E96 for ; Mon, 26 Feb 2024 14:36:19 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41Q9thj4016559 for ; Mon, 26 Feb 2024 05:36:19 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=sLY6dYAAayTUnio/Oohss80s1Mp5zeA+eIFqcJD01WQ=; b=Ist nDcKTgPKYLsOpvb7B8POCxnPINsjZLSCSSuUbbpheg2baseoDzTyHhbeEgb/Gt6Z SXlQhIHV+HaHZSglH9ztzcaD0750Iq42gbZnXMn9Ir9++xIGqinFq10mwcrooQlC iVuCPTy/5uWvYP2oCgerdKkA6maTB1FjhbLgnfYEvicyICQzKECW8lAHcAeWGaOX nz2fkmdaPsVdtvAAK39F2bGf/T56A464qcTz9s8euE75Nwz0iXBWnlxJmU6RXl9m 3uSzKC3amCbL/Ab2w3CID4xD/ZXY+3Ri5gVrMcoQuyrAE9iW1LmOmp5927A3Xrxf Ib2xsmRrGSrkKM7AWDA== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wgre8rjc5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 26 Feb 2024 05:36:19 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1258.12; Mon, 26 Feb 2024 05:36:18 -0800 Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 26 Feb 2024 05:36:17 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 26 Feb 2024 05:36:17 -0800 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 7A91D3F708F; Mon, 26 Feb 2024 05:36:15 -0800 (PST) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rahul Bhansali Subject: [PATCH v5 14/14] net/cnxk: fix mbuf fields in multi-seg Tx path Date: Mon, 26 Feb 2024 19:05:36 +0530 Message-ID: <20240226133536.2456406-14-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240226133536.2456406-1-ndabilpuram@marvell.com> References: <20240208085956.1741174-1-ndabilpuram@marvell.com> <20240226133536.2456406-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: qhB5t2y_1skaO0WgU14IToxdD-J6lBZZ X-Proofpoint-GUID: qhB5t2y_1skaO0WgU14IToxdD-J6lBZZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-26_09,2024-02-26_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rahul Bhansali Currently in debug mode when a buffer is allocated in SW, nb_segs will have invalid values as it didn't come from driver Rx path. Hence reset mbuf next and nb_segs fields in multi-seg Tx path. Fixes: 3626d5195d49 ("net/cnxk: add multi-segment Tx for CN10K") Signed-off-by: Rahul Bhansali --- drivers/net/cnxk/cn10k_tx.h | 2 ++ drivers/net/cnxk/cn9k_tx.h | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index 84d71d0818..cc480d24e8 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -1328,6 +1328,7 @@ cn10k_nix_prepare_mseg(struct cn10k_eth_txq *txq, nb_segs = m->nb_segs - 1; m_next = m->next; m->next = NULL; + m->nb_segs = 1; slist = &cmd[3 + off + 1]; cookie = RTE_MBUF_DIRECT(m) ? m : rte_mbuf_from_indirect(m); @@ -1873,6 +1874,7 @@ cn10k_nix_prepare_mseg_vec_list(struct rte_mbuf *m, uint64_t *cmd, nb_segs = m->nb_segs - 1; m_next = m->next; m->next = NULL; + m->nb_segs = 1; m = m_next; /* Fill mbuf segments */ do { diff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h index 3596651cc2..94acbe64fa 100644 --- a/drivers/net/cnxk/cn9k_tx.h +++ b/drivers/net/cnxk/cn9k_tx.h @@ -647,6 +647,10 @@ cn9k_nix_prepare_mseg(struct cn9k_eth_txq *txq, rte_io_wmb(); #else RTE_SET_USED(cookie); +#endif +#ifdef RTE_ENABLE_ASSERT + m->next = NULL; + m->nb_segs = 1; #endif m = m_next; if (!m) @@ -683,6 +687,9 @@ cn9k_nix_prepare_mseg(struct cn9k_eth_txq *txq, sg_u = sg->u; slist++; } +#ifdef RTE_ENABLE_ASSERT + m->next = NULL; +#endif m = m_next; } while (nb_segs); @@ -696,6 +703,9 @@ cn9k_nix_prepare_mseg(struct cn9k_eth_txq *txq, segdw += (off >> 1) + 1 + !!(flags & NIX_TX_OFFLOAD_TSTAMP_F); send_hdr->w0.sizem1 = segdw - 1; +#ifdef RTE_ENABLE_ASSERT + rte_io_wmb(); +#endif return segdw; } @@ -912,6 +922,10 @@ cn9k_nix_prepare_mseg_vec_list(struct cn9k_eth_txq *txq, RTE_SET_USED(cookie); #endif +#ifdef RTE_ENABLE_ASSERT + m->next = NULL; + m->nb_segs = 1; +#endif m = m_next; /* Fill mbuf segments */ do { @@ -942,6 +956,9 @@ cn9k_nix_prepare_mseg_vec_list(struct cn9k_eth_txq *txq, sg_u = sg->u; slist++; } +#ifdef RTE_ENABLE_ASSERT + m->next = NULL; +#endif m = m_next; } while (nb_segs); @@ -957,6 +974,9 @@ cn9k_nix_prepare_mseg_vec_list(struct cn9k_eth_txq *txq, !!(flags & NIX_TX_OFFLOAD_TSTAMP_F); send_hdr->w0.sizem1 = segdw - 1; +#ifdef RTE_ENABLE_ASSERT + rte_io_wmb(); +#endif return segdw; }