[v3,1/4] common/qat: add new gen3 device

Message ID 20240226170818.533793-2-ciara.power@intel.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers
Series add new QAT gen3 and gen5 |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Ciara Power Feb. 26, 2024, 5:08 p.m. UTC
  Add new gen3 QAT device ID.
This device has a wireless slice, but other gen3 devices do not, so we
must set a flag to indicate this wireless enabled device.

Capabilities for the device are slightly different from base gen3
capabilities, some are removed from the list for this device.

Symmetric, asymmetric and compression services are enabled.

Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Kai Ji <kai.ji@intel.com>
---
v2: Added documentation updates.
---
 doc/guides/compressdevs/qat_comp.rst         |  1 +
 doc/guides/cryptodevs/qat.rst                |  2 ++
 doc/guides/rel_notes/release_24_03.rst       |  4 ++++
 drivers/common/qat/qat_device.c              | 13 +++++++++++++
 drivers/common/qat/qat_device.h              |  2 ++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 11 +++++++++++
 6 files changed, 33 insertions(+)
  

Patch

diff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst
index 475c4a9f9f..338b1bf623 100644
--- a/doc/guides/compressdevs/qat_comp.rst
+++ b/doc/guides/compressdevs/qat_comp.rst
@@ -10,6 +10,7 @@  support for the following hardware accelerator devices:
 * ``Intel QuickAssist Technology C62x``
 * ``Intel QuickAssist Technology C3xxx``
 * ``Intel QuickAssist Technology DH895x``
+* ``Intel QuickAssist Technology 300xx``
 
 
 Features
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index dc6b95165d..51190e12d6 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -26,6 +26,7 @@  poll mode crypto driver support for the following hardware accelerator devices:
 * ``Intel QuickAssist Technology D15xx``
 * ``Intel QuickAssist Technology C4xxx``
 * ``Intel QuickAssist Technology 4xxx``
+* ``Intel QuickAssist Technology 300xx``
 
 
 Features
@@ -177,6 +178,7 @@  poll mode crypto driver support for the following hardware accelerator devices:
 * ``Intel QuickAssist Technology C4xxx``
 * ``Intel QuickAssist Technology 4xxx``
 * ``Intel QuickAssist Technology 401xxx``
+* ``Intel QuickAssist Technology 300xx``
 
 The QAT ASYM PMD has support for:
 
diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst
index 879bb4944c..55517eabd8 100644
--- a/doc/guides/rel_notes/release_24_03.rst
+++ b/doc/guides/rel_notes/release_24_03.rst
@@ -131,6 +131,10 @@  New Features
   * Added support for comparing result between packet fields or value.
   * Added support for accumulating value of field into another one.
 
+* **Updated Intel QuickAssist Technology driver.**
+
+  * Enabled support for new QAT GEN3 (578a) devices in QAT crypto driver.
+
 * **Updated Marvell cnxk crypto driver.**
 
   * Added support for Rx inject in crypto_cn10k.
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index f55dc3c6f0..0e7d387d78 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -53,6 +53,9 @@  static const struct rte_pci_id pci_id_qat_map[] = {
 		{
 			RTE_PCI_DEVICE(0x8086, 0x18a1),
 		},
+		{
+			RTE_PCI_DEVICE(0x8086, 0x578b),
+		},
 		{
 			RTE_PCI_DEVICE(0x8086, 0x4941),
 		},
@@ -194,6 +197,7 @@  pick_gen(const struct rte_pci_device *pci_dev)
 	case 0x18ef:
 		return QAT_GEN2;
 	case 0x18a1:
+	case 0x578b:
 		return QAT_GEN3;
 	case 0x4941:
 	case 0x4943:
@@ -205,6 +209,12 @@  pick_gen(const struct rte_pci_device *pci_dev)
 	}
 }
 
+static int
+wireless_slice_support(uint16_t pci_dev_id)
+{
+	return pci_dev_id == 0x578b;
+}
+
 struct qat_pci_device *
 qat_pci_device_allocate(struct rte_pci_device *pci_dev,
 		struct qat_dev_cmd_param *qat_dev_cmd_param)
@@ -282,6 +292,9 @@  qat_pci_device_allocate(struct rte_pci_device *pci_dev,
 	qat_dev->qat_dev_id = qat_dev_id;
 	qat_dev->qat_dev_gen = qat_dev_gen;
 
+	if (wireless_slice_support(pci_dev->id.device_id))
+		qat_dev->has_wireless_slice = 1;
+
 	ops_hw = qat_dev_hw_spec[qat_dev->qat_dev_gen];
 	NOT_NULL(ops_hw->qat_dev_get_misc_bar, goto error,
 		"QAT internal error! qat_dev_get_misc_bar function not set");
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index aa7988bb74..43e4752812 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -135,6 +135,8 @@  struct qat_pci_device {
 	/**< Per generation specific information */
 	uint32_t slice_map;
 	/**< Map of the crypto and compression slices */
+	uint16_t has_wireless_slice;
+	/**< Wireless Slices supported */
 };
 
 struct qat_gen_hw_data {
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
index 02bcdb06b1..bc53e2e0f1 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
@@ -255,6 +255,17 @@  qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals,
 				RTE_CRYPTO_AUTH_SM3_HMAC))) {
 			continue;
 		}
+		if (internals->qat_dev->has_wireless_slice && (
+			check_auth_capa(&capabilities[iter],
+				RTE_CRYPTO_AUTH_KASUMI_F9) ||
+			check_cipher_capa(&capabilities[iter],
+				RTE_CRYPTO_CIPHER_KASUMI_F8) ||
+			check_cipher_capa(&capabilities[iter],
+				RTE_CRYPTO_CIPHER_DES_CBC) ||
+			check_cipher_capa(&capabilities[iter],
+				RTE_CRYPTO_CIPHER_DES_DOCSISBPI)))
+			continue;
+
 		memcpy(addr + curr_capa, capabilities + iter,
 			sizeof(struct rte_cryptodev_capabilities));
 		curr_capa++;