From patchwork Tue Jun 9 12:29:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dybkowski, AdamX" X-Patchwork-Id: 71060 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3E2FEA0516; Tue, 9 Jun 2020 14:30:04 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C583D1BED9; Tue, 9 Jun 2020 14:30:03 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 7431D1BED9 for ; Tue, 9 Jun 2020 14:30:01 +0200 (CEST) IronPort-SDR: DHT2NKkAa7iJ/dPqV9/u+O4pilaHe+e1R5vt+g6+VC4xptpxknGY1vwLOK3RJ+UBCLTLzBKTLp HnZQioqpJcsw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2020 05:30:00 -0700 IronPort-SDR: mX+zHvPlHOY2oOPVTJbfUV2Ty7YGM0SaxhmNIpEQ7W424dzxEJhA+ZvdOKlEAxIdVwp7R01eWW jDxCOkAK26CA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,492,1583222400"; d="scan'208";a="306175538" Received: from adamdybx-mobl.ger.corp.intel.com ([10.104.125.43]) by fmsmga002.fm.intel.com with ESMTP; 09 Jun 2020 05:29:58 -0700 From: Adam Dybkowski To: dev@dpdk.org, fiona.trahe@intel.com, akhil.goyal@nxp.com Cc: Adam Dybkowski Date: Tue, 9 Jun 2020 14:29:58 +0200 Message-Id: <20200609122958.4755-1-adamx.dybkowski@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH] common/qat: support GEN2 device C34xx X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This adds pci detection and documentation for Intel GEN2 QuickAssist device C34xx (PF Did 0x18ee, VF Did 0x18ef). Signed-off-by: Adam Dybkowski --- doc/guides/compressdevs/qat_comp.rst | 3 ++- doc/guides/cryptodevs/qat.rst | 8 ++++++-- doc/guides/rel_notes/release_20_08.rst | 5 +++++ drivers/common/qat/qat_device.c | 6 +++++- 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst index 475c4a9f9..93757957a 100644 --- a/doc/guides/compressdevs/qat_comp.rst +++ b/doc/guides/compressdevs/qat_comp.rst @@ -1,5 +1,5 @@ .. SPDX-License-Identifier: BSD-3-Clause - Copyright(c) 2018 Intel Corporation. + Copyright(c) 2018-2020 Intel Corporation. Intel(R) QuickAssist (QAT) Compression Poll Mode Driver ======================================================= @@ -9,6 +9,7 @@ support for the following hardware accelerator devices: * ``Intel QuickAssist Technology C62x`` * ``Intel QuickAssist Technology C3xxx`` +* ``Intel QuickAssist Technology C34xx`` * ``Intel QuickAssist Technology DH895x`` diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index c2cc3d5ca..8311abffe 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -22,6 +22,7 @@ poll mode crypto driver support for the following hardware accelerator devices: * ``Intel QuickAssist Technology DH895xCC`` * ``Intel QuickAssist Technology C62x`` * ``Intel QuickAssist Technology C3xxx`` +* ``Intel QuickAssist Technology C34xx`` * ``Intel QuickAssist Technology D15xx`` * ``Intel QuickAssist Technology P5xxx`` @@ -154,6 +155,7 @@ poll mode crypto driver support for the following hardware accelerator devices: * ``Intel QuickAssist Technology DH895xCC`` * ``Intel QuickAssist Technology C62x`` * ``Intel QuickAssist Technology C3xxx`` +* ``Intel QuickAssist Technology C34xx`` * ``Intel QuickAssist Technology D15xx`` * ``Intel QuickAssist Technology P5xxx`` @@ -383,6 +385,8 @@ to see the full table) +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ | Yes | Yes | Yes | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ + | Yes | Yes | Yes | 2 | C34xx | p | qat_c34xx | c34xx | 18ee | 1 | 18ef | 16 | + +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ | Yes | No | No | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 | +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ | Yes | No | No | 3 | P5xxx | p | qat_p5xxx | p5xxx | 18a0 | 1 | 18a1 | 128 | @@ -609,8 +613,8 @@ adjust the unbind command below:: done; \ done -For Intel(R) QuickAssist Technology C3xxx or D15xx device -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +For Intel(R) QuickAssist Technology C3xxx or C34xx or D15xx device +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The unbind command below assumes ``BDFs`` of ``01:01.00-01:02.07``, if your VFs are different adjust the unbind command below:: diff --git a/doc/guides/rel_notes/release_20_08.rst b/doc/guides/rel_notes/release_20_08.rst index 39064afbe..29c380532 100644 --- a/doc/guides/rel_notes/release_20_08.rst +++ b/doc/guides/rel_notes/release_20_08.rst @@ -56,6 +56,11 @@ New Features Also, make sure to start the actual text at the margin. ========================================================= +* **Added support for GEN2 device C34xx to Intel QAT driver.** + + Added support for Intel GEN2 QuickAssist device C34xx + (PF Did 0x18ee, VF Did 0x18ef). + Removed Items ------------- diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c index 2b41d9a13..b135eb869 100644 --- a/drivers/common/qat/qat_device.c +++ b/drivers/common/qat/qat_device.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2018 Intel Corporation + * Copyright(c) 2018-2020 Intel Corporation */ #include @@ -53,6 +53,9 @@ static const struct rte_pci_id pci_id_qat_map[] = { { RTE_PCI_DEVICE(0x8086, 0x6f55), }, + { + RTE_PCI_DEVICE(0x8086, 0x18ef), + }, { RTE_PCI_DEVICE(0x8086, 0x18a1), }, @@ -199,6 +202,7 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev, case 0x37c9: case 0x19e3: case 0x6f55: + case 0x18ef: qat_dev->qat_dev_gen = QAT_GEN2; break; case 0x18a1: