From patchwork Wed Sep 30 13:03:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79338 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2974EA04B5; Wed, 30 Sep 2020 15:08:27 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3D54A1D629; Wed, 30 Sep 2020 15:08:10 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id A173D1D614 for ; Wed, 30 Sep 2020 15:08:05 +0200 (CEST) IronPort-SDR: lo7p61BFbjQC5HgDRQZR+A8IMZFC1uOHYdde0rZqqPm4j936nroYszyqdf7pABdsRIFf/QxEDv k4kD67dmbVHw== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223433" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223433" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:04 -0700 IronPort-SDR: 3U4m/nSfvIKmbqcXwTy3cqH5e+EpM8piFRdnRl7CqNARzcCwTaNTiv5YC3U4OhLpEMOlWsTql3 XOTo//18MWiA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603152" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:02 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Ray Kinsella , Neil Horman Date: Wed, 30 Sep 2020 14:03:57 +0100 Message-Id: <20200930130415.11211-2-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 01/18] eal: add max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds a max SIMD bitwidth EAL configuration. The API allows for an app to set this value. It can also be set using EAL argument --force-max-simd-bitwidth, which will lock the value and override any modifications made by the app. Signed-off-by: Ciara Power --- v3: - Added enum value to essentially disable using max SIMD to choose paths, intended for use by ARM SVE. - Fixed parsing bitwidth argument to return an error for values greater than uint16_t. v2: Added to Doxygen comment for API. --- lib/librte_eal/common/eal_common_options.c | 64 ++++++++++++++++++++++ lib/librte_eal/common/eal_internal_cfg.h | 8 +++ lib/librte_eal/common/eal_options.h | 2 + lib/librte_eal/include/rte_eal.h | 33 +++++++++++ lib/librte_eal/rte_eal_version.map | 4 ++ 5 files changed, 111 insertions(+) diff --git a/lib/librte_eal/common/eal_common_options.c b/lib/librte_eal/common/eal_common_options.c index a5426e1234..e9117a96af 100644 --- a/lib/librte_eal/common/eal_common_options.c +++ b/lib/librte_eal/common/eal_common_options.c @@ -102,6 +102,7 @@ eal_long_options[] = { {OPT_MATCH_ALLOCATIONS, 0, NULL, OPT_MATCH_ALLOCATIONS_NUM}, {OPT_TELEMETRY, 0, NULL, OPT_TELEMETRY_NUM }, {OPT_NO_TELEMETRY, 0, NULL, OPT_NO_TELEMETRY_NUM }, + {OPT_FORCE_MAX_SIMD_BITWIDTH, 1, NULL, OPT_FORCE_MAX_SIMD_BITWIDTH_NUM}, {0, 0, NULL, 0 } }; @@ -1309,6 +1310,34 @@ eal_parse_iova_mode(const char *name) return 0; } +static int +eal_parse_simd_bitwidth(const char *arg, bool locked) +{ + char *end; + unsigned long bitwidth; + int ret; + struct internal_config *internal_conf = + eal_get_internal_configuration(); + + if (arg == NULL || arg[0] == '\0') + return -1; + + errno = 0; + bitwidth = strtoul(arg, &end, 0); + + /* check for errors */ + if (bitwidth > UINT16_MAX || errno != 0 || end == NULL || *end != '\0') + return -1; + + if (bitwidth == 0) + bitwidth = UINT16_MAX; + ret = rte_set_max_simd_bitwidth(bitwidth); + if (ret < 0) + return -1; + internal_conf->max_simd_bitwidth.locked = locked; + return 0; +} + static int eal_parse_base_virtaddr(const char *arg) { @@ -1707,6 +1736,13 @@ eal_parse_common_option(int opt, const char *optarg, case OPT_NO_TELEMETRY_NUM: conf->no_telemetry = 1; break; + case OPT_FORCE_MAX_SIMD_BITWIDTH_NUM: + if (eal_parse_simd_bitwidth(optarg, 1) < 0) { + RTE_LOG(ERR, EAL, "invalid parameter for --" + OPT_FORCE_MAX_SIMD_BITWIDTH "\n"); + return -1; + } + break; /* don't know what to do, leave this to caller */ default: @@ -1903,6 +1939,33 @@ eal_check_common_options(struct internal_config *internal_cfg) return 0; } +uint16_t +rte_get_max_simd_bitwidth(void) +{ + const struct internal_config *internal_conf = + eal_get_internal_configuration(); + return internal_conf->max_simd_bitwidth.bitwidth; +} + +int +rte_set_max_simd_bitwidth(uint16_t bitwidth) +{ + struct internal_config *internal_conf = + eal_get_internal_configuration(); + if (internal_conf->max_simd_bitwidth.locked) { + RTE_LOG(NOTICE, EAL, "Cannot set max SIMD bitwidth - user runtime override enabled"); + return -EPERM; + } + + if (bitwidth != RTE_MAX_SIMD_DISABLE && (bitwidth < RTE_NO_SIMD || + !rte_is_power_of_2(bitwidth))) { + RTE_LOG(ERR, EAL, "Invalid bitwidth value!\n"); + return -EINVAL; + } + internal_conf->max_simd_bitwidth.bitwidth = bitwidth; + return 0; +} + void eal_common_usage(void) { @@ -1981,6 +2044,7 @@ eal_common_usage(void) " --"OPT_BASE_VIRTADDR" Base virtual address\n" " --"OPT_TELEMETRY" Enable telemetry support (on by default)\n" " --"OPT_NO_TELEMETRY" Disable telemetry support\n" + " --"OPT_FORCE_MAX_SIMD_BITWIDTH" Force the max SIMD bitwidth\n" "\nEAL options for DEBUG use only:\n" " --"OPT_HUGE_UNLINK" Unlink hugepage files after init\n" " --"OPT_NO_HUGE" Use malloc instead of hugetlbfs\n" diff --git a/lib/librte_eal/common/eal_internal_cfg.h b/lib/librte_eal/common/eal_internal_cfg.h index 13f93388a7..367e0cc19e 100644 --- a/lib/librte_eal/common/eal_internal_cfg.h +++ b/lib/librte_eal/common/eal_internal_cfg.h @@ -33,6 +33,12 @@ struct hugepage_info { int lock_descriptor; /**< file descriptor for hugepage dir */ }; +struct simd_bitwidth { + /**< flag indicating if bitwidth is locked from further modification */ + bool locked; + uint16_t bitwidth; /**< bitwidth value */ +}; + /** * internal configuration */ @@ -85,6 +91,8 @@ struct internal_config { volatile unsigned int init_complete; /**< indicates whether EAL has completed initialization */ unsigned int no_telemetry; /**< true to disable Telemetry */ + /** max simd bitwidth path to use */ + struct simd_bitwidth max_simd_bitwidth; }; void eal_reset_internal_config(struct internal_config *internal_cfg); diff --git a/lib/librte_eal/common/eal_options.h b/lib/librte_eal/common/eal_options.h index 89769d48b4..ef33979664 100644 --- a/lib/librte_eal/common/eal_options.h +++ b/lib/librte_eal/common/eal_options.h @@ -85,6 +85,8 @@ enum { OPT_TELEMETRY_NUM, #define OPT_NO_TELEMETRY "no-telemetry" OPT_NO_TELEMETRY_NUM, +#define OPT_FORCE_MAX_SIMD_BITWIDTH "force-max-simd-bitwidth" + OPT_FORCE_MAX_SIMD_BITWIDTH_NUM, OPT_LONG_MAX_NUM }; diff --git a/lib/librte_eal/include/rte_eal.h b/lib/librte_eal/include/rte_eal.h index ddcf6a2e7a..fb739f3474 100644 --- a/lib/librte_eal/include/rte_eal.h +++ b/lib/librte_eal/include/rte_eal.h @@ -43,6 +43,14 @@ enum rte_proc_type_t { RTE_PROC_INVALID }; +enum rte_max_simd_t { + RTE_NO_SIMD = 64, + RTE_MAX_128_SIMD = 128, + RTE_MAX_256_SIMD = 256, + RTE_MAX_512_SIMD = 512, + RTE_MAX_SIMD_DISABLE = UINT16_MAX, +}; + /** * Get the process type in a multi-process setup * @@ -51,6 +59,31 @@ enum rte_proc_type_t { */ enum rte_proc_type_t rte_eal_process_type(void); +/** + * Get the supported SIMD bitwidth. + * + * @return + * uint16_t bitwidth. + */ +__rte_experimental +uint16_t rte_get_max_simd_bitwidth(void); + +/** + * Set the supported SIMD bitwidth. + * This API should only be called once at initialization, before EAL init. + * + * @param bitwidth + * uint16_t bitwidth. + * @return + * 0 on success. + * @return + * -EINVAL on invalid bitwidth parameter. + * @return + * -EPERM if bitwidth is locked. + */ +__rte_experimental +int rte_set_max_simd_bitwidth(uint16_t bitwidth); + /** * Request iopl privilege for all RPL. * diff --git a/lib/librte_eal/rte_eal_version.map b/lib/librte_eal/rte_eal_version.map index c32461c663..17a7195a3d 100644 --- a/lib/librte_eal/rte_eal_version.map +++ b/lib/librte_eal/rte_eal_version.map @@ -397,6 +397,10 @@ EXPERIMENTAL { rte_service_lcore_may_be_active; rte_thread_register; rte_thread_unregister; + + # added in 20.11 + rte_get_max_simd_bitwidth; + rte_set_max_simd_bitwidth; }; INTERNAL { From patchwork Wed Sep 30 13:03:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79339 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 07585A04B5; Wed, 30 Sep 2020 15:08:45 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 107FE1DA10; Wed, 30 Sep 2020 15:08:12 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 19A5A1D619 for ; Wed, 30 Sep 2020 15:08:06 +0200 (CEST) IronPort-SDR: 4z/LzyksNqQS5Ry3HitqHW9JFIoKDXP7quMpCuvMT32eGmp8NX0HNVSjADnBPaL1tleVfXB5IR 5Epn3P/EoKyA== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223441" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223441" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:06 -0700 IronPort-SDR: 280JDzs4QW/IroXsDY2Fn/1+VVotWSMydoX5F9GJxf9W6TQR2Vy38RHpPkdSB1U1TLzI04RrAN JCBy4iss3okQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603170" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:04 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Ruifeng Wang , Jerin Jacob , Honnappa Nagarahalli , David Christensen , Jan Viktorin , Bruce Richardson , Konstantin Ananyev Date: Wed, 30 Sep 2020 14:03:58 +0100 Message-Id: <20200930130415.11211-3-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 02/18] eal: add default SIMD bitwidth values X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Each arch has a define for the default SIMD bitwidth value, this is used on EAL init to set the config max SIMD bitwidth. Cc: Ruifeng Wang Cc: Jerin Jacob Cc: Honnappa Nagarahalli Cc: David Christensen Signed-off-by: Ciara Power Reviewed-By: David Christensen --- v3: - Removed unnecessary define in generic rte_vect.h - Changed default bitwidth for ARM to UINT16_MAX, to allow for SVE. v2: Changed default bitwidth for Arm to 128. --- lib/librte_eal/arm/include/rte_vect.h | 2 ++ lib/librte_eal/common/eal_common_options.c | 3 +++ lib/librte_eal/ppc/include/rte_vect.h | 2 ++ lib/librte_eal/x86/include/rte_vect.h | 2 ++ 4 files changed, 9 insertions(+) diff --git a/lib/librte_eal/arm/include/rte_vect.h b/lib/librte_eal/arm/include/rte_vect.h index 01c51712a1..a3508e69d5 100644 --- a/lib/librte_eal/arm/include/rte_vect.h +++ b/lib/librte_eal/arm/include/rte_vect.h @@ -14,6 +14,8 @@ extern "C" { #endif +#define RTE_DEFAULT_SIMD_BITWIDTH UINT16_MAX + typedef int32x4_t xmm_t; #define XMM_SIZE (sizeof(xmm_t)) diff --git a/lib/librte_eal/common/eal_common_options.c b/lib/librte_eal/common/eal_common_options.c index e9117a96af..d412cae89b 100644 --- a/lib/librte_eal/common/eal_common_options.c +++ b/lib/librte_eal/common/eal_common_options.c @@ -35,6 +35,7 @@ #ifndef RTE_EXEC_ENV_WINDOWS #include #endif +#include #include "eal_internal_cfg.h" #include "eal_options.h" @@ -344,6 +345,8 @@ eal_reset_internal_config(struct internal_config *internal_cfg) internal_cfg->user_mbuf_pool_ops_name = NULL; CPU_ZERO(&internal_cfg->ctrl_cpuset); internal_cfg->init_complete = 0; + internal_cfg->max_simd_bitwidth.bitwidth = RTE_DEFAULT_SIMD_BITWIDTH; + internal_cfg->max_simd_bitwidth.locked = 0; } static int diff --git a/lib/librte_eal/ppc/include/rte_vect.h b/lib/librte_eal/ppc/include/rte_vect.h index b0545c878c..70fbd0c423 100644 --- a/lib/librte_eal/ppc/include/rte_vect.h +++ b/lib/librte_eal/ppc/include/rte_vect.h @@ -15,6 +15,8 @@ extern "C" { #endif +#define RTE_DEFAULT_SIMD_BITWIDTH 256 + typedef vector signed int xmm_t; #define XMM_SIZE (sizeof(xmm_t)) diff --git a/lib/librte_eal/x86/include/rte_vect.h b/lib/librte_eal/x86/include/rte_vect.h index df5a607623..b1df75aca7 100644 --- a/lib/librte_eal/x86/include/rte_vect.h +++ b/lib/librte_eal/x86/include/rte_vect.h @@ -35,6 +35,8 @@ extern "C" { #endif +#define RTE_DEFAULT_SIMD_BITWIDTH 256 + typedef __m128i xmm_t; #define XMM_SIZE (sizeof(xmm_t)) From patchwork Wed Sep 30 13:03:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79340 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C31D3A04B5; Wed, 30 Sep 2020 15:09:09 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F3F771DAE6; Wed, 30 Sep 2020 15:08:16 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 41B321D630 for ; Wed, 30 Sep 2020 15:08:10 +0200 (CEST) IronPort-SDR: 9QJImaHHn9+KVhQInaxZ9pDc6tzvZc0blhT45gLdnkkauVLwo8UREckQZlv51hMxOxKduG8mKc eRtqO/oKYfNw== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223448" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223448" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:08 -0700 IronPort-SDR: zbFH8STS1FMRP2BhXjjCSAI4k+uSU2D0HjdXUEGRv6RmxR1Hu29VhCUp35UEg3kFM0dpGo3eXA 6heWBX15n97g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603183" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:06 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Anatoly Burakov , John McNamara , Marko Kovacevic Date: Wed, 30 Sep 2020 14:03:59 +0100 Message-Id: <20200930130415.11211-4-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 03/18] doc: add detail on using max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds documentation on the usage of the max SIMD bitwidth EAL setting, and how to use it to enable AVX-512 at runtime. Cc: Anatoly Burakov Cc: John McNamara Cc: Marko Kovacevic Signed-off-by: Ciara Power --- v3: - Added enum value for disabling use of max SIMD to doc. - Added entry to HowTo index. --- doc/guides/howto/avx512.rst | 36 +++++++++++++++++++ doc/guides/howto/index.rst | 1 + doc/guides/linux_gsg/eal_args.include.rst | 16 +++++++++ .../prog_guide/env_abstraction_layer.rst | 32 +++++++++++++++++ 4 files changed, 85 insertions(+) create mode 100644 doc/guides/howto/avx512.rst diff --git a/doc/guides/howto/avx512.rst b/doc/guides/howto/avx512.rst new file mode 100644 index 0000000000..ebae0f2b4f --- /dev/null +++ b/doc/guides/howto/avx512.rst @@ -0,0 +1,36 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2020 Intel Corporation. + + +Using AVX-512 with DPDK +======================= + +AVX-512 is not used by default in DPDK, but it can be selected at runtime by apps through the use of EAL API, +and by the user with a commandline argument. DPDK has a setting for max SIMD bitwidth, +which can be modified and will then limit the vector path taken by the code. + + +Using the API in apps +--------------------- + +Apps can request DPDK uses AVX-512 at runtime, if it provides improved application performance. +This can be done by modifying the EAL setting for max SIMD bitwidth to 512, as by default it is 256, +which does not allow for AVX-512. + +.. code-block:: c + + rte_set_max_simd_bitwidth(RTE_MAX_512_SIMD); + +This API should only be called once at initialization, before EAL init. +For more information on the possible enum values to use as a parameter, go to :ref:`max_simd_bitwidth`: + + +Using the command-line argument +--------------------------------------------- + +The user can select to use AVX-512 at runtime, using the following argument to set the max bitwidth:: + + ./app/dpdk-testpmd --force-max-simd-bitwidth=512 + +This will override any further changes to the max SIMD bitwidth in DPDK, +which is useful for testing purposes. diff --git a/doc/guides/howto/index.rst b/doc/guides/howto/index.rst index 5a97ea508c..c2a2c60ddb 100644 --- a/doc/guides/howto/index.rst +++ b/doc/guides/howto/index.rst @@ -20,3 +20,4 @@ HowTo Guides telemetry debug_troubleshoot openwrt + avx512 diff --git a/doc/guides/linux_gsg/eal_args.include.rst b/doc/guides/linux_gsg/eal_args.include.rst index 0fe4457968..a0bfbd1a98 100644 --- a/doc/guides/linux_gsg/eal_args.include.rst +++ b/doc/guides/linux_gsg/eal_args.include.rst @@ -210,3 +210,19 @@ Other options * ``--no-telemetry``: Disable telemetry. + +* ``--force-max-simd-bitwidth=``: + + Specify the maximum SIMD bitwidth size to handle. This limits which vector paths, + if any, are taken, as any paths taken must use a bitwidth below the max bitwidth limit. + For example, to allow all SIMD bitwidths up to and including AVX-512:: + + --force-max-simd-bitwidth=512 + + The following example shows limiting the bitwidth to 64-bits to disable all vector code:: + + --force-max-simd-bitwidth=64 + + To disable use of max SIMD bitwidth limit:: + + --force-max-simd-bitwidth=0 diff --git a/doc/guides/prog_guide/env_abstraction_layer.rst b/doc/guides/prog_guide/env_abstraction_layer.rst index f64ae953d1..58f591e921 100644 --- a/doc/guides/prog_guide/env_abstraction_layer.rst +++ b/doc/guides/prog_guide/env_abstraction_layer.rst @@ -486,6 +486,38 @@ the desired addressing mode when virtual devices that are not directly attached To facilitate forcing the IOVA mode to a specific value the EAL command line option ``--iova-mode`` can be used to select either physical addressing('pa') or virtual addressing('va'). +.. _max_simd_bitwidth: + + +Max SIMD bitwidth +~~~~~~~~~~~~~~~~~ + +The EAL provides a single setting to limit the max SIMD bitwidth used by DPDK, +which is used in determining the vector path, if any, chosen by a component. +The value can be set at runtime by an application using the 'rte_set_max_simd_bitwidth(uint16_t bitwidth)' function, +which should only be called once at initialization, before EAL init. +The value can be overridden by the user using the EAL command-line option '--force-max-simd-bitwidth'. + +When choosing a vector path, along with checking the CPU feature support, +the value of the max SIMD bitwidth must also be checked, and can be retrieved using the 'rte_get_max_simd_bitwidth()' function. +The value should be compared against the enum values for accepted max SIMD bitwidths: + +.. code-block:: c + + enum rte_max_simd_t { + RTE_NO_SIMD = 64, + RTE_MAX_128_SIMD = 128, + RTE_MAX_256_SIMD = 256, + RTE_MAX_512_SIMD = 512, + RTE_MAX_SIMD_DISABLE = UINT16_MAX, + }; + + if (rte_get_max_simd_bitwidth() >= RTE_MAX_512_SIMD) + /* Take AVX-512 vector path */ + else if (rte_get_max_simd_bitwidth() >= RTE_MAX_256_SIMD) + /* Take AVX2 vector path */ + + Memory Segments and Memory Zones (memzone) ------------------------------------------ From patchwork Wed Sep 30 13:04:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79341 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0CA74A04B5; Wed, 30 Sep 2020 15:09:30 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E1BF21DAFF; Wed, 30 Sep 2020 15:08:18 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id D3D581D66B for ; Wed, 30 Sep 2020 15:08:10 +0200 (CEST) IronPort-SDR: QKcjbzj6inz+tNv3qBTWA0yl/EmUbC8uyHGIPk+01ABQGeEf4fJOJ3szQqz0mjFVrHfhawuejs 35BlS/OuZrtQ== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223457" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223457" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:09 -0700 IronPort-SDR: qjqpBsVN4HsNpoNkMnpmRVUC/j07Riqd/zu8dqkYgEgM4k8fSMiF8jVRiimJOnPo7dA5KdMGW4 ZV6qyq0rIPXA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603192" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:08 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Beilei Xing , Jeff Guo Date: Wed, 30 Sep 2020 14:04:00 +0100 Message-Id: <20200930130415.11211-5-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 04/18] net/i40e: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Beilei Xing Cc: Jeff Guo Signed-off-by: Ciara Power Acked-by: Konstantin Ananyev --- drivers/net/i40e/i40e_rxtx.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index 60b33d20a1..9b535b52fa 100644 --- a/drivers/net/i40e/i40e_rxtx.c +++ b/drivers/net/i40e/i40e_rxtx.c @@ -3098,7 +3098,8 @@ static eth_rx_burst_t i40e_get_latest_rx_vec(bool scatter) { #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && + rte_get_max_simd_bitwidth() >= RTE_MAX_256_SIMD) return scatter ? i40e_recv_scattered_pkts_vec_avx2 : i40e_recv_pkts_vec_avx2; #endif @@ -3115,7 +3116,8 @@ i40e_get_recommend_rx_vec(bool scatter) * use of AVX2 version to later plaforms, not all those that could * theoretically run it. */ - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && + rte_get_max_simd_bitwidth() >= RTE_MAX_256_SIMD) return scatter ? i40e_recv_scattered_pkts_vec_avx2 : i40e_recv_pkts_vec_avx2; #endif @@ -3154,7 +3156,8 @@ i40e_set_rx_function(struct rte_eth_dev *dev) } } - if (ad->rx_vec_allowed) { + if (ad->rx_vec_allowed && rte_get_max_simd_bitwidth() + >= RTE_MAX_128_SIMD) { /* Vec Rx path */ PMD_INIT_LOG(DEBUG, "Vector Rx path will be used on port=%d.", dev->data->port_id); @@ -3268,7 +3271,8 @@ static eth_tx_burst_t i40e_get_latest_tx_vec(void) { #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && + rte_get_max_simd_bitwidth() >= RTE_MAX_256_SIMD) return i40e_xmit_pkts_vec_avx2; #endif return i40e_xmit_pkts_vec; @@ -3283,7 +3287,8 @@ i40e_get_recommend_tx_vec(void) * use of AVX2 version to later plaforms, not all those that could * theoretically run it. */ - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && + rte_get_max_simd_bitwidth() >= RTE_MAX_256_SIMD) return i40e_xmit_pkts_vec_avx2; #endif return i40e_xmit_pkts_vec; @@ -3311,7 +3316,9 @@ i40e_set_tx_function(struct rte_eth_dev *dev) } if (ad->tx_simple_allowed) { - if (ad->tx_vec_allowed) { + if (ad->tx_vec_allowed && + rte_get_max_simd_bitwidth() + >= RTE_MAX_128_SIMD) { PMD_INIT_LOG(DEBUG, "Vector tx finally be used."); if (ad->use_latest_vec) dev->tx_pkt_burst = From patchwork Wed Sep 30 13:04:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79342 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id EFBD1A04B5; Wed, 30 Sep 2020 15:09:45 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6AC971DB18; Wed, 30 Sep 2020 15:08:20 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id A6F881D66B for ; Wed, 30 Sep 2020 15:08:11 +0200 (CEST) IronPort-SDR: yij+k3BzMuhzTkgZLQJvxnDwz0Iey6LMtYKl1Gy/1UE0Cy4Fo/vqe/FR89DxzjsC9I04JgAfeY I36Pvtv71z7w== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223465" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223465" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:11 -0700 IronPort-SDR: g+HXJXzthxpuDGzfreavxWDN4l4t7Se0jOORomTp18NpcWGTdOOgtJ7lLjVO+9Bee52zbHfzJz sqJ3/Qx5/TeA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603201" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:10 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Somalapuram Amaranath Date: Wed, 30 Sep 2020 14:04:01 +0100 Message-Id: <20200930130415.11211-6-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 05/18] net/axgbe: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Somalapuram Amaranath Signed-off-by: Ciara Power Signed-off-by: Ciara Power Acked-by: Amaranath Somalapuram --- drivers/net/axgbe/axgbe_rxtx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c index bc93becaa5..6093ec7279 100644 --- a/drivers/net/axgbe/axgbe_rxtx.c +++ b/drivers/net/axgbe/axgbe_rxtx.c @@ -557,7 +557,8 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, if (!pdata->tx_queues) pdata->tx_queues = dev->data->tx_queues; - if (txq->vector_disable) + if (txq->vector_disable || rte_get_max_simd_bitwidth() + < RTE_MAX_128_SIMD) dev->tx_pkt_burst = &axgbe_xmit_pkts; else #ifdef RTE_ARCH_X86 From patchwork Wed Sep 30 13:04:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79343 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 48A86A04B5; Wed, 30 Sep 2020 15:10:13 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B8F381DB3E; Wed, 30 Sep 2020 15:08:24 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 32EDB1DAE5 for ; Wed, 30 Sep 2020 15:08:13 +0200 (CEST) IronPort-SDR: 6mJZ2szPrvO73SlrPtz0VSL3Ook3Rdsnw2fEAsNhUjskKCmGbM6CFJaovHR5RklkBfF3VNNXe2 TzXLevo4Dckw== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223467" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223467" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:12 -0700 IronPort-SDR: nkOZx4ogUHL0YItGBlsagFDGjDuN5bmicHW2Cf2u1YsussBizezNsoMnY5mpnZym3Qun8P+LXA hlEYEKRc2zVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603205" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:11 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Ajit Khaparde , Somnath Kotur Date: Wed, 30 Sep 2020 14:04:02 +0100 Message-Id: <20200930130415.11211-7-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 06/18] net/bnxt: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Ajit Khaparde Cc: Somnath Kotur Signed-off-by: Ciara Power --- drivers/net/bnxt/bnxt_ethdev.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 05e9a6abbf..5cd522f1fd 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1122,7 +1122,8 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev) DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_RSS_HASH | DEV_RX_OFFLOAD_VLAN_FILTER)) && - !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) { + !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) && + rte_get_max_simd_bitwidth() >= RTE_MAX_128_SIMD) { PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", eth_dev->data->port_id); bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; @@ -1154,7 +1155,8 @@ bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev) */ if (!eth_dev->data->scattered_rx && !eth_dev->data->dev_conf.txmode.offloads && - !BNXT_TRUFLOW_EN(bp)) { + !BNXT_TRUFLOW_EN(bp) && + rte_get_max_simd_bitwidth() >= RTE_MAX_128_SIMD) { PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", eth_dev->data->port_id); return bnxt_xmit_pkts_vec; From patchwork Wed Sep 30 13:04:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79344 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 57EF7A04B5; Wed, 30 Sep 2020 15:10:30 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6071E1DB4A; Wed, 30 Sep 2020 15:08:26 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 231841DAE5 for ; Wed, 30 Sep 2020 15:08:16 +0200 (CEST) IronPort-SDR: tMNw917CUUdUhppTME9/tQEqFbW6Bo+YWZ89ijRx5XouUeWf8PBB7EqS6QPk4Dmf60u7TWV+uf coNy6PA+vlaQ== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223470" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223470" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:14 -0700 IronPort-SDR: 8jQBNbplFeHPs1V9zEPI10MHGsPVOVbn8oVmxE7XFSFD95Ef+rLJG1RYexHaib8gwhH7BewBYv AnPwMv/UdpXA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603212" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:13 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , John Daley , Hyong Youb Kim Date: Wed, 30 Sep 2020 14:04:03 +0100 Message-Id: <20200930130415.11211-8-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 07/18] net/enic: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: John Daley Cc: Hyong Youb Kim Acked-by: Hyong Youb Kim Signed-off-by: Ciara Power --- drivers/net/enic/enic_rxtx_vec_avx2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/enic/enic_rxtx_vec_avx2.c b/drivers/net/enic/enic_rxtx_vec_avx2.c index 676b9f5fdb..5db43bdbb8 100644 --- a/drivers/net/enic/enic_rxtx_vec_avx2.c +++ b/drivers/net/enic/enic_rxtx_vec_avx2.c @@ -821,7 +821,8 @@ enic_use_vector_rx_handler(struct rte_eth_dev *eth_dev) fconf = ð_dev->data->dev_conf.fdir_conf; if (fconf->mode != RTE_FDIR_MODE_NONE) return false; - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) { + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && + rte_get_max_simd_bitwidth() >= RTE_MAX_256_SIMD) { ENICPMD_LOG(DEBUG, " use the non-scatter avx2 Rx handler"); eth_dev->rx_pkt_burst = &enic_noscatter_vec_recv_pkts; enic->use_noscatter_vec_rx_handler = 1; From patchwork Wed Sep 30 13:04:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79346 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 70EE0A04B5; Wed, 30 Sep 2020 15:11:12 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 292DE1DB5A; Wed, 30 Sep 2020 15:08:30 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 7828E1DAFA for ; Wed, 30 Sep 2020 15:08:16 +0200 (CEST) IronPort-SDR: DPhZhsM5UHUvK1CqpqXQDHcxLPp+MAgQxtKk209d6SW9Ag4zD4gIavjlhBWetKEcrqD3M4Aqqs dL+g8lThQC7Q== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223473" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223473" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:15 -0700 IronPort-SDR: gW+a7K67X8/iwiONdMPkZUSOWEb5VzqJOaB3zzEkgacAyZlfKEc5FVXxsH90HVhOyGYVivBi3Q K+rcK2KJAIAw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603217" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:14 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Qi Zhang , Xiao Wang Date: Wed, 30 Sep 2020 14:04:04 +0100 Message-Id: <20200930130415.11211-9-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 08/18] net/fm10k: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Qi Zhang Cc: Xiao Wang Signed-off-by: Ciara Power Acked-by: Qi Zhang --- drivers/net/fm10k/fm10k_ethdev.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/net/fm10k/fm10k_ethdev.c b/drivers/net/fm10k/fm10k_ethdev.c index 5771d83b55..a8bc1036a3 100644 --- a/drivers/net/fm10k/fm10k_ethdev.c +++ b/drivers/net/fm10k/fm10k_ethdev.c @@ -2930,7 +2930,9 @@ fm10k_set_tx_function(struct rte_eth_dev *dev) if (rte_eal_process_type() != RTE_PROC_PRIMARY) { /* primary process has set the ftag flag and offloads */ txq = dev->data->tx_queues[0]; - if (fm10k_tx_vec_condition_check(txq)) { + if (fm10k_tx_vec_condition_check(txq) || + rte_get_max_simd_bitwidth() + < RTE_MAX_128_SIMD) { dev->tx_pkt_burst = fm10k_xmit_pkts; dev->tx_pkt_prepare = fm10k_prep_pkts; PMD_INIT_LOG(DEBUG, "Use regular Tx func"); @@ -2949,7 +2951,8 @@ fm10k_set_tx_function(struct rte_eth_dev *dev) txq = dev->data->tx_queues[i]; txq->tx_ftag_en = tx_ftag_en; /* Check if Vector Tx is satisfied */ - if (fm10k_tx_vec_condition_check(txq)) + if (fm10k_tx_vec_condition_check(txq) || + rte_get_max_simd_bitwidth() < RTE_MAX_128_SIMD) use_sse = 0; } @@ -2983,7 +2986,9 @@ fm10k_set_rx_function(struct rte_eth_dev *dev) * conditions to be met. */ if (!fm10k_rx_vec_condition_check(dev) && - dev_info->rx_vec_allowed && !rx_ftag_en) { + dev_info->rx_vec_allowed && !rx_ftag_en && + rte_get_max_simd_bitwidth() + >= RTE_MAX_128_SIMD) { if (dev->data->scattered_rx) dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec; else From patchwork Wed Sep 30 13:04:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79345 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 07D31A04B5; Wed, 30 Sep 2020 15:10:54 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 492CC1DB54; Wed, 30 Sep 2020 15:08:28 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 63EEE1DAF8 for ; Wed, 30 Sep 2020 15:08:17 +0200 (CEST) IronPort-SDR: ABT3E2Ny6ruD+Twg0BAr3SVvslq6xqnhS+nBK+oATyIQa/fTcvE5m0p3oKLBXxXTH3/qfNEsHq u3gSk95PUjFg== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223477" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223477" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:17 -0700 IronPort-SDR: my4Fdnqv1TvcgTu3ig48ABfBBhTY/ub9Xa9QX3UY/zvCLcg05S3UuhrE9Lz5byvzt2LlI8mh+t S1cM46l2ObTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603224" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:15 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Jingjing Wu , Beilei Xing Date: Wed, 30 Sep 2020 14:04:05 +0100 Message-Id: <20200930130415.11211-10-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 09/18] net/iavf: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Jingjing Wu Cc: Beilei Xing Signed-off-by: Ciara Power --- drivers/net/iavf/iavf_rxtx.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c index 05a7dd898a..b798d082a2 100644 --- a/drivers/net/iavf/iavf_rxtx.c +++ b/drivers/net/iavf/iavf_rxtx.c @@ -2105,14 +2105,16 @@ iavf_set_rx_function(struct rte_eth_dev *dev) int i; bool use_avx2 = false; - if (!iavf_rx_vec_dev_check(dev)) { + if (!iavf_rx_vec_dev_check(dev) && + rte_get_max_simd_bitwidth() >= RTE_MAX_128_SIMD) { for (i = 0; i < dev->data->nb_rx_queues; i++) { rxq = dev->data->rx_queues[i]; (void)iavf_rxq_vec_setup(rxq); } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() >= RTE_MAX_256_SIMD) use_avx2 = true; if (dev->data->scattered_rx) { @@ -2178,7 +2180,8 @@ iavf_set_tx_function(struct rte_eth_dev *dev) int i; bool use_avx2 = false; - if (!iavf_tx_vec_dev_check(dev)) { + if (!iavf_tx_vec_dev_check(dev) && + rte_get_max_simd_bitwidth() >= RTE_MAX_128_SIMD) { for (i = 0; i < dev->data->nb_tx_queues; i++) { txq = dev->data->tx_queues[i]; if (!txq) @@ -2186,8 +2189,9 @@ iavf_set_tx_function(struct rte_eth_dev *dev) iavf_txq_vec_setup(txq); } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() >= RTE_MAX_256_SIMD) use_avx2 = true; PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).", From patchwork Wed Sep 30 13:04:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79347 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5AE06A04B5; Wed, 30 Sep 2020 15:11:33 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0CCF51DB66; Wed, 30 Sep 2020 15:08:32 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 4896D1DB0D for ; Wed, 30 Sep 2020 15:08:20 +0200 (CEST) IronPort-SDR: Jx12fLmssUqU+mpmasnd6xMpLSDXDNkxCfbRvcQ8yvt1pTH46clcZuAYJ/r3bz0ot/Lf3Y8lqL F7AAA7KFgw/A== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223481" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223481" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:18 -0700 IronPort-SDR: 77qWGp/EGe00vvTXTB4MGJHnUwwL/rcvGMiA9Wd2KpwnCpI7+febh5ozWjitZwHF8H1jKHcVDY e5Mxyi+A5XOQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603231" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:17 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Qiming Yang , Qi Zhang Date: Wed, 30 Sep 2020 14:04:06 +0100 Message-Id: <20200930130415.11211-11-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 10/18] net/ice: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Qiming Yang Cc: Qi Zhang Signed-off-by: Ciara Power Acked-by: Qi Zhang --- drivers/net/ice/ice_rxtx.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c index fef6ad4544..5a29af743c 100644 --- a/drivers/net/ice/ice_rxtx.c +++ b/drivers/net/ice/ice_rxtx.c @@ -2936,7 +2936,9 @@ ice_set_rx_function(struct rte_eth_dev *dev) bool use_avx2 = false; if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) { + if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed && + rte_get_max_simd_bitwidth() + >= RTE_MAX_128_SIMD) { ad->rx_vec_allowed = true; for (i = 0; i < dev->data->nb_rx_queues; i++) { rxq = dev->data->rx_queues[i]; @@ -2946,8 +2948,10 @@ ice_set_rx_function(struct rte_eth_dev *dev) } } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() + >= RTE_MAX_256_SIMD) use_avx2 = true; } else { @@ -3114,7 +3118,9 @@ ice_set_tx_function(struct rte_eth_dev *dev) bool use_avx2 = false; if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - if (!ice_tx_vec_dev_check(dev)) { + if (!ice_tx_vec_dev_check(dev) && + rte_get_max_simd_bitwidth() + >= RTE_MAX_128_SIMD) { ad->tx_vec_allowed = true; for (i = 0; i < dev->data->nb_tx_queues; i++) { txq = dev->data->tx_queues[i]; @@ -3124,8 +3130,10 @@ ice_set_tx_function(struct rte_eth_dev *dev) } } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() + >= RTE_MAX_256_SIMD) use_avx2 = true; } else { From patchwork Wed Sep 30 13:04:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79348 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 64F98A04B5; Wed, 30 Sep 2020 15:11:48 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D21651DB71; Wed, 30 Sep 2020 15:08:33 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id D7E851DB2B for ; Wed, 30 Sep 2020 15:08:20 +0200 (CEST) IronPort-SDR: eKPv//LyTdqjumNka2cW+Py4HrDtnBLCUve8QvxNA/N2aVO3T9SYYKqpwcoclrQQWuzCNlCgML FmeYT8Fn7QxA== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223485" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223485" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:19 -0700 IronPort-SDR: Zl3qk6+2MfscKreBI+8qorgvDf9xz2lXnqgk67fVVVj5vldNmRzCoDJz8mRKNJxg3d4dJ3Y724 H9+vMQ77rZpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603239" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:18 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Wei Zhao , Jeff Guo , Haiyue Wang Date: Wed, 30 Sep 2020 14:04:07 +0100 Message-Id: <20200930130415.11211-12-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Wei Zhao Cc: Jeff Guo Signed-off-by: Ciara Power Acked-by: Konstantin Ananyev --- drivers/net/ixgbe/ixgbe_rxtx.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index 977ecf5137..eadc7183f2 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -2503,7 +2503,9 @@ ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq) dev->tx_pkt_prepare = NULL; if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ && (rte_eal_process_type() != RTE_PROC_PRIMARY || - ixgbe_txq_vec_setup(txq) == 0)) { + ixgbe_txq_vec_setup(txq) == 0) && + rte_get_max_simd_bitwidth() + >= RTE_MAX_128_SIMD) { PMD_INIT_LOG(DEBUG, "Vector tx enabled."); dev->tx_pkt_burst = ixgbe_xmit_pkts_vec; } else @@ -4743,7 +4745,8 @@ ixgbe_set_rx_function(struct rte_eth_dev *dev) * conditions to be met and Rx Bulk Allocation should be allowed. */ if (ixgbe_rx_vec_dev_conf_condition_check(dev) || - !adapter->rx_bulk_alloc_allowed) { + !adapter->rx_bulk_alloc_allowed || + rte_get_max_simd_bitwidth() < RTE_MAX_128_SIMD) { PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx " "preconditions", dev->data->port_id); From patchwork Wed Sep 30 13:04:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79349 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9FF4CA04B5; Wed, 30 Sep 2020 15:12:13 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 908441DB79; Wed, 30 Sep 2020 15:08:35 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 21D551DB37 for ; Wed, 30 Sep 2020 15:08:21 +0200 (CEST) IronPort-SDR: c0dtWZ3u6lYw2mghC7EEAGlV06byG/PVpVE9D/S5SZ6ds62KOiWbbQOmcd/YNSYyc6wo4toglM +BlwTcV8Ec1g== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223487" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223487" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:21 -0700 IronPort-SDR: faZjvkByuiWVUXkOVMjXLchoOZ+EE+1zWHmNZKPZYAtZx0E8ferz4cN76PctMgHZKZdXk9JjYv 0xkx225OhaJA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603249" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:20 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Matan Azrad , Shahaf Shuler , Viacheslav Ovsiienko Date: Wed, 30 Sep 2020 14:04:08 +0100 Message-Id: <20200930130415.11211-13-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 12/18] net/mlx5: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Matan Azrad Cc: Shahaf Shuler Cc: Viacheslav Ovsiienko Signed-off-by: Ciara Power Acked-by: Viacheslav Ovsiienko --- v2: Moved check for max bitwidth into existing check vec support function. --- drivers/net/mlx5/mlx5_rxtx_vec.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c index 711dcd35fa..c384c737dc 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec.c +++ b/drivers/net/mlx5/mlx5_rxtx_vec.c @@ -148,6 +148,8 @@ mlx5_check_vec_rx_support(struct rte_eth_dev *dev) struct mlx5_priv *priv = dev->data->dev_private; uint32_t i; + if (rte_get_max_simd_bitwidth() < RTE_MAX_128_SIMD) + return -ENOTSUP; if (!priv->config.rx_vec_en) return -ENOTSUP; if (mlx5_mprq_enabled(dev)) From patchwork Wed Sep 30 13:04:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79350 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0A1B3A04B5; Wed, 30 Sep 2020 15:12:37 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9C0A01DB83; Wed, 30 Sep 2020 15:08:40 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 0AE831DB44 for ; Wed, 30 Sep 2020 15:08:24 +0200 (CEST) IronPort-SDR: kQa7KCYebNYTwsViF9Oz6XIO15xGL/9lvo6HDU+IN1JSvP4hLN6/O58kSirBcrcCvtlbHBqt2N QpIJDB5EMCtQ== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223489" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223489" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:23 -0700 IronPort-SDR: oibkUHzkZC9DqYke/Qa1mm/zKiFHhUSdJ9bdtIVkjFypAGFAT5aJ3pMxviCFoOW82ScujHfvrX jK3bfcPVZAnA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603259" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:21 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Maxime Coquelin , Chenbo Xia , Zhihong Wang Date: Wed, 30 Sep 2020 14:04:09 +0100 Message-Id: <20200930130415.11211-14-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 13/18] net/virtio: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Maxime Coquelin Cc: Chenbo Xia Cc: Zhihong Wang Signed-off-by: Ciara Power --- v3: Moved max SIMD bitwidth check to configure function with other vec support checks. --- drivers/net/virtio/virtio_ethdev.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/net/virtio/virtio_ethdev.c b/drivers/net/virtio/virtio_ethdev.c index 013a2904e6..f749e81405 100644 --- a/drivers/net/virtio/virtio_ethdev.c +++ b/drivers/net/virtio/virtio_ethdev.c @@ -2306,7 +2306,8 @@ virtio_dev_configure(struct rte_eth_dev *dev) if ((hw->use_vec_rx || hw->use_vec_tx) && (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) || !vtpci_with_feature(hw, VIRTIO_F_IN_ORDER) || - !vtpci_with_feature(hw, VIRTIO_F_VERSION_1))) { + !vtpci_with_feature(hw, VIRTIO_F_VERSION_1) || + rte_get_max_simd_bitwidth() < RTE_MAX_512_SIMD)) { PMD_DRV_LOG(INFO, "disabled packed ring vectorized path for requirements not met"); hw->use_vec_rx = 0; @@ -2359,6 +2360,12 @@ virtio_dev_configure(struct rte_eth_dev *dev) "disabled split ring vectorized rx for offloading enabled"); hw->use_vec_rx = 0; } + + if (rte_get_max_simd_bitwidth() < RTE_MAX_128_SIMD) { + PMD_DRV_LOG(INFO, + "disabled split ring vectorized rx, max SIMD bitwidth too low"); + hw->use_vec_rx = 0; + } } } From patchwork Wed Sep 30 13:04:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79351 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 436E2A04B5; Wed, 30 Sep 2020 15:12:58 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F1FD81DB8A; Wed, 30 Sep 2020 15:08:41 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 59A531DB46 for ; Wed, 30 Sep 2020 15:08:25 +0200 (CEST) IronPort-SDR: sxR4k9TgJ1WqLmmlEq6EhtGu7lcd3JkyDRkKkDqQTxydlmKEDL5VoiPNODfAcN7WosUixEEMhl ZyhwnHDw1ppw== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223491" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223491" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:24 -0700 IronPort-SDR: fA5LH/deRl6RngHd71+7O5SvKDp3ARzbQ0SKiGUB7QQbjGk0GaLi1M2MNWAzi46R/DW5jaSm9R GHGtxms9ZJwg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603263" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:23 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , David Hunt Date: Wed, 30 Sep 2020 14:04:10 +0100 Message-Id: <20200930130415.11211-15-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 14/18] distributor: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: David Hunt Signed-off-by: Ciara Power Acked-by: David Hunt --- lib/librte_distributor/rte_distributor.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/librte_distributor/rte_distributor.c b/lib/librte_distributor/rte_distributor.c index 1c047f065a..9f0a9b1d48 100644 --- a/lib/librte_distributor/rte_distributor.c +++ b/lib/librte_distributor/rte_distributor.c @@ -636,7 +636,8 @@ rte_distributor_create(const char *name, d->dist_match_fn = RTE_DIST_MATCH_SCALAR; #if defined(RTE_ARCH_X86) - d->dist_match_fn = RTE_DIST_MATCH_VECTOR; + if (rte_get_max_simd_bitwidth() >= RTE_MAX_128_SIMD) + d->dist_match_fn = RTE_DIST_MATCH_VECTOR; #endif /* From patchwork Wed Sep 30 13:04:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79352 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8C245A04B5; Wed, 30 Sep 2020 15:13:19 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 79A801DB91; Wed, 30 Sep 2020 15:08:43 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 6D76C1DB5A for ; Wed, 30 Sep 2020 15:08:27 +0200 (CEST) IronPort-SDR: uaXUrAra+4yR7IEoYf2FA2Typ5KvhhC0rq6ighfMdo+NrhampghoWJvt3EhIEh4SnhxvcedETM DyGReW23TOxw== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223496" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223496" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:26 -0700 IronPort-SDR: pV5ZUDvGaHX51RcUMH6Y8IKTRzHdtfERbAishvFVTpAWySMYVNiQnEBScB7hO95flVKDqghAEB zjaWZWb/xocw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603268" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:24 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Yipeng Wang , Sameh Gobriel Date: Wed, 30 Sep 2020 14:04:11 +0100 Message-Id: <20200930130415.11211-16-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 15/18] member: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Yipeng Wang Cc: Sameh Gobriel Signed-off-by: Ciara Power Acked-by: Yipeng Wang --- lib/librte_member/rte_member_ht.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/librte_member/rte_member_ht.c b/lib/librte_member/rte_member_ht.c index cbcd0d4407..71e3cf7b52 100644 --- a/lib/librte_member/rte_member_ht.c +++ b/lib/librte_member/rte_member_ht.c @@ -113,7 +113,8 @@ rte_member_create_ht(struct rte_member_setsum *ss, } #if defined(RTE_ARCH_X86) if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && - RTE_MEMBER_BUCKET_ENTRIES == 16) + RTE_MEMBER_BUCKET_ENTRIES == 16 && + rte_get_max_simd_bitwidth() >= RTE_MAX_256_SIMD) ss->sig_cmp_fn = RTE_MEMBER_COMPARE_AVX2; else #endif From patchwork Wed Sep 30 13:04:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79353 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 97874A04B5; Wed, 30 Sep 2020 15:13:35 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 127A71DB99; Wed, 30 Sep 2020 15:08:45 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id CB8F11DB4D for ; Wed, 30 Sep 2020 15:08:27 +0200 (CEST) IronPort-SDR: Sgo9svMbRh3+WSfxrJN50eDB8v6K9B38NCGG//MPwEgr7POy0Sb95ZemHKjVU9vslQwXOsolJa JyvCOIY/B5uQ== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223500" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223500" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:27 -0700 IronPort-SDR: xNlV69C8+nKPbi/glCPlqt5PyPZ8ub6ot3eVOzFQWyWEmKdare9P+U5u5UBc7fZxTx23DaSZCQ HILoBfgDfQJg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603273" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:26 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Byron Marohn , Yipeng Wang Date: Wed, 30 Sep 2020 14:04:12 +0100 Message-Id: <20200930130415.11211-17-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 16/18] efd: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Byron Marohn Cc: Yipeng Wang Signed-off-by: Ciara Power Acked-by: Yipeng Wang --- lib/librte_efd/rte_efd.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/lib/librte_efd/rte_efd.c b/lib/librte_efd/rte_efd.c index 6a799556d4..509ecc8256 100644 --- a/lib/librte_efd/rte_efd.c +++ b/lib/librte_efd/rte_efd.c @@ -645,7 +645,9 @@ rte_efd_create(const char *name, uint32_t max_num_rules, uint32_t key_len, * For less than 4 bits, scalar function performs better * than vectorised version */ - if (RTE_EFD_VALUE_NUM_BITS > 3 && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (RTE_EFD_VALUE_NUM_BITS > 3 + && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) + && rte_get_max_simd_bitwidth() >= RTE_MAX_256_SIMD) table->lookup_fn = EFD_LOOKUP_AVX2; else #endif @@ -655,7 +657,8 @@ rte_efd_create(const char *name, uint32_t max_num_rules, uint32_t key_len, * than vectorised version */ if (RTE_EFD_VALUE_NUM_BITS > 16 && - rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON)) + rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON) && + rte_get_max_simd_bitwidth() >= RTE_MAX_128_SIMD) table->lookup_fn = EFD_LOOKUP_NEON; else #endif From patchwork Wed Sep 30 13:04:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79354 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5EB48A04B5; Wed, 30 Sep 2020 15:13:57 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B32841DBA0; Wed, 30 Sep 2020 15:08:46 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id DA35C1DB61 for ; Wed, 30 Sep 2020 15:08:30 +0200 (CEST) IronPort-SDR: 50UPfOZPYLWnL5dyXt1qUB1CfTRiHx0jMSbajXuPBWNStzVLlKEh+kQtw3eCpyP8t5QiFsq3uw H4uZhTtJMvsg== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223510" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223510" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:29 -0700 IronPort-SDR: tINi71Xq7teoX9BflM9n5VZTHSGVUbiSKUgi1gPqXC3NaqXZ50LFZI+SgMcFEgY9HwA+eShBQh hKya+17l160w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603281" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:27 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Jasvinder Singh , Olivier Matz Date: Wed, 30 Sep 2020 14:04:13 +0100 Message-Id: <20200930130415.11211-18-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 17/18] net: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. The vector path was initially chosen in RTE_INIT, however this is no longer suitable as we cannot check the max SIMD bitwidth at that time. The default chosen in RTE_INIT is now scalar. For best performance and to use vector paths, apps must explicitly call the set algorithm function before using other functions from this library, as this is where vector handlers are now chosen. Suggested-by: Jasvinder Singh Signed-off-by: Ciara Power --- v3: - Moved choosing vector paths out of RTE_INIT. - Moved checking max_simd_bitwidth into the set_alg function. --- lib/librte_net/rte_net_crc.c | 26 +++++++++++++++++--------- lib/librte_net/rte_net_crc.h | 3 ++- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c index 9fd4794a9d..241eb16399 100644 --- a/lib/librte_net/rte_net_crc.c +++ b/lib/librte_net/rte_net_crc.c @@ -9,6 +9,7 @@ #include #include #include +#include #if defined(RTE_ARCH_X86_64) && defined(RTE_MACHINE_CPUFLAG_PCLMULQDQ) #define X86_64_SSE42_PCLMULQDQ 1 @@ -60,6 +61,9 @@ static rte_net_crc_handler handlers_neon[] = { }; #endif +static uint16_t max_simd_bitwidth; +#define RTE_LOGTYPE_NET RTE_LOGTYPE_USER1 + /** * Reflect the bits about the middle * @@ -145,18 +149,26 @@ rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len) void rte_net_crc_set_alg(enum rte_net_crc_alg alg) { + if (max_simd_bitwidth == 0) + max_simd_bitwidth = rte_get_max_simd_bitwidth(); + switch (alg) { #ifdef X86_64_SSE42_PCLMULQDQ case RTE_NET_CRC_SSE42: - handlers = handlers_sse42; - break; + if (max_simd_bitwidth >= RTE_MAX_128_SIMD) { + handlers = handlers_sse42; + return; + } + RTE_LOG(INFO, NET, "Max SIMD Bitwidth too low, using scalar\n"); #elif defined ARM64_NEON_PMULL /* fall-through */ case RTE_NET_CRC_NEON: - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) { + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL) && + max_simd_bitwidth >= RTE_MAX_128_SIMD) { handlers = handlers_neon; - break; + return; } + RTE_LOG(INFO, NET, "Max SIMD Bitwidth too low or CPU flag not enabled, using scalar\n"); #endif /* fall-through */ case RTE_NET_CRC_SCALAR: @@ -184,19 +196,15 @@ rte_net_crc_calc(const void *data, /* Select highest available crc algorithm as default one */ RTE_INIT(rte_net_crc_init) { - enum rte_net_crc_alg alg = RTE_NET_CRC_SCALAR; - rte_net_crc_scalar_init(); #ifdef X86_64_SSE42_PCLMULQDQ - alg = RTE_NET_CRC_SSE42; rte_net_crc_sse42_init(); #elif defined ARM64_NEON_PMULL if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) { - alg = RTE_NET_CRC_NEON; rte_net_crc_neon_init(); } #endif - rte_net_crc_set_alg(alg); + rte_net_crc_set_alg(RTE_NET_CRC_SCALAR); } diff --git a/lib/librte_net/rte_net_crc.h b/lib/librte_net/rte_net_crc.h index 16e85ca970..7a45ebe193 100644 --- a/lib/librte_net/rte_net_crc.h +++ b/lib/librte_net/rte_net_crc.h @@ -28,7 +28,8 @@ enum rte_net_crc_alg { /** * This API set the CRC computation algorithm (i.e. scalar version, * x86 64-bit sse4.2 intrinsic version, etc.) and internal data - * structure. + * structure. This should be called before any other functions, to + * choose the algorithm for best performance. * * @param alg * This parameter is used to select the CRC implementation version. From patchwork Wed Sep 30 13:04:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 79355 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B8BB8A04B5; Wed, 30 Sep 2020 15:14:19 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 321F21DBA3; Wed, 30 Sep 2020 15:08:48 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 700251DB69 for ; Wed, 30 Sep 2020 15:08:31 +0200 (CEST) IronPort-SDR: FV+b+4P7kMAuRCOiVVKgUFcw1+WSZogbbXOeRQJmkh0af7lDTioAra7QBjh4mVDQnRH++BK7we CxocF9TM+Mjg== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223515" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223515" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:30 -0700 IronPort-SDR: GUzG9J+IIRnW/o3gdcIxhUIFJBYvgysAv/oJSiBiQaTNYyC/tO4ejejVoxTaAmdsVCfx2K2hED AxDIjaY6zCCw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603292" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:29 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Bruce Richardson , Vladimir Medvedkin , Jerin Jacob , Ruifeng Wang Date: Wed, 30 Sep 2020 14:04:14 +0100 Message-Id: <20200930130415.11211-19-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 18/18] lpm: choose vector path at runtime X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing the vector path, max SIMD bitwidth is now checked to ensure a vector path is allowable. To do this, rather than the vector lookup functions being called directly from apps, a generic lookup function is called which will call the vector functions if suitable. Signed-off-by: Ciara Power --- lib/librte_lpm/rte_lpm.h | 57 ++++++++++++++++++++++++++------ lib/librte_lpm/rte_lpm_altivec.h | 2 +- lib/librte_lpm/rte_lpm_neon.h | 2 +- lib/librte_lpm/rte_lpm_sse.h | 2 +- 4 files changed, 50 insertions(+), 13 deletions(-) diff --git a/lib/librte_lpm/rte_lpm.h b/lib/librte_lpm/rte_lpm.h index 03da2d37e0..edba7cafd5 100644 --- a/lib/librte_lpm/rte_lpm.h +++ b/lib/librte_lpm/rte_lpm.h @@ -397,8 +397,18 @@ rte_lpm_lookup_bulk_func(const struct rte_lpm *lpm, const uint32_t *ips, /* Mask four results. */ #define RTE_LPM_MASKX4_RES UINT64_C(0x00ffffff00ffffff) +#if defined(RTE_ARCH_ARM) || defined(RTE_ARCH_ARM64) +#include "rte_lpm_neon.h" +#elif defined(RTE_ARCH_PPC_64) +#include "rte_lpm_altivec.h" +#else +#include "rte_lpm_sse.h" +#endif + /** - * Lookup four IP addresses in an LPM table. + * Lookup four IP addresses in an LPM table individually by calling the + * lookup function for each ip. This is used when lookupx4 is called but + * the vector path is not suitable. * * @param lpm * LPM object handle @@ -417,16 +427,43 @@ rte_lpm_lookup_bulk_func(const struct rte_lpm *lpm, const uint32_t *ips, * if lookup would fail. */ static inline void -rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], - uint32_t defv); +rte_lpm_lookupx4_scalar(struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], + uint32_t defv) +{ + int i; + for (i = 0; i < 4; i++) + if (rte_lpm_lookup(lpm, ((uint32_t *) &ip)[i], &hop[i]) < 0) + hop[i] = defv; /* lookupx4 expected to set on failure */ +} -#if defined(RTE_ARCH_ARM) || defined(RTE_ARCH_ARM64) -#include "rte_lpm_neon.h" -#elif defined(RTE_ARCH_PPC_64) -#include "rte_lpm_altivec.h" -#else -#include "rte_lpm_sse.h" -#endif +/** + * Lookup four IP addresses in an LPM table. + * + * @param lpm + * LPM object handle + * @param ip + * Four IPs to be looked up in the LPM table + * @param hop + * Next hop of the most specific rule found for IP (valid on lookup hit only). + * This is an 4 elements array of two byte values. + * If the lookup was successful for the given IP, then least significant byte + * of the corresponding element is the actual next hop and the most + * significant byte is zero. + * If the lookup for the given IP failed, then corresponding element would + * contain default value, see description of then next parameter. + * @param defv + * Default value to populate into corresponding element of hop[] array, + * if lookup would fail. + */ +static inline void +rte_lpm_lookupx4(struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], + uint32_t defv) +{ + if (rte_get_max_simd_bitwidth() >= RTE_MAX_128_SIMD) + rte_lpm_lookupx4_vec(lpm, ip, hop, defv); + else + rte_lpm_lookupx4_scalar(lpm, ip, hop, defv); +} #ifdef __cplusplus } diff --git a/lib/librte_lpm/rte_lpm_altivec.h b/lib/librte_lpm/rte_lpm_altivec.h index 228c41b38e..82142d3351 100644 --- a/lib/librte_lpm/rte_lpm_altivec.h +++ b/lib/librte_lpm/rte_lpm_altivec.h @@ -16,7 +16,7 @@ extern "C" { #endif static inline void -rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], +rte_lpm_lookupx4_vec(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv) { vector signed int i24; diff --git a/lib/librte_lpm/rte_lpm_neon.h b/lib/librte_lpm/rte_lpm_neon.h index 6c131d3125..14b184515d 100644 --- a/lib/librte_lpm/rte_lpm_neon.h +++ b/lib/librte_lpm/rte_lpm_neon.h @@ -16,7 +16,7 @@ extern "C" { #endif static inline void -rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], +rte_lpm_lookupx4_vec(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv) { uint32x4_t i24; diff --git a/lib/librte_lpm/rte_lpm_sse.h b/lib/librte_lpm/rte_lpm_sse.h index 44770b6ff8..cb5477c6cf 100644 --- a/lib/librte_lpm/rte_lpm_sse.h +++ b/lib/librte_lpm/rte_lpm_sse.h @@ -15,7 +15,7 @@ extern "C" { #endif static inline void -rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], +rte_lpm_lookupx4_vec(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv) { __m128i i24;