From patchwork Tue Dec 15 06:04:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85158 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2360FA09E9; Tue, 15 Dec 2020 07:01:56 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E19DEC982; Tue, 15 Dec 2020 07:01:32 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 01C3CA3 for ; Tue, 15 Dec 2020 07:01:29 +0100 (CET) IronPort-SDR: 5TGN8OL1QATUCTODRWUbpe3JL9TSbuNCe9bG7rNPw786wUOTj+YfdvZkwwLuuF14dhoMlDqgGW INqloVXypMew== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200211" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200211" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:27 -0800 IronPort-SDR: xl99VCT7RO0XXjXNkVAHJg0dY4fmQ9P29vuW7YQC6NZyKgYB5shmsSHLvHubIRknhR/puT4OyP 8mdAQ6cEfw8Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723290" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:26 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang Date: Tue, 15 Dec 2020 14:04:53 +0800 Message-Id: <20201215060519.302145-2-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 01/27] net/ice/base: modify ptype map for UDP X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add below ptypes into ice_ptypes_udp_il. MAC_IPV4_GTPC_TEID MAC_IPV6_GTPC_TEID MAC_IPV4_GTPC MAC_IPV6_GTPC MAC_IPV4_GTPU MAC_IPV6_GTPU So outer UDP can also be selected as input set for GTPC and GTPU non IP packet. Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flow.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 1b36c2b897..f667b8ef7d 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -364,7 +364,7 @@ static const u32 ice_ptypes_arp_of[] = { static const u32 ice_ptypes_udp_il[] = { 0x81000000, 0x20204040, 0x04000010, 0x80810102, 0x00000040, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00410000, 0x90842000, 0x00000007, + 0x00000000, 0x00410000, 0x908427E0, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, From patchwork Tue Dec 15 06:04:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85159 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 167C0A09E9; Tue, 15 Dec 2020 07:02:13 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 66FDAC99E; Tue, 15 Dec 2020 07:01:34 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 618F8DE0 for ; Tue, 15 Dec 2020 07:01:30 +0100 (CET) IronPort-SDR: SKCogV7bS4QexsEaGw8lxhzo+BANrb8CqNW2YTNxGEQoR0ls0NNwnlGmtxYaLYatiWOPJ6WCWM lirQOHFJh6Kw== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200213" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200213" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:28 -0800 IronPort-SDR: Ebiw0sBLnL6ekYtAytm0y/iEvfCv5F2GzY9yc72iNLQaVubHUbFE68xc9speRnuzJidb0kJF1s +F8hViLwxsSw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723305" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:27 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Fabio Pricoco Date: Tue, 15 Dec 2020 14:04:54 +0800 Message-Id: <20201215060519.302145-3-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 02/27] net/ice/base: increased control queue timeout X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 250 msec timeout is insufficient for some AQ commands. Advice from FW team was to increase the timeout. Increased to 1 second. Signed-off-by: Fabio Pricoco Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_controlq.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h index e5e0001788..84c114f7a4 100644 --- a/drivers/net/ice/base/ice_controlq.h +++ b/drivers/net/ice/base/ice_controlq.h @@ -32,8 +32,8 @@ enum ice_ctl_q { ICE_CTL_Q_MAILBOX, }; -/* Control Queue timeout settings - max delay 250ms */ -#define ICE_CTL_Q_SQ_CMD_TIMEOUT 2500 /* Count 2500 times */ +/* Control Queue timeout settings - max delay 1s */ +#define ICE_CTL_Q_SQ_CMD_TIMEOUT 10000 /* Count 10000 times */ #define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */ #define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */ #define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */ From patchwork Tue Dec 15 06:04:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85160 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5B3EDA09E9; Tue, 15 Dec 2020 07:02:37 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 04EA6C9AC; Tue, 15 Dec 2020 07:01:36 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 997F51E35 for ; Tue, 15 Dec 2020 07:01:30 +0100 (CET) IronPort-SDR: 00dOb0sjbOFUWj3Ro2C142N+Y7dKnACXHN+bBCLhfIVNcPp+Fp4r2b7v7mNs06s3+QqEx7FNOw f2SJpOWiDvwQ== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200214" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200214" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:29 -0800 IronPort-SDR: DP61DGzsJYw5Bidg81V2vL+jacYhEm45ms5hPDkfMzCmABjG4p+e9VkLrEU9GsVvXGkoa3+o3T JBZIJ+SRjZdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723322" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:28 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Fabio Pricoco Date: Tue, 15 Dec 2020 14:04:55 +0800 Message-Id: <20201215060519.302145-4-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 03/27] net/ice/base: read more security revision options X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Added read of security revision disabled and updated disabled. Signed-off-by: Fabio Pricoco Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_common.c | 17 +++++++++++++++++ drivers/net/ice/base/ice_type.h | 4 ++++ 2 files changed, 21 insertions(+) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 304e55e210..b217ae6d41 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -1882,6 +1882,23 @@ ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, caps->msix_vector_first_id); break; + case ICE_AQC_CAPS_NVM_MGMT: + caps->sec_rev_disabled = + (number & ICE_NVM_MGMT_SEC_REV_DISABLED) ? + true : false; + ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix, + caps->sec_rev_disabled); + caps->update_disabled = + (number & ICE_NVM_MGMT_UPDATE_DISABLED) ? + true : false; + ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix, + caps->update_disabled); + caps->nvm_unified_update = + (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? + true : false; + ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, + caps->nvm_unified_update); + break; case ICE_AQC_CAPS_MAX_MTU: caps->max_mtu = number; ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 6b8d44f0b4..3b54ce92e1 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -419,7 +419,11 @@ struct ice_hw_common_caps { u8 apm_wol_support; u8 acpi_prog_mthd; u8 proxy_support; + bool sec_rev_disabled; + bool update_disabled; bool nvm_unified_update; +#define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0) +#define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1) #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) }; From patchwork Tue Dec 15 06:04:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85161 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 164CEA09E9; Tue, 15 Dec 2020 07:02:57 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AD980C9B8; Tue, 15 Dec 2020 07:01:37 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 190F0C96A for ; Tue, 15 Dec 2020 07:01:31 +0100 (CET) IronPort-SDR: ZOg7xc45+KETQKY4sMJwF028BVWI/a0xFiqlykr+QODWOPyj9Nf1ctSS/o6yVGiyHtYiUYG9Yi F0aKE5vz5GWw== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200218" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200218" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:31 -0800 IronPort-SDR: k96gNZOomtoy1iIyxTsxgux++gHBp+iWUtQB+Xor8l6Ij177hfvnLEGDyFJC7k0W5MY8h4fPvL qAwLzWKSY5IA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723346" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:30 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Jacob Keller Date: Tue, 15 Dec 2020 14:04:56 +0800 Message-Id: <20201215060519.302145-5-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 04/27] net/ice/base: refactor interface for flash read X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The ice_read_flash_module interface for reading from the various NVM modules was introduced. It's purpose is two-fold. First, it enables reading data from the CSS header, used to allow accessing the image security revisions. Second, it allowed reading from either the 1st or the 2nd NVM bank. This interface was necessary because the device has two copies of each module. Only one bank is active at a time, but it could be different for each module. The driver had to determine which bank was active and then use that to calculate the offset into the flash to read. Future plans include allowing access to read not just from the active flash bank, but also the inactive bank. This will be useful for enabling display of the version information for a pending flash update. The current abstraction in ice_read_flash_module is to specify the exact bank to read. This requires callers to know whether to read from the 1st or 2nd flash bank. This is the wrong abstraction level, since in most cases the decision point from a caller's perspective is whether to read from the active bank or the inactive bank. Add a new ice_bank_select enumeration, used to indicate whether a flow wants to read from the active, or inactive flash bank. Refactor ice_read_flash_module to take this new enumeration instead of a raw flash bank. Have ice_read_flash_module select which bank to read from based on the cached data we load during NVM initialization. With this change, it will be come easier to implement reading version data from the inactive flash banks in a future change. Signed-off-by: Jacob Keller Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_nvm.c | 116 ++++++++++++++++++++++---------- drivers/net/ice/base/ice_type.h | 9 +++ 2 files changed, 91 insertions(+), 34 deletions(-) diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index 7b76af7b6f..facfaf1a41 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -212,6 +212,74 @@ void ice_release_nvm(struct ice_hw *hw) ice_release_res(hw, ICE_NVM_RES_ID); } +/** + * ice_get_flash_bank_offset - Get offset into requested flash bank + * @hw: pointer to the HW structure + * @bank: whether to read from the active or inactive flash bank + * @module: the module to read from + * + * Based on the module, lookup the module offset from the beginning of the + * flash. + * + * Returns the flash offset. Note that a value of zero is invalid and must be + * treated as an error. + */ +static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module) +{ + struct ice_bank_info *banks = &hw->flash.banks; + enum ice_flash_bank active_bank; + bool second_bank_active; + u32 offset, size; + + switch (module) { + case ICE_SR_1ST_NVM_BANK_PTR: + offset = banks->nvm_ptr; + size = banks->nvm_size; + active_bank = banks->nvm_bank; + break; + case ICE_SR_1ST_OROM_BANK_PTR: + offset = banks->orom_ptr; + size = banks->orom_size; + active_bank = banks->orom_bank; + break; + case ICE_SR_NETLIST_BANK_PTR: + offset = banks->netlist_ptr; + size = banks->netlist_size; + active_bank = banks->netlist_bank; + break; + default: + ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash module: 0x%04x\n", module); + return 0; + } + + switch (active_bank) { + case ICE_1ST_FLASH_BANK: + second_bank_active = false; + break; + case ICE_2ND_FLASH_BANK: + second_bank_active = true; + break; + default: + ice_debug(hw, ICE_DBG_NVM, "Unexpected value for active flash bank: %u\n", + active_bank); + return 0; + } + + /* The second flash bank is stored immediately following the first + * bank. Based on whether the 1st or 2nd bank is active, and whether + * we want the active or inactive bank, calculate the desired offset. + */ + switch (bank) { + case ICE_ACTIVE_FLASH_BANK: + return offset + (second_bank_active ? size : 0); + case ICE_INACTIVE_FLASH_BANK: + return offset + (second_bank_active ? 0 : size); + } + + ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash bank selection: %u\n", bank); + return 0; +} + /** * ice_read_flash_module - Read a word from one of the main NVM modules * @hw: pointer to the HW structure @@ -220,49 +288,29 @@ void ice_release_nvm(struct ice_hw *hw) * @offset: the offset into the module in words * @data: storage for the word read from the flash * - * Read a word from the specified bank of the module. The bank must be either - * the 1st or 2nd bank. The word will be read using flat NVM access, and - * relies on the hw->flash.banks data being setup by - * ice_determine_active_flash_banks() during initialization. + * Read data from the specified flash module. The bank parameter indicates + * whether or not to read from the active bank or the inactive bank of that + * module. + * + * The word will be read using flat NVM access, and relies on the + * hw->flash.banks data being setup by ice_determine_active_flash_banks() + * during initialization. */ static enum ice_status -ice_read_flash_module(struct ice_hw *hw, enum ice_flash_bank bank, u16 module, +ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module, u32 offset, u16 *data) { - struct ice_bank_info *banks = &hw->flash.banks; u32 bytes = sizeof(u16); enum ice_status status; __le16 data_local; - bool second_bank; u32 start; ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); - switch (bank) { - case ICE_1ST_FLASH_BANK: - second_bank = false; - break; - case ICE_2ND_FLASH_BANK: - second_bank = true; - break; - case ICE_INVALID_FLASH_BANK: - default: - ice_debug(hw, ICE_DBG_NVM, "Unexpected flash bank %u\n", bank); - return ICE_ERR_PARAM; - } - - switch (module) { - case ICE_SR_1ST_NVM_BANK_PTR: - start = banks->nvm_ptr + (second_bank ? banks->nvm_size : 0); - break; - case ICE_SR_1ST_OROM_BANK_PTR: - start = banks->orom_ptr + (second_bank ? banks->orom_size : 0); - break; - case ICE_SR_NETLIST_BANK_PTR: - start = banks->netlist_ptr + (second_bank ? banks->netlist_size : 0); - break; - default: - ice_debug(hw, ICE_DBG_NVM, "Unexpected flash module 0x%04x\n", module); + start = ice_get_flash_bank_offset(hw, bank, module); + if (!start) { + ice_debug(hw, ICE_DBG_NVM, "Unable to calculate flash bank offset for module 0x%04x\n", + module); return ICE_ERR_PARAM; } @@ -292,7 +340,7 @@ ice_read_flash_module(struct ice_hw *hw, enum ice_flash_bank bank, u16 module, static enum ice_status ice_read_active_nvm_module(struct ice_hw *hw, u32 offset, u16 *data) { - return ice_read_flash_module(hw, hw->flash.banks.nvm_bank, + return ice_read_flash_module(hw, ICE_ACTIVE_FLASH_BANK, ICE_SR_1ST_NVM_BANK_PTR, offset, data); } @@ -309,7 +357,7 @@ ice_read_active_nvm_module(struct ice_hw *hw, u32 offset, u16 *data) static enum ice_status ice_read_active_orom_module(struct ice_hw *hw, u32 offset, u16 *data) { - return ice_read_flash_module(hw, hw->flash.banks.orom_bank, + return ice_read_flash_module(hw, ICE_ACTIVE_FLASH_BANK, ICE_SR_1ST_OROM_BANK_PTR, offset, data); } diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 3b54ce92e1..b0f70c15dd 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -537,6 +537,15 @@ enum ice_flash_bank { ICE_2ND_FLASH_BANK, }; +/* Enumeration of which flash bank is desired to read from, either the active + * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from + * code which just wants to read the active or inactive flash bank. + */ +enum ice_bank_select { + ICE_ACTIVE_FLASH_BANK, + ICE_INACTIVE_FLASH_BANK, +}; + /* information for accessing NVM, OROM, and Netlist flash banks */ struct ice_bank_info { u32 nvm_ptr; /* Pointer to 1st NVM bank */ From patchwork Tue Dec 15 06:04:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85162 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5463EA09E9; Tue, 15 Dec 2020 07:03:17 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7E780C9C0; Tue, 15 Dec 2020 07:01:39 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id BC346C9A4 for ; Tue, 15 Dec 2020 07:01:33 +0100 (CET) IronPort-SDR: lp27y2NKrYhb+8dEqziwgcSd1qmZvqW1Fyea7irnoBv3AUZUm32lU1l7YwcoPPQOb3aYQCxxRm MoDSpTqTgOjA== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200222" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200222" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:33 -0800 IronPort-SDR: UjwDFkUGr+d2ZxNdioVvBksxDCFLSL1cby5iVq1v/LMQO4ftHt7ZRRBLNvzdjCIpFDPafM/qhI MH1QXernqb8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723363" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:31 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Jacob Keller Date: Tue, 15 Dec 2020 14:04:57 +0800 Message-Id: <20201215060519.302145-6-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 05/27] net/ice/base: allow reading inactive flash security revision X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Modify ice_get_nvm_srev and ice_get_orom_srev to take the ice_flash_bank enumeration that specifies whether to read from the active or the inactive flash module. Rename and refactor the ice_read_active_nvm_module and ice_read_active_orom_module functions to take the bank enum value as well. With this change, ice_get_nvm_srev and ice_get_orom_srev will be usable in a future change to implement reading the version data for a pending flash image. Signed-off-by: Jacob Keller Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_nvm.c | 36 ++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index facfaf1a41..4c709fd866 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -329,8 +329,9 @@ ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module, } /** - * ice_read_active_nvm_module - Read from the active main NVM module + * ice_read_nvm_module - Read from the active main NVM module * @hw: pointer to the HW structure + * @bank: whether to read from active or inactive NVM module * @offset: offset into the NVM module to read, in words * @data: storage for returned word value * @@ -338,15 +339,15 @@ ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module, * header at the start of the NVM module. */ static enum ice_status -ice_read_active_nvm_module(struct ice_hw *hw, u32 offset, u16 *data) +ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data) { - return ice_read_flash_module(hw, ICE_ACTIVE_FLASH_BANK, - ICE_SR_1ST_NVM_BANK_PTR, offset, data); + return ice_read_flash_module(hw, bank, ICE_SR_1ST_NVM_BANK_PTR, offset, data); } /** - * ice_read_active_orom_module - Read from the active Option ROM module + * ice_read_orom_module - Read from the active Option ROM module * @hw: pointer to the HW structure + * @bank: whether to read from active or inactive OROM module * @offset: offset into the OROM module to read, in words * @data: storage for returned word value * @@ -355,10 +356,9 @@ ice_read_active_nvm_module(struct ice_hw *hw, u32 offset, u16 *data) * module instead of at the beginning. */ static enum ice_status -ice_read_active_orom_module(struct ice_hw *hw, u32 offset, u16 *data) +ice_read_orom_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data) { - return ice_read_flash_module(hw, ICE_ACTIVE_FLASH_BANK, - ICE_SR_1ST_OROM_BANK_PTR, offset, data); + return ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, offset, data); } /** @@ -510,21 +510,22 @@ ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size) /** * ice_get_nvm_srev - Read the security revision from the NVM CSS header * @hw: pointer to the HW struct + * @bank: whether to read from the active or inactive flash bank * @srev: storage for security revision * * Read the security revision out of the CSS header of the active NVM module * bank. */ -static enum ice_status ice_get_nvm_srev(struct ice_hw *hw, u32 *srev) +static enum ice_status ice_get_nvm_srev(struct ice_hw *hw, enum ice_bank_select bank, u32 *srev) { enum ice_status status; u16 srev_l, srev_h; - status = ice_read_active_nvm_module(hw, ICE_NVM_CSS_SREV_L, &srev_l); + status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_SREV_L, &srev_l); if (status) return status; - status = ice_read_active_nvm_module(hw, ICE_NVM_CSS_SREV_H, &srev_h); + status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_SREV_H, &srev_h); if (status) return status; @@ -568,7 +569,7 @@ ice_get_nvm_ver_info(struct ice_hw *hw, struct ice_nvm_info *nvm) nvm->eetrack = (eetrack_hi << 16) | eetrack_lo; - status = ice_get_nvm_srev(hw, &nvm->srev); + status = ice_get_nvm_srev(hw, ICE_ACTIVE_FLASH_BANK, &nvm->srev); if (status) ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM security revision.\n"); @@ -578,12 +579,13 @@ ice_get_nvm_ver_info(struct ice_hw *hw, struct ice_nvm_info *nvm) /** * ice_get_orom_srev - Read the security revision from the OROM CSS header * @hw: pointer to the HW struct + * @bank: whether to read from active or inactive flash module * @srev: storage for security revision * * Read the security revision out of the CSS header of the active OROM module * bank. */ -static enum ice_status ice_get_orom_srev(struct ice_hw *hw, u32 *srev) +static enum ice_status ice_get_orom_srev(struct ice_hw *hw, enum ice_bank_select bank, u32 *srev) { enum ice_status status; u16 srev_l, srev_h; @@ -596,16 +598,16 @@ static enum ice_status ice_get_orom_srev(struct ice_hw *hw, u32 *srev) } /* calculate how far into the Option ROM the CSS header starts. Note - * that ice_read_active_orom_module takes a word offset so we need to + * that ice_read_orom_module takes a word offset so we need to * divide by 2 here. */ css_start = (hw->flash.banks.orom_size - ICE_NVM_OROM_TRAILER_LENGTH) / 2; - status = ice_read_active_orom_module(hw, css_start + ICE_NVM_CSS_SREV_L, &srev_l); + status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_L, &srev_l); if (status) return status; - status = ice_read_active_orom_module(hw, css_start + ICE_NVM_CSS_SREV_H, &srev_h); + status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_H, &srev_h); if (status) return status; @@ -666,7 +668,7 @@ ice_get_orom_ver_info(struct ice_hw *hw, struct ice_orom_info *orom) orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >> ICE_OROM_VER_BUILD_SHIFT); - status = ice_get_orom_srev(hw, &orom->srev); + status = ice_get_orom_srev(hw, ICE_ACTIVE_FLASH_BANK, &orom->srev); if (status) ice_debug(hw, ICE_DBG_NVM, "Failed to read Option ROM security revision.\n"); From patchwork Tue Dec 15 06:04:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85163 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0B0D1A09E9; Tue, 15 Dec 2020 07:03:39 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 91233C9C8; Tue, 15 Dec 2020 07:01:40 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 843D3C9A8 for ; Tue, 15 Dec 2020 07:01:35 +0100 (CET) IronPort-SDR: J39qMrjflhwtyzWjNaVy4MAkiRM96Bsnp2cXR9urtcfl0/i94NK5MFPIyONx0Ddhbszwq+lJiy 2MZNusrd9TlQ== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200227" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200227" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:35 -0800 IronPort-SDR: MOI6jVjX5JUg/Ru5hDeeVgx4EfWVLKxiqv1BA4lUvOmg8EzXiD3EHqEdatgsWS5lXZeIbpAzns Q4rFhf0YMKBw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723382" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:33 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Jacob Keller Date: Tue, 15 Dec 2020 14:04:58 +0800 Message-Id: <20201215060519.302145-7-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 06/27] net/ice/base: allow reading arbitrary size data with flash read X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Refactor ice_read_flash_module so that it takes a size and a length value, rather than always reading in 2-byte increments. The ice_read_nvm_module and ice_read_orom_module wrapper functions will still read a u16 with the byte-swapping enabled. This will be used in a future change to implement reading of the CIVD data from the Option ROM module. Signed-off-by: Jacob Keller Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_nvm.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index 4c709fd866..e2c9068bc5 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -285,8 +285,9 @@ static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select ban * @hw: pointer to the HW structure * @bank: which bank of the module to read * @module: the module to read - * @offset: the offset into the module in words + * @offset: the offset into the module in bytes * @data: storage for the word read from the flash + * @length: bytes of data to read * * Read data from the specified flash module. The bank parameter indicates * whether or not to read from the active bank or the inactive bank of that @@ -298,11 +299,9 @@ static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select ban */ static enum ice_status ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module, - u32 offset, u16 *data) + u32 offset, u8 *data, u32 length) { - u32 bytes = sizeof(u16); enum ice_status status; - __le16 data_local; u32 start; ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); @@ -318,10 +317,7 @@ ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module, if (status) return status; - status = ice_read_flat_nvm(hw, start + offset * sizeof(u16), &bytes, - (_FORCE_ u8 *)&data_local, false); - if (!status) - *data = LE16_TO_CPU(data_local); + status = ice_read_flat_nvm(hw, start + offset, &length, data, false); ice_release_nvm(hw); @@ -341,7 +337,15 @@ ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module, static enum ice_status ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data) { - return ice_read_flash_module(hw, bank, ICE_SR_1ST_NVM_BANK_PTR, offset, data); + enum ice_status status; + __le16 data_local; + + status = ice_read_flash_module(hw, bank, ICE_SR_1ST_NVM_BANK_PTR, offset * sizeof(u16), + (_FORCE_ u8 *)&data_local, sizeof(u16)); + if (!status) + *data = LE16_TO_CPU(data_local); + + return status; } /** @@ -358,7 +362,15 @@ ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u1 static enum ice_status ice_read_orom_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data) { - return ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, offset, data); + enum ice_status status; + __le16 data_local; + + status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, offset * sizeof(u16), + (_FORCE_ u8 *)&data_local, sizeof(u16)); + if (!status) + *data = LE16_TO_CPU(data_local); + + return status; } /** From patchwork Tue Dec 15 06:04:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85164 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 68EC0A09E9; Tue, 15 Dec 2020 07:04:05 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8940EC9E6; Tue, 15 Dec 2020 07:01:42 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 830A9C9B4 for ; Tue, 15 Dec 2020 07:01:37 +0100 (CET) IronPort-SDR: I+VncG7jKyQhwqp0TqjhgGxpbOIeLumFtXaDbyBrdp/L+g7+bhLJs1i3l8UhlwgsKZV758aq27 MrBqrpmWagIw== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200231" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200231" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:36 -0800 IronPort-SDR: YUCgF59evXF+HauVack6c1k/1qV/+agsb6Y/DIs883Qqo9OJeXib0htP5w+WIpvT4QXOCpnvpC wBe0z7tWmwRw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723402" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:35 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Jacob Keller Date: Tue, 15 Dec 2020 14:04:59 +0800 Message-Id: <20201215060519.302145-8-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 07/27] net/ice/base: read Option ROM combo version from CIVD section X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The driver currently reads the combo image version data from within the Boot Configuration TLV block of the PFA area of the NVM. This allows access to the active Option ROM version data, assuming that it has been properly copied into this section. There is no equivalent method for reading the Option ROM version data from a pending Option ROM update, as it will not yet have been copied into the PFA boot configuration block. Instead, replace this implementation with one which scans for the CIVD data section of the Option ROM image data. This CIVD data is stored in a packed structured format within the Option ROM. It is always aligned to a 512 byte boundary, and starts with a special '$CIV' 4-byte signature. Data integrity is checked using a simple modulo 256 sum of the structure bytes. Implement a new ice_get_orom_civd_data function which allows reading from the selected flash bank (active or inactive), and scans for valid CIVD data. Use this instead of the boot configuration TLV in order to report the combo version data of precisely what is in the Option ROM data. To allow access to reading the inactive Option ROM bank, introduce a new ice_get_inactive_orom_ver function. Use of a new function is done in order to avoid leaking the bank selection abstraction outside of ice_nvm.c With this new function, the driver can now read and display the version of the to-be-activated Option ROM when an update has been initiated but not yet finalized. Signed-off-by: Jacob Keller Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_nvm.c | 121 ++++++++++++++++++++++----------- drivers/net/ice/base/ice_nvm.h | 13 ++++ 2 files changed, 95 insertions(+), 39 deletions(-) diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index e2c9068bc5..71affd1812 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -629,64 +629,109 @@ static enum ice_status ice_get_orom_srev(struct ice_hw *hw, enum ice_bank_select } /** - * ice_get_orom_ver_info - Read Option ROM version information + * ice_get_orom_civd_data - Get the combo version information from Option ROM * @hw: pointer to the HW struct - * @orom: pointer to Option ROM info structure + * @bank: whether to read from the active or inactive flash module + * @civd: storage for the Option ROM CIVD data. * - * Read the Combo Image version data from the Boot Configuration TLV and fill - * in the option ROM version data. + * Searches through the Option ROM flash contents to locate the CIVD data for + * the image. */ static enum ice_status -ice_get_orom_ver_info(struct ice_hw *hw, struct ice_orom_info *orom) +ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank, + struct ice_orom_civd_info *civd) { - u16 combo_hi, combo_lo, boot_cfg_tlv, boot_cfg_tlv_len; + struct ice_orom_civd_info tmp; enum ice_status status; - u32 combo_ver; - - status = ice_get_pfa_module_tlv(hw, &boot_cfg_tlv, &boot_cfg_tlv_len, - ICE_SR_BOOT_CFG_PTR); - if (status) { - ice_debug(hw, ICE_DBG_INIT, "Failed to read Boot Configuration Block TLV.\n"); - return status; - } + u32 offset; - /* Boot Configuration Block must have length at least 2 words - * (Combo Image Version High and Combo Image Version Low) + /* The CIVD section is located in the Option ROM aligned to 512 bytes. + * The first 4 bytes must contain the ASCII characters "$CIV". + * A simple modulo 256 sum of all of the bytes of the structure must + * equal 0. */ - if (boot_cfg_tlv_len < 2) { - ice_debug(hw, ICE_DBG_INIT, "Invalid Boot Configuration Block TLV size.\n"); - return ICE_ERR_INVAL_SIZE; - } + for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size; offset += 512) { + u8 sum = 0, i; - status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OROM_VER_OFF), - &combo_hi); - if (status) { - ice_debug(hw, ICE_DBG_INIT, "Failed to read OROM_VER hi.\n"); - return status; + status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, + offset, (u8 *)&tmp, sizeof(tmp)); + if (status) { + ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM CIVD data\n"); + return status; + } + + /* Skip forward until we find a matching signature */ + if (memcmp("$CIV", tmp.signature, sizeof(tmp.signature)) != 0) + continue; + + /* Verify that the simple checksum is zero */ + for (i = 0; i < sizeof(tmp); i++) + sum += ((u8 *)&tmp)[i]; + + if (sum) { + ice_debug(hw, ICE_DBG_NVM, "Found CIVD data with invalid checksum of %u\n", + sum); + return ICE_ERR_NVM; + } + + *civd = tmp; + return ICE_SUCCESS; } - status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OROM_VER_OFF + 1), - &combo_lo); + return ICE_ERR_NVM; +} + +/** + * ice_get_orom_ver_info - Read Option ROM version information + * @hw: pointer to the HW struct + * @bank: whether to read from the active or inactive flash module + * @orom: pointer to Option ROM info structure + * + * Read Option ROM version and security revision from the Option ROM flash + * section. + */ +static enum ice_status +ice_get_orom_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_info *orom) +{ + struct ice_orom_civd_info civd; + enum ice_status status; + u32 combo_ver; + + status = ice_get_orom_civd_data(hw, bank, &civd); if (status) { - ice_debug(hw, ICE_DBG_INIT, "Failed to read OROM_VER lo.\n"); + ice_debug(hw, ICE_DBG_NVM, "Failed to locate valid Option ROM CIVD data\n"); return status; } - combo_ver = ((u32)combo_hi << 16) | combo_lo; + combo_ver = LE32_TO_CPU(civd.combo_ver); - orom->major = (u8)((combo_ver & ICE_OROM_VER_MASK) >> - ICE_OROM_VER_SHIFT); + orom->major = (u8)((combo_ver & ICE_OROM_VER_MASK) >> ICE_OROM_VER_SHIFT); orom->patch = (u8)(combo_ver & ICE_OROM_VER_PATCH_MASK); - orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >> - ICE_OROM_VER_BUILD_SHIFT); + orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >> ICE_OROM_VER_BUILD_SHIFT); - status = ice_get_orom_srev(hw, ICE_ACTIVE_FLASH_BANK, &orom->srev); - if (status) + status = ice_get_orom_srev(hw, bank, &orom->srev); + if (status) { ice_debug(hw, ICE_DBG_NVM, "Failed to read Option ROM security revision.\n"); + return status; + } return ICE_SUCCESS; } +/** + * ice_get_inactive_orom_ver - Read Option ROM version from the inactive bank + * @hw: pointer to the HW structure + * @orom: storage for Option ROM version information + * + * Reads the Option ROM version and security revision data for the inactive + * section of flash. Used to access version data for a pending update that has + * not yet been activated. + */ +enum ice_status ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom) +{ + return ice_get_orom_ver_info(hw, ICE_INACTIVE_FLASH_BANK, orom); +} + /** * ice_discover_flash_size - Discover the available flash size. * @hw: pointer to the HW struct @@ -937,11 +982,9 @@ enum ice_status ice_init_nvm(struct ice_hw *hw) return status; } - status = ice_get_orom_ver_info(hw, &flash->orom); - if (status) { + status = ice_get_orom_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->orom); + if (status) ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n"); - return status; - } return ICE_SUCCESS; } diff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h index 8e2eb4df1b..74fd16305a 100644 --- a/drivers/net/ice/base/ice_nvm.h +++ b/drivers/net/ice/base/ice_nvm.h @@ -26,6 +26,17 @@ #define ICE_NVM_REG_RW_MODULE 0x0 #define ICE_NVM_REG_RW_FLAGS 0x1 +#pragma pack(1) +struct ice_orom_civd_info { + u8 signature[4]; /* Must match ASCII '$CIV' characters */ + u8 checksum; /* Simple modulo 256 sum of all structure bytes must equal 0 */ + __le32 combo_ver; /* Combo Image Version number */ + u8 combo_name_len; /* Length of the unicode combo image version string, max of 32 */ + __le16 combo_name[32]; /* Unicode string representing the Combo Image version */ +}; + +#pragma pack() + #define ICE_NVM_ACCESS_MAJOR_VER 0 #define ICE_NVM_ACCESS_MINOR_VER 5 @@ -98,6 +109,8 @@ enum ice_status ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len, u16 module_type); enum ice_status +ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom); +enum ice_status ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size); enum ice_status ice_init_nvm(struct ice_hw *hw); enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data); From patchwork Tue Dec 15 06:05:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85165 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id ACC92A09E9; Tue, 15 Dec 2020 07:04:25 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 34079C9F0; Tue, 15 Dec 2020 07:01:44 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id D5C2BC9C4 for ; Tue, 15 Dec 2020 07:01:38 +0100 (CET) IronPort-SDR: rZXrD7UZ2tscXA3oHDFQgyp/Y7ZyO72qbkuVfKypTn8uU6L/kCbX8yRcrI1DJaDo5vQIK+ioBL vHXUtRDkvE/Q== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200237" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200237" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:38 -0800 IronPort-SDR: K/6PjvxY5VvkCXf5YmXWQjoWJKBA4yxZlgvo/KHM9p52Kg8JpOvaKYonPXpc9+7dGUbsystv35 vTb39CSBVTKA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723424" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:36 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Jacob Keller Date: Tue, 15 Dec 2020 14:05:00 +0800 Message-Id: <20201215060519.302145-9-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 08/27] net/ice/base: implement inactive NVM version get X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Similar to ice_get_inactive_orom_ver, add a function to read the NVM version data from the inactive section of flash. The primary motivation of this function is to allow the driver to report the version of a pending update that has not yet been activated. To do this, refactor ice_get_nvm_ver_info to allow it to take a bank parameter. Read from the copy of the Shadow RAM in the NVM bank, rather than reading from the RAM copy that is loaded by the device. This ensures we get the accurate value when reading the inactive section. Note that the start of the Shadow RAM copy is not directly following the CSS header, but is actually aligned to the next 64-byte boundary. The correct word offset must be rounded up to 32-bytes. Signed-off-by: Jacob Keller Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_nvm.c | 44 ++++++++++++++++++++++++++++----- drivers/net/ice/base/ice_nvm.h | 2 ++ drivers/net/ice/base/ice_type.h | 8 +++++- 3 files changed, 47 insertions(+), 7 deletions(-) diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index 71affd1812..c807ce9ebc 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -348,6 +348,22 @@ ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u1 return status; } +/** + * ice_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank + * @hw: pointer to the HW structure + * @bank: whether to read from the active or inactive NVM module + * @offset: offset into the Shadow RAM copy to read, in words + * @data: storage for returned word value + * + * Read the specified word from the copy of the Shadow RAM found in the + * specified NVM module. + */ +static enum ice_status +ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data) +{ + return ice_read_nvm_module(hw, bank, ICE_NVM_SR_COPY_WORD_OFFSET + offset, data); +} + /** * ice_read_orom_module - Read from the active Option ROM module * @hw: pointer to the HW structure @@ -549,31 +565,33 @@ static enum ice_status ice_get_nvm_srev(struct ice_hw *hw, enum ice_bank_select /** * ice_get_nvm_ver_info - Read NVM version information * @hw: pointer to the HW struct + * @bank: whether to read from the active or inactive flash bank * @nvm: pointer to NVM info structure * * Read the NVM EETRACK ID and map version of the main NVM image bank, filling * in the nvm info structure. */ static enum ice_status -ice_get_nvm_ver_info(struct ice_hw *hw, struct ice_nvm_info *nvm) +ice_get_nvm_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_nvm_info *nvm) { u16 eetrack_lo, eetrack_hi, ver; enum ice_status status; - status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &ver); + status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_DEV_STARTER_VER, &ver); if (status) { ice_debug(hw, ICE_DBG_NVM, "Failed to read DEV starter version.\n"); return status; } + nvm->major = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT; nvm->minor = (ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT; - status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo); + status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_LO, &eetrack_lo); if (status) { ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK lo.\n"); return status; } - status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi); + status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_HI, &eetrack_hi); if (status) { ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK hi.\n"); return status; @@ -581,13 +599,27 @@ ice_get_nvm_ver_info(struct ice_hw *hw, struct ice_nvm_info *nvm) nvm->eetrack = (eetrack_hi << 16) | eetrack_lo; - status = ice_get_nvm_srev(hw, ICE_ACTIVE_FLASH_BANK, &nvm->srev); + status = ice_get_nvm_srev(hw, bank, &nvm->srev); if (status) ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM security revision.\n"); return ICE_SUCCESS; } +/** + * ice_get_inactive_nvm_ver - Read Option ROM version from the inactive bank + * @hw: pointer to the HW structure + * @nvm: storage for Option ROM version information + * + * Reads the NVM EETRACK ID, Map version, and security revision of the + * inactive NVM bank. Used to access version data for a pending update that + * has not yet been activated. + */ +enum ice_status ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm) +{ + return ice_get_nvm_ver_info(hw, ICE_INACTIVE_FLASH_BANK, nvm); +} + /** * ice_get_orom_srev - Read the security revision from the OROM CSS header * @hw: pointer to the HW struct @@ -976,7 +1008,7 @@ enum ice_status ice_init_nvm(struct ice_hw *hw) return status; } - status = ice_get_nvm_ver_info(hw, &flash->nvm); + status = ice_get_nvm_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->nvm); if (status) { ice_debug(hw, ICE_DBG_INIT, "Failed to read NVM info.\n"); return status; diff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h index 74fd16305a..52f79ca5c9 100644 --- a/drivers/net/ice/base/ice_nvm.h +++ b/drivers/net/ice/base/ice_nvm.h @@ -111,6 +111,8 @@ ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len, enum ice_status ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom); enum ice_status +ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm); +enum ice_status ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size); enum ice_status ice_init_nvm(struct ice_hw *hw); enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data); diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index b0f70c15dd..828c7a7fd5 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -1157,8 +1157,14 @@ struct ice_aq_get_set_rss_lut_params { #define ICE_NVM_CSS_SREV_L 0x14 #define ICE_NVM_CSS_SREV_H 0x15 +/* Length of CSS header section in words */ +#define ICE_CSS_HEADER_LENGTH 330 + +/* Offset of Shadow RAM copy in the NVM bank area. */ +#define ICE_NVM_SR_COPY_WORD_OFFSET ROUND_UP(ICE_CSS_HEADER_LENGTH, 32) + /* Size in bytes of Option ROM trailer */ -#define ICE_NVM_OROM_TRAILER_LENGTH 660 +#define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH) /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ #define ICE_SR_VPD_SIZE_WORDS 512 From patchwork Tue Dec 15 06:05:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85166 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B917FA09E9; Tue, 15 Dec 2020 07:04:46 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B7848CA00; Tue, 15 Dec 2020 07:01:45 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id B729CC9CC for ; Tue, 15 Dec 2020 07:01:40 +0100 (CET) IronPort-SDR: zYI/AaROdpmlcbQnCnyG720GbEioRxtaqhJsevhllXtwdffsIB4cjUYHumA9uC/2OMHA48R/xC JDa+icW7GxCw== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200245" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200245" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:40 -0800 IronPort-SDR: h8EnVoEd3XVcO4UThjMDEwjRyiMzRCYsPldtWkloIKW0YMzlXP9r3juRYhzWiGRiBrfvJrWTgv iz8IR6A2JkKw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723448" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:38 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Kiran Patil Date: Tue, 15 Dec 2020 14:05:01 +0800 Message-Id: <20201215060519.302145-10-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 09/27] net/ice/base: support GTP filtering via advanced switch filter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support to enable GTP filtering using advanced switch filter mechanism. Example of GTP filter criteria: Outer UDP + GTP (Optional) + Inner IPv4[6] + Inner TCP/UDP Signed-off-by: Kiran Patil Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flex_type.h | 1 + drivers/net/ice/base/ice_switch.c | 407 +++++++++++++++++++++++++++ 2 files changed, 408 insertions(+) diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h index 1dd57baccd..7d0204fa50 100644 --- a/drivers/net/ice/base/ice_flex_type.h +++ b/drivers/net/ice/base/ice_flex_type.h @@ -516,6 +516,7 @@ struct ice_pkg_enum { enum ice_tunnel_type { TNL_VXLAN = 0, TNL_GENEVE, + TNL_GTP, TNL_LAST = 0xFF, TNL_ALL = 0xFF, }; diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index dc55d7e3ce..45c44ca256 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -504,6 +504,413 @@ static const u8 dummy_vlan_udp_ipv6_packet[] = { 0x00, 0x00, /* 2 bytes for 4 byte alignment */ }; +/* Outer IPv4 + Outer UDP + GTP + Inner IPv4 + Inner TCP */ +static const struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv4_tcp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_UDP_OF, 34 }, + { ICE_GTP, 42 }, + { ICE_IPV4_IL, 62 }, + { ICE_TCP_IL, 82 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_ipv4_gtpu_ipv4_tcp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* Ethernet 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, + + 0x45, 0x00, 0x00, 0x58, /* IP 14 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x11, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x08, 0x68, /* UDP 34 */ + 0x00, 0x44, 0x00, 0x00, + + 0x34, 0xff, 0x00, 0x34, /* GTP-U Header 42 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x85, + + 0x02, 0x00, 0x00, 0x00, /* GTP_PDUSession_ExtensionHeader 54 */ + 0x00, 0x00, 0x00, 0x00, + + 0x45, 0x00, 0x00, 0x28, /* IP 62 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x06, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* TCP 82 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 byte alignment */ +}; + +/* Outer IPv4 + Outer UDP + GTP + Inner IPv4 + Inner UDP */ +static const struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv4_udp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_UDP_OF, 34 }, + { ICE_GTP, 42 }, + { ICE_IPV4_IL, 62 }, + { ICE_UDP_ILOS, 82 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_ipv4_gtpu_ipv4_udp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* Ethernet 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, + + 0x45, 0x00, 0x00, 0x4c, /* IP 14 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x11, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x08, 0x68, /* UDP 34 */ + 0x00, 0x38, 0x00, 0x00, + + 0x34, 0xff, 0x00, 0x28, /* GTP-U Header 42 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x85, + + 0x02, 0x00, 0x00, 0x00, /* GTP_PDUSession_ExtensionHeader 54 */ + 0x00, 0x00, 0x00, 0x00, + + 0x45, 0x00, 0x00, 0x1c, /* IP 62 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x11, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* UDP 82 */ + 0x00, 0x08, 0x00, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 byte alignment */ +}; + +/* Outer IPv6 + Outer UDP + GTP + Inner IPv4 + Inner TCP */ +static const struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv6_tcp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_UDP_OF, 34 }, + { ICE_GTP, 42 }, + { ICE_IPV6_IL, 62 }, + { ICE_TCP_IL, 102 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_ipv4_gtpu_ipv6_tcp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* Ethernet 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, + + 0x45, 0x00, 0x00, 0x6c, /* IP 14 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x11, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x08, 0x68, /* UDP 34 */ + 0x00, 0x58, 0x00, 0x00, + + 0x34, 0xff, 0x00, 0x48, /* GTP-U Header 42 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x85, + + 0x02, 0x00, 0x00, 0x00, /* GTP_PDUSession_ExtensionHeader 54 */ + 0x00, 0x00, 0x00, 0x00, + + 0x60, 0x00, 0x00, 0x00, /* IPv6 62 */ + 0x00, 0x14, 0x06, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* TCP 102 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 byte alignment */ +}; + +static const struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv6_udp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_UDP_OF, 34 }, + { ICE_GTP, 42 }, + { ICE_IPV6_IL, 62 }, + { ICE_UDP_ILOS, 102 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_ipv4_gtpu_ipv6_udp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* Ethernet 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, + + 0x45, 0x00, 0x00, 0x60, /* IP 14 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x11, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x08, 0x68, /* UDP 34 */ + 0x00, 0x4c, 0x00, 0x00, + + 0x34, 0xff, 0x00, 0x3c, /* GTP-U Header 42 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x85, + + 0x02, 0x00, 0x00, 0x00, /* GTP_PDUSession_ExtensionHeader 54 */ + 0x00, 0x00, 0x00, 0x00, + + 0x60, 0x00, 0x00, 0x00, /* IPv6 62 */ + 0x00, 0x08, 0x11, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* UDP 102 */ + 0x00, 0x08, 0x00, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 byte alignment */ +}; + +static const struct ice_dummy_pkt_offsets dummy_ipv6_gtpu_ipv4_tcp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_IPV6_OFOS, 14 }, + { ICE_UDP_OF, 54 }, + { ICE_GTP, 62 }, + { ICE_IPV4_IL, 82 }, + { ICE_TCP_IL, 102 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_ipv6_gtpu_ipv4_tcp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* Ethernet 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x86, 0xdd, + + 0x60, 0x00, 0x00, 0x00, /* IPv6 14 */ + 0x00, 0x44, 0x11, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x08, 0x68, /* UDP 54 */ + 0x00, 0x44, 0x00, 0x00, + + 0x34, 0xff, 0x00, 0x34, /* GTP-U Header 62 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x85, + + 0x02, 0x00, 0x00, 0x00, /* GTP_PDUSession_ExtensionHeader 74 */ + 0x00, 0x00, 0x00, 0x00, + + 0x45, 0x00, 0x00, 0x28, /* IP 82 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x06, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* TCP 102 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 byte alignment */ +}; + +static const struct ice_dummy_pkt_offsets dummy_ipv6_gtpu_ipv4_udp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_IPV6_OFOS, 14 }, + { ICE_UDP_OF, 54 }, + { ICE_GTP, 62 }, + { ICE_IPV4_IL, 82 }, + { ICE_UDP_ILOS, 102 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_ipv6_gtpu_ipv4_udp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* Ethernet 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x86, 0xdd, + + 0x60, 0x00, 0x00, 0x00, /* IPv6 14 */ + 0x00, 0x38, 0x11, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x08, 0x68, /* UDP 54 */ + 0x00, 0x38, 0x00, 0x00, + + 0x34, 0xff, 0x00, 0x28, /* GTP-U Header 62 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x85, + + 0x02, 0x00, 0x00, 0x00, /* GTP_PDUSession_ExtensionHeader 74 */ + 0x00, 0x00, 0x00, 0x00, + + 0x45, 0x00, 0x00, 0x1c, /* IP 82 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x11, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* UDP 102 */ + 0x00, 0x08, 0x00, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 byte alignment */ +}; + +static const struct ice_dummy_pkt_offsets dummy_ipv6_gtpu_ipv6_tcp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_IPV6_OFOS, 14 }, + { ICE_UDP_OF, 54 }, + { ICE_GTP, 62 }, + { ICE_IPV6_IL, 82 }, + { ICE_TCP_IL, 102 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_ipv6_gtpu_ipv6_tcp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* Ethernet 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x86, 0xdd, + + 0x60, 0x00, 0x00, 0x00, /* IPv6 14 */ + 0x00, 0x58, 0x11, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x08, 0x68, /* UDP 54 */ + 0x00, 0x58, 0x00, 0x00, + + 0x34, 0xff, 0x00, 0x48, /* GTP-U Header 62 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x85, + + 0x02, 0x00, 0x00, 0x00, /* GTP_PDUSession_ExtensionHeader 74 */ + 0x00, 0x00, 0x00, 0x00, + + 0x60, 0x00, 0x00, 0x00, /* IPv6 82 */ + 0x00, 0x14, 0x06, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* TCP 122 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 byte alignment */ +}; + +static const struct ice_dummy_pkt_offsets dummy_ipv6_gtpu_ipv6_udp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_IPV6_OFOS, 14 }, + { ICE_UDP_OF, 54 }, + { ICE_GTP, 62 }, + { ICE_IPV6_IL, 82 }, + { ICE_UDP_ILOS, 102 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_ipv6_gtpu_ipv6_udp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* Ethernet 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x86, 0xdd, + + 0x60, 0x00, 0x00, 0x00, /* IPv6 14 */ + 0x00, 0x4c, 0x11, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x08, 0x68, /* UDP 54 */ + 0x00, 0x4c, 0x00, 0x00, + + 0x34, 0xff, 0x00, 0x3c, /* GTP-U Header 62 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x85, + + 0x02, 0x00, 0x00, 0x00, /* GTP_PDUSession_ExtensionHeader 74 */ + 0x00, 0x00, 0x00, 0x00, + + 0x60, 0x00, 0x00, 0x00, /* IPv6 82 */ + 0x00, 0x08, 0x11, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* UDP 122 */ + 0x00, 0x08, 0x00, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 byte alignment */ +}; + static const struct ice_dummy_pkt_offsets dummy_udp_gtp_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, { ICE_IPV4_OFOS, 14 }, From patchwork Tue Dec 15 06:05:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85167 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2709AA09E9; Tue, 15 Dec 2020 07:05:13 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C97ABCA12; Tue, 15 Dec 2020 07:01:47 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 39C5FC9DA for ; Tue, 15 Dec 2020 07:01:42 +0100 (CET) IronPort-SDR: RG0fZJSaZK+SgYmW/KO2Brt+tigzgGZraT2u/f3bCbpX5LA5Loxy78DX80SIyg9/pq0ew6zEIB oHeaNzD9RWQQ== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200251" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200251" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:41 -0800 IronPort-SDR: vtu80r9+9lY1aGQYcfkZfHC2y3konecwq8iPi5PPavDsTsSZuDItuGsAZ3I9fgJ/JLt6T22rxV VzYLixKif67w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723468" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:40 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang Date: Tue, 15 Dec 2020 14:05:02 +0800 Message-Id: <20201215060519.302145-11-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 10/27] net/ice/base: cleanup some macros X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Replaced the netlist related macro and removed some unused macro Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 26 ---------------- drivers/net/ice/base/ice_type.h | 43 ++++++++++++++++++++++----- 2 files changed, 35 insertions(+), 34 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index f715fb0910..17fd418b0e 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1709,32 +1709,6 @@ struct ice_aqc_nvm { #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ -/* The result of netlist NVM read comes in a TLV format. The actual data - * (netlist header) starts from word offset 1 (byte 2). The FW strips - * out the type field from the TLV header so all the netlist fields - * should adjust their offset value by 1 word (2 bytes) in order to map - * their correct location. - */ -#define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID 0x11B -#define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET 1 -#define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN 2 /* In bytes */ -#define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET 2 -#define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN 2 /* In bytes */ -#define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET 5 -#define ICE_AQC_NVM_NETLIST_ID_BLK_LEN 0x30 /* In words */ - -/* netlist ID block field offsets (word offsets) */ -#define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW 2 -#define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH 3 -#define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW 4 -#define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH 5 -#define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW 6 -#define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH 7 -#define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW 8 -#define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH 9 -#define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH 0xA -#define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER 0x2F - /* Used for 0x0704 as well as for 0x0705 commands */ struct ice_aqc_nvm_cfg { u8 cmd_flags; diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 828c7a7fd5..984dca6358 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -778,18 +778,10 @@ struct ice_dcb_app_priority_table { #define ICE_TLV_STATUS_OPER 0x1 #define ICE_TLV_STATUS_SYNC 0x2 #define ICE_TLV_STATUS_ERR 0x4 -#ifndef ICE_APP_PROT_ID_FCOE #define ICE_APP_PROT_ID_FCOE 0x8906 -#endif /* ICE_APP_PROT_ID_FCOE */ -#ifndef ICE_APP_PROT_ID_ISCSI #define ICE_APP_PROT_ID_ISCSI 0x0cbc -#endif /* ICE_APP_PROT_ID_ISCSI */ -#ifndef ICE_APP_PROT_ID_ISCSI_860 #define ICE_APP_PROT_ID_ISCSI_860 0x035c -#endif /* ICE_APP_PROT_ID_ISCSI_860 */ -#ifndef ICE_APP_PROT_ID_FIP #define ICE_APP_PROT_ID_FIP 0x8914 -#endif /* ICE_APP_PROT_ID_FIP */ #define ICE_APP_SEL_ETHTYPE 0x1 #define ICE_APP_SEL_TCPIP 0x2 #define ICE_CEE_APP_SEL_ETHTYPE 0x0 @@ -1166,6 +1158,41 @@ struct ice_aq_get_set_rss_lut_params { /* Size in bytes of Option ROM trailer */ #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH) +/* The Link Topology Netlist section is stored as a series of words. It is + * stored in the NVM as a TLV, with the first two words containing the type + * and length. + */ +#define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B +#define ICE_NETLIST_TYPE_OFFSET 0x0000 +#define ICE_NETLIST_LEN_OFFSET 0x0001 + +/* The Link Topology section follows the TLV header. When reading the netlist + * using ice_read_netlist_module, we need to account for the 2-word TLV + * header. + */ +#define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) + +#define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000) +#define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001) + +#define ICE_LINK_TOPO_NODE_COUNT_M MAKEMASK(0x3FF, 0) + +/* The Netlist ID Block is located after all of the Link Topology nodes. */ +#define ICE_NETLIST_ID_BLK_SIZE 0x30 +#define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) + +/* netlist ID block field offsets (word offsets) */ +#define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 +#define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 +#define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 +#define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 +#define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06 +#define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07 +#define ICE_NETLIST_ID_BLK_REV_LOW 0x08 +#define ICE_NETLIST_ID_BLK_REV_HIGH 0x09 +#define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) +#define ICE_NETLIST_ID_BLK_CUST_VER 0x2F + /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ #define ICE_SR_VPD_SIZE_WORDS 512 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512 From patchwork Tue Dec 15 06:05:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85168 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 02ABCA09E9; Tue, 15 Dec 2020 07:05:35 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 59B1ACA1E; Tue, 15 Dec 2020 07:01:49 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 9F848C9F6 for ; Tue, 15 Dec 2020 07:01:43 +0100 (CET) IronPort-SDR: W9sRkLBudRZoZaZl53pMZlJ5BVvSDEJaCYWB+Uv1TH2Y2tkQsMI+E3KMbRk0+pye0Zpcvlurk8 wfEE7kvQh56w== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200256" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200256" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:43 -0800 IronPort-SDR: vDCeR2rGvgp/MikYhMp/LNfZuvhoK1evO5KXa3lo0+eKsJ9ADGrhVK35OnsHrshY6/hjOHsteb 74aCMl2hZngA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723485" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:41 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Nick Nunley Date: Tue, 15 Dec 2020 14:05:03 +0800 Message-Id: <20201215060519.302145-12-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 11/27] net/ice/base: add definitions for FW health status codes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add definitions for the various health status codes that can be reported by firmware. Signed-off-by: Nick Nunley Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 17fd418b0e..e69691427a 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -2601,6 +2601,35 @@ struct ice_aqc_set_health_status_config { u8 reserved[15]; }; +#define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101 +#define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102 +#define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103 +#define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104 +#define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105 +#define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106 +#define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107 +#define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108 +#define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B +#define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C +#define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D +#define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F +#define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110 +#define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111 +#define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112 +#define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113 +#define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114 +#define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115 +#define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116 +#define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117 +#define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500 +#define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501 +#define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502 +#define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503 +#define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504 +#define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505 +#define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506 +#define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509 + /* Get Health Status codes (indirect 0xFF21) */ struct ice_aqc_get_supported_health_status_codes { __le16 health_code_count; From patchwork Tue Dec 15 06:05:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85169 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 12778A09E9; Tue, 15 Dec 2020 07:05:56 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4BD4ECA2C; Tue, 15 Dec 2020 07:01:50 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 43F5CC9FA for ; Tue, 15 Dec 2020 07:01:45 +0100 (CET) IronPort-SDR: SYKEcWFFgACX7QbMbz9jA8NpS/wxJvj3FOn2AUZDHMu6LhMkUbwvuNboYPQmZAOW2omoXTetpL fYE3zDuYZUPQ== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200261" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200261" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:44 -0800 IronPort-SDR: +eH4u8uVqYUZElFzxGlyZ9SzQvAYS9Mu6DeyxHfe6t4PAh5ZvHvwXMo+HC/0RQfobF8tL0kDhJ JfzZNTDE/0Qw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723508" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:43 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Milena Olech Date: Tue, 15 Dec 2020 14:05:04 +0800 Message-Id: <20201215060519.302145-13-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 12/27] net/ice/base: add function for NVM checksum verification X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" AQ 0x0706 lets user to verify and recalculate NVM checksum. The usage depends on command flags. Signed-off-by: Milena Olech Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_nvm.c | 28 ++++++++++++++++++++++++++++ drivers/net/ice/base/ice_nvm.h | 1 + 2 files changed, 29 insertions(+) diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index c807ce9ebc..45310bfc6b 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -1077,6 +1077,34 @@ enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw) return status; } +/** + * ice_nvm_recalculate_checksum + * @hw: pointer to the HW struct + * + * Recalculate NVM PFA checksum (0x0706) + */ +enum ice_status ice_nvm_recalculate_checksum(struct ice_hw *hw) +{ + struct ice_aqc_nvm_checksum *cmd; + struct ice_aq_desc desc; + enum ice_status status; + + status = ice_acquire_nvm(hw, ICE_RES_READ); + if (status) + return status; + + cmd = &desc.params.nvm_checksum; + + ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum); + cmd->flags = ICE_AQC_NVM_CHECKSUM_RECALC; + + status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); + + ice_release_nvm(hw); + + return status; +} + /** * ice_nvm_access_get_features - Return the NVM access features structure * @cmd: NVM access command to process diff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h index 52f79ca5c9..48b71950e9 100644 --- a/drivers/net/ice/base/ice_nvm.h +++ b/drivers/net/ice/base/ice_nvm.h @@ -119,4 +119,5 @@ enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data); enum ice_status ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data); enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw); +enum ice_status ice_nvm_recalculate_checksum(struct ice_hw *hw); #endif /* _ICE_NVM_H_ */ From patchwork Tue Dec 15 06:05:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85170 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2364FA09E9; Tue, 15 Dec 2020 07:06:17 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DAAC8CA35; Tue, 15 Dec 2020 07:01:51 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 1D425CA06 for ; Tue, 15 Dec 2020 07:01:46 +0100 (CET) IronPort-SDR: 1rREDyIxztKPx1CUt6PBbbsJHwxlukuTCDQNEb6UiatVmMGYMJz8lBQlHCXAcY9RB4zCK0ELSG E4qG6w7+6Oaw== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200269" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200269" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:46 -0800 IronPort-SDR: mueLbm5q1TZzHmGJg/eFG3j99zyryk4CYjvlkkVKqG+rckFDWQXQgI3+DNTDERvLWBet1FnE0Y /JHTP5BKUAFA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723526" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:44 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Szymon T Cudzilo Date: Tue, 15 Dec 2020 14:05:05 +0800 Message-Id: <20201215060519.302145-14-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 13/27] net/ice/base: add condition to copy module info into memory X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" There is added condition,to copy information about used module into memory Signed-off-by: Szymon T Cudzilo Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_common.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index b217ae6d41..ca764b2566 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -2652,6 +2652,11 @@ enum ice_status ice_update_link_info(struct ice_port_info *pi) status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); + if (status == ICE_SUCCESS) + ice_memcpy(li->module_type, &pcaps->module_type, + sizeof(li->module_type), + ICE_NONDMA_TO_NONDMA); + ice_free(hw, pcaps); } From patchwork Tue Dec 15 06:05:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85171 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 147C7A09E9; Tue, 15 Dec 2020 07:06:36 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 105EBCA3A; Tue, 15 Dec 2020 07:01:53 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id D81ADCA26 for ; Tue, 15 Dec 2020 07:01:48 +0100 (CET) IronPort-SDR: gclv9xV+1GJJxzd0AMVCHRdpxRJp849vAxvgvrt3j3l3jQ02luu+qGz2BPr4RWmwvWmaTaUrmm kWHJ2DRF1d2g== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200275" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200275" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:48 -0800 IronPort-SDR: fmxT2mpC2WsNQqRERU/AxlPAmjMhbms472HkTef61zWE+8fy1lTCYzfvMQuYdpGcOcCv5xawEe 2m5OtXfEREqA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723547" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:46 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Brett Creeley Date: Tue, 15 Dec 2020 14:05:06 +0800 Message-Id: <20201215060519.302145-15-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 14/27] net/ice/base: add interface to support configuring VLAN mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The VLAN mode of the device has to be configured while the global configuration lock is held while downloading the DDP, specifically after the DDP has been downloaded. In order to support this a VLAN mode interface was added. By default the device will stay in single VLAN mode (SVM), which is the current implementation. However, this can be changed by implementing the .set_dvm op. Signed-off-by: Brett Creeley Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 23 ++++++++++++++ drivers/net/ice/base/ice_common.c | 40 ++++++++++++++++++++++++ drivers/net/ice/base/ice_common.h | 4 +++ drivers/net/ice/base/ice_flex_pipe.c | 7 +++++ drivers/net/ice/base/ice_type.h | 2 ++ drivers/net/ice/base/ice_vlan_mode.c | 44 +++++++++++++++++++++++++++ drivers/net/ice/base/ice_vlan_mode.h | 32 +++++++++++++++++++ drivers/net/ice/base/meson.build | 1 + 8 files changed, 153 insertions(+) create mode 100644 drivers/net/ice/base/ice_vlan_mode.c create mode 100644 drivers/net/ice/base/ice_vlan_mode.h diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index e69691427a..ff0e712d7a 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -227,6 +227,27 @@ struct ice_aqc_get_sw_cfg_resp_elem { #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) }; +/* Set Port parameters, (direct, 0x0203) */ +struct ice_aqc_set_port_params { + __le16 cmd_flags; +#define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0) +#define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1) +#define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) + __le16 bad_frame_vsi; +#define ICE_AQC_SET_P_PARAMS_VSI_S 0 +#define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S) +#define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15) + __le16 swid; +#define ICE_AQC_SET_P_PARAMS_SWID_S 0 +#define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S) +#define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8 +#define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \ + (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S) +#define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14) +#define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15) + u8 reserved[10]; +}; + /* These resource type defines are used for all switch resource * commands where a resource type is required, such as: * Get Resource Allocation command (indirect 0x0204) @@ -2709,6 +2730,7 @@ struct ice_aq_desc { struct ice_aqc_sff_eeprom read_write_sff_param; struct ice_aqc_set_port_id_led set_port_id_led; struct ice_aqc_get_sw_cfg get_sw_conf; + struct ice_aqc_set_port_params set_port_params; struct ice_aqc_sw_rules sw_rules; struct ice_aqc_storm_cfg storm_conf; struct ice_aqc_add_get_recipe add_get_recipe; @@ -2872,6 +2894,7 @@ enum ice_adminq_opc { /* internal switch commands */ ice_aqc_opc_get_sw_cfg = 0x0200, + ice_aqc_opc_set_port_params = 0x0203, /* Alloc/Free/Get Resources */ ice_aqc_opc_get_res_alloc = 0x0204, diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index ca764b2566..16dc474425 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -830,6 +830,9 @@ enum ice_status ice_init_hw(struct ice_hw *hw) if (status) goto err_unroll_fltr_mgmt_struct; ice_init_lock(&hw->tnl_lock); + + ice_init_vlan_mode_ops(hw); + return ICE_SUCCESS; err_unroll_fltr_mgmt_struct: @@ -2387,6 +2390,43 @@ void ice_clear_pxe_mode(struct ice_hw *hw) ice_aq_clear_pxe_mode(hw); } +/** + * ice_aq_set_port_params - set physical port parameters. + * @pi: pointer to the port info struct + * @bad_frame_vsi: defines the VSI to which bad frames are forwarded + * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI + * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded + * @double_vlan: if set double VLAN is enabled + * @cd: pointer to command details structure or NULL + * + * Set Physical port parameters (0x0203) + */ +enum ice_status +ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, + bool save_bad_pac, bool pad_short_pac, bool double_vlan, + struct ice_sq_cd *cd) + +{ + struct ice_aqc_set_port_params *cmd; + struct ice_hw *hw = pi->hw; + struct ice_aq_desc desc; + u16 cmd_flags = 0; + + cmd = &desc.params.set_port_params; + + ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); + cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); + if (save_bad_pac) + cmd_flags |= ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS; + if (pad_short_pac) + cmd_flags |= ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS; + if (double_vlan) + cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; + cmd->cmd_flags = CPU_TO_LE16(cmd_flags); + + return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); +} + /** * ice_get_link_speed_based_on_phy_type - returns link speed * @phy_type_low: lower part of phy_type diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index 8c16c7a024..765dc3054f 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -123,6 +123,10 @@ enum ice_status ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, struct ice_sq_cd *cd); enum ice_status +ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, + bool save_bad_pac, bool pad_short_pac, bool double_vlan, + struct ice_sq_cd *cd); +enum ice_status ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, struct ice_aqc_get_phy_caps_data *caps, struct ice_sq_cd *cd); diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 7594df1696..0812135cf5 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -1006,6 +1006,13 @@ ice_dwnld_cfg_bufs(struct ice_hw *hw, struct ice_buf *bufs, u32 count) break; } + if (!status) { + status = ice_set_vlan_mode(hw); + if (status) + ice_debug(hw, ICE_DBG_PKG, "Failed to set VLAN mode: err %d\n", + status); + } + ice_release_global_cfg_lock(hw); return status; diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 984dca6358..7790ee2e54 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -57,6 +57,7 @@ #include "ice_lan_tx_rx.h" #include "ice_flex_type.h" #include "ice_protocol_type.h" +#include "ice_vlan_mode.h" /** * ice_is_pow2 - check if integer value is a power of 2 @@ -990,6 +991,7 @@ struct ice_hw { ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX); struct ice_lock rss_locks; /* protect RSS configuration */ struct LIST_HEAD_TYPE rss_list_head; + struct ice_vlan_mode_ops vlan_mode_ops; }; /* Statistics collected by each port, VSI, VEB, and S-channel */ diff --git a/drivers/net/ice/base/ice_vlan_mode.c b/drivers/net/ice/base/ice_vlan_mode.c new file mode 100644 index 0000000000..603de74e25 --- /dev/null +++ b/drivers/net/ice/base/ice_vlan_mode.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2001-2020 Intel Corporation + */ + +#include "ice_vlan_mode.h" +#include "ice_common.h" + +/** + * ice_set_svm - set single VLAN mode + * @hw: pointer to the HW structure + */ +static enum ice_status ice_set_svm_dflt(struct ice_hw *hw) +{ + ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); + + return ice_aq_set_port_params(hw->port_info, 0, false, false, false, NULL); +} + +/** + * ice_init_vlan_mode_ops - initialize VLAN mode configuration ops + * @hw: pointer to the HW structure + */ +void ice_init_vlan_mode_ops(struct ice_hw *hw) +{ + hw->vlan_mode_ops.set_dvm = NULL; + hw->vlan_mode_ops.set_svm = ice_set_svm_dflt; +} + +/** + * ice_set_vlan_mode + * @hw: pointer to the HW structure + */ +enum ice_status ice_set_vlan_mode(struct ice_hw *hw) +{ + enum ice_status status = ICE_ERR_NOT_IMPL; + + if (hw->vlan_mode_ops.set_dvm) + status = hw->vlan_mode_ops.set_dvm(hw); + + if (status) + return hw->vlan_mode_ops.set_svm(hw); + + return ICE_SUCCESS; +} diff --git a/drivers/net/ice/base/ice_vlan_mode.h b/drivers/net/ice/base/ice_vlan_mode.h new file mode 100644 index 0000000000..1b9db4d36f --- /dev/null +++ b/drivers/net/ice/base/ice_vlan_mode.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2001-2020 Intel Corporation + */ + +#ifndef _ICE_VLAN_MODE_H_ +#define _ICE_VLAN_MODE_H_ + +struct ice_hw; + +enum ice_status ice_set_vlan_mode(struct ice_hw *hw); +void ice_init_vlan_mode_ops(struct ice_hw *hw); + +/* This structure defines the VLAN mode configuration interface. It is used to set the VLAN mode. + * + * Note: These operations will be called while the global configuration lock is held. + * + * enum ice_status (*set_svm)(struct ice_hw *hw); + * This function is called when the DDP and/or Firmware don't support double VLAN mode (DVM) or + * if the set_dvm op is not implemented and/or returns failure. It will set the device in + * single VLAN mode (SVM). + * + * enum ice_status (*set_dvm)(struct ice_hw *hw); + * This function is called when the DDP and Firmware support double VLAN mode (DVM). It should + * be implemented to set double VLAN mode. If it fails or remains unimplemented, set_svm will + * be called as a fallback plan. + */ +struct ice_vlan_mode_ops { + enum ice_status (*set_svm)(struct ice_hw *hw); + enum ice_status (*set_dvm)(struct ice_hw *hw); +}; + +#endif /* _ICE_VLAN_MODE_H */ diff --git a/drivers/net/ice/base/meson.build b/drivers/net/ice/base/meson.build index 22963ce31d..ad5e5da25b 100644 --- a/drivers/net/ice/base/meson.build +++ b/drivers/net/ice/base/meson.build @@ -13,6 +13,7 @@ sources = [ 'ice_fdir.c', 'ice_acl.c', 'ice_acl_ctrl.c', + 'ice_vlan_mode.c', ] error_cflags = ['-Wno-unused-value', From patchwork Tue Dec 15 06:05:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85172 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 333EAA09E9; Tue, 15 Dec 2020 07:06:55 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7BB46CA41; Tue, 15 Dec 2020 07:01:54 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 09192C9D2 for ; Tue, 15 Dec 2020 07:01:50 +0100 (CET) IronPort-SDR: x15Z/Rd5K9f66PF+hKwWnA860c+XcgFFbNUgvvM01qi/C7M3TIWaabAqkjjuS6N1b8oAnG5qrn BKQErpmvxsJQ== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200278" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200278" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:50 -0800 IronPort-SDR: gPh08kjxGbUc0YGd1PbhkizZDuf/FLhuMvskGvpYOBf1/jQRGvb3ExqwxyLUL6vTHUbRpK2CnJ mVZKhBxYcx2Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723573" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:48 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Zhirun Yan Date: Tue, 15 Dec 2020 14:05:07 +0800 Message-Id: <20201215060519.302145-16-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 15/27] net/ice/base: support VXLAN VNI field in FDIR X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Enable VXLAN VNI field in FDIR. Signed-off-by: Zhirun Yan Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_fdir.c | 43 +++++++++++++++++++++++++++++++++ drivers/net/ice/base/ice_fdir.h | 8 ++++++ drivers/net/ice/base/ice_flow.c | 21 ++++++++++++++++ drivers/net/ice/base/ice_flow.h | 6 +++++ drivers/net/ice/base/ice_type.h | 1 + 5 files changed, 79 insertions(+) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index aeff7af55d..cccbcf5e7f 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -42,6 +42,21 @@ static const u8 ice_fdir_ipv4_pkt[] = { 0x00, 0x00 }; +static const u8 ice_fdir_udp4_vxlan_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x4e, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, + 0x45, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x40, 0x00, + 0x40, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, +}; + static const u8 ice_fdir_udp4_gtpu4_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, @@ -614,6 +629,11 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = { sizeof(ice_fdir_non_ip_l2_pkt), ice_fdir_non_ip_l2_pkt, sizeof(ice_fdir_non_ip_l2_pkt), ice_fdir_non_ip_l2_pkt, }, + { + ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN, + sizeof(ice_fdir_udp4_vxlan_pkt), ice_fdir_udp4_vxlan_pkt, + sizeof(ice_fdir_udp4_vxlan_pkt), ice_fdir_udp4_vxlan_pkt, + }, { ICE_FLTR_PTYPE_NONF_IPV6_TCP, sizeof(ice_fdir_tcpv6_pkt), ice_fdir_tcpv6_pkt, @@ -1102,6 +1122,29 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, input->ip.v4.proto); ice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac); break; + case ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN: + ice_pkt_insert_mac_addr(pkt, input->ext_data_outer.dst_mac); + ice_pkt_insert_mac_addr(pkt + ETH_ALEN, input->ext_data_outer.src_mac); + ice_pkt_insert_u32(pkt, ICE_IPV4_SRC_ADDR_OFFSET, + input->ip_outer.v4.dst_ip); + ice_pkt_insert_u32(pkt, ICE_IPV4_DST_ADDR_OFFSET, + input->ip_outer.v4.src_ip); + ice_pkt_insert_u8(pkt, ICE_IPV4_TOS_OFFSET, input->ip_outer.v4.tos); + ice_pkt_insert_u32(pkt, ICE_IPV4_VXLAN_VNI_OFFSET, + input->vxlan_data.vni); + ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET, + input->ip.v4.src_ip); + ice_pkt_insert_u16(loc, ICE_IPV4_UDP_DST_PORT_OFFSET, + input->ip.v4.src_port); + ice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET, + input->ip.v4.dst_ip); + ice_pkt_insert_u16(loc, ICE_IPV4_UDP_SRC_PORT_OFFSET, + input->ip.v4.dst_port); + ice_pkt_insert_u8(loc, ICE_IPV4_TOS_OFFSET, input->ip.v4.tos); + ice_pkt_insert_u8(loc, ICE_IPV4_TTL_OFFSET, input->ip.v4.ttl); + ice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac); + ice_pkt_insert_mac_addr(loc + ETH_ALEN, input->ext_data.src_mac); + break; case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER: ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET, input->ip.v4.src_ip); diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index d363de385d..1c8de8956d 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -55,6 +55,7 @@ #define ICE_IPV6_AH_SPI_OFFSET 58 #define ICE_IPV4_NAT_T_ESP_SPI_OFFSET 42 #define ICE_IPV6_NAT_T_ESP_SPI_OFFSET 62 +#define ICE_IPV4_VXLAN_VNI_OFFSET 45 #define ICE_FDIR_MAX_FLTRS 16384 @@ -163,6 +164,10 @@ struct ice_fdir_l2tpv3 { __be32 session_id; }; +struct ice_fdir_udp_vxlan { + __be32 vni; /* 8 bits reserved, always be zero */ +}; + struct ice_fdir_extra { u8 dst_mac[ETH_ALEN]; /* dest MAC address */ u8 src_mac[ETH_ALEN]; /* src MAC address */ @@ -190,6 +195,9 @@ struct ice_fdir_fltr { struct ice_fdir_extra ext_data_outer; struct ice_fdir_extra ext_mask_outer; + struct ice_fdir_udp_vxlan vxlan_data; + struct ice_fdir_udp_vxlan vxlan_mask; + struct ice_fdir_udp_gtp gtpu_data; struct ice_fdir_udp_gtp gtpu_mask; diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index f667b8ef7d..bce90d9335 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -30,6 +30,7 @@ #define ICE_FLOW_FLD_SZ_ESP_SPI 4 #define ICE_FLOW_FLD_SZ_AH_SPI 4 #define ICE_FLOW_FLD_SZ_NAT_T_ESP_SPI 4 +#define ICE_FLOW_FLD_SZ_VXLAN_VNI 4 /* Describe properties of a protocol header field */ struct ice_flow_field_info { @@ -189,6 +190,9 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = { /* ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_NAT_T_ESP, 8, ICE_FLOW_FLD_SZ_NAT_T_ESP_SPI), + /* ICE_FLOW_FIELD_IDX_VXLAN_VNI */ + ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_VXLAN, 12, + ICE_FLOW_FLD_SZ_VXLAN_VNI), }; /* Bitmaps indicating relevant packet types for a particular protocol header @@ -456,6 +460,18 @@ static const u32 ice_ptypes_gtpc[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; +/* Packet types for VXLAN with VNI */ +static const u32 ice_ptypes_vxlan_vni[] = { + 0x00000000, 0xBFBFF800, 0x00EFDFDF, 0xFEFDE000, + 0x03BF7F7E, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + /* Packet types for GTPC with TEID */ static const u32 ice_ptypes_gtpc_tid[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -974,6 +990,10 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params) src = (const ice_bitmap_t *)ice_ptypes_nat_t_esp; ice_and_bitmap(params->ptypes, params->ptypes, src, ICE_FLOW_PTYPE_MAX); + } else if (hdrs & ICE_FLOW_SEG_HDR_VXLAN) { + src = (const ice_bitmap_t *)ice_ptypes_vxlan_vni; + ice_and_bitmap(params->ptypes, params->ptypes, + src, ICE_FLOW_PTYPE_MAX); } if (hdrs & ICE_FLOW_SEG_HDR_PFCP) { @@ -1144,6 +1164,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, case ICE_FLOW_FIELD_IDX_SCTP_DST_PORT: prot_id = ICE_PROT_SCTP_IL; break; + case ICE_FLOW_FIELD_IDX_VXLAN_VNI: case ICE_FLOW_FIELD_IDX_GTPC_TEID: case ICE_FLOW_FIELD_IDX_GTPU_IP_TEID: case ICE_FLOW_FIELD_IDX_GTPU_UP_TEID: diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h index 2a9ae66454..23a98cfe89 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -72,6 +72,9 @@ #define ICE_HASH_SCTP_IPV6_PRE64 \ (ICE_FLOW_HASH_IPV6_PRE64 | ICE_FLOW_HASH_SCTP_PORT) +#define ICE_FLOW_HASH_VXLAN_VNI \ + (BIT_ULL(ICE_FLOW_FIELD_IDX_VXLAN_VNI)) + #define ICE_FLOW_HASH_GTP_TEID \ (BIT_ULL(ICE_FLOW_FIELD_IDX_GTPC_TEID)) @@ -179,6 +182,7 @@ enum ice_flow_seg_hdr { ICE_FLOW_SEG_HDR_NAT_T_ESP = 0x00400000, ICE_FLOW_SEG_HDR_ETH_NON_IP = 0x00800000, ICE_FLOW_SEG_HDR_GTPU_NON_IP = 0x01000000, + ICE_FLOW_SEG_HDR_VXLAN = 0x02000000, /* The following is an additive bit for ICE_FLOW_SEG_HDR_IPV4 and * ICE_FLOW_SEG_HDR_IPV6 which include the IPV4 other PTYPEs */ @@ -267,6 +271,8 @@ enum ice_flow_field { ICE_FLOW_FIELD_IDX_AH_SPI, /* NAT_T ESP */ ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI, + /* VXLAN VNI */ + ICE_FLOW_FIELD_IDX_VXLAN_VNI, /* The total number of enums must not exceed 64 */ ICE_FLOW_FIELD_IDX_MAX }; diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 7790ee2e54..4552288b85 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -329,6 +329,7 @@ enum ice_fltr_ptype { ICE_FLTR_PTYPE_NONF_IPV6_TCP, ICE_FLTR_PTYPE_NONF_IPV6_SCTP, ICE_FLTR_PTYPE_NONF_IPV6_OTHER, + ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN, ICE_FLTR_PTYPE_MAX, }; From patchwork Tue Dec 15 06:05:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85173 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B134DA09E9; Tue, 15 Dec 2020 07:07:19 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 237D4CA4E; Tue, 15 Dec 2020 07:01:56 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 50AADCA36 for ; Tue, 15 Dec 2020 07:01:52 +0100 (CET) IronPort-SDR: 1iNdYhwtsds5MME9rApG0O9Vota1BPoT4RuYT1tkzkQN7fYj3USviuszb0qLX+aDAW5CYJ8257 lYCYhzr++ixQ== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200283" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200283" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:51 -0800 IronPort-SDR: HqxTYMm5D7DIdlHiYSdJPcDW5Aw0PkyPiPxKiKaZJoYF0+J+jeMerCyFC1B/0IimmctTjesNpU CH4/aZEWhG/Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723598" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:50 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , stable@dpdkr.org, Xiao Zhang Date: Tue, 15 Dec 2020 14:05:08 +0800 Message-Id: <20201215060519.302145-17-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 16/27] net/ice/base: fix incorrect tunnel destroy X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The tcam information in AQ command buffer is not correct when destroy tunnel entries. The tcam count was always ONE even destroy multiple entries, and the offset of tcam memory was also incorrect. This patch is to fix this issue. Fixes: 884efe3ca1f3 ("net/ice/base: add VXLAN/generic tunnel management") Cc: stable@dpdkr.org Signed-off-by: Xiao Zhang Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flex_pipe.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 0812135cf5..6c7f83899d 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -2163,7 +2163,7 @@ enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 port, bool all) u16 count = 0; u16 index; u16 size; - u16 i; + u16 i, j; ice_acquire_lock(&hw->tnl_lock); @@ -2203,30 +2203,31 @@ enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 port, bool all) size); if (!sect_rx) goto ice_destroy_tunnel_err; - sect_rx->count = CPU_TO_LE16(1); + sect_rx->count = CPU_TO_LE16(count); sect_tx = (struct ice_boost_tcam_section *) ice_pkg_buf_alloc_section(bld, ICE_SID_TXPARSER_BOOST_TCAM, size); if (!sect_tx) goto ice_destroy_tunnel_err; - sect_tx->count = CPU_TO_LE16(1); + sect_tx->count = CPU_TO_LE16(count); /* copy original boost entry to update package buffer, one copy to Rx * section, another copy to the Tx section */ - for (i = 0; i < hw->tnl.count && i < ICE_TUNNEL_MAX_ENTRIES; i++) + for (i = 0, j = 0; i < hw->tnl.count && i < ICE_TUNNEL_MAX_ENTRIES; i++) if (hw->tnl.tbl[i].valid && hw->tnl.tbl[i].in_use && (all || hw->tnl.tbl[i].port == port)) { - ice_memcpy(sect_rx->tcam + i, + ice_memcpy(sect_rx->tcam + j, hw->tnl.tbl[i].boost_entry, sizeof(*sect_rx->tcam), ICE_NONDMA_TO_NONDMA); - ice_memcpy(sect_tx->tcam + i, + ice_memcpy(sect_tx->tcam + j, hw->tnl.tbl[i].boost_entry, sizeof(*sect_tx->tcam), ICE_NONDMA_TO_NONDMA); hw->tnl.tbl[i].marked = true; + j++; } status = ice_update_pkg(hw, ice_pkg_buf(bld), 1); From patchwork Tue Dec 15 06:05:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85174 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E6D9AA09E9; Tue, 15 Dec 2020 07:07:39 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 55FD6CA56; Tue, 15 Dec 2020 07:01:58 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id CF678CA4B for ; Tue, 15 Dec 2020 07:01:54 +0100 (CET) IronPort-SDR: lfPLxKggRNpmlL3bgabZfdmNTOvnYNWOpyxi5DnjBWGCWDzspn16wr9eeNQY3EHAN626KxgZYL Lvt1LEk7Ismg== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200290" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200290" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:54 -0800 IronPort-SDR: ZhnsVIEiNFmPxWjofoiZTZ96KDCoE25j3pHZku9bRRoS0hKWtehE3JIa+/efVbfj9wi2onYhpb h/7Cxh3S61Jw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723627" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:52 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Dan Nowlin , Brett Creeley , Jacob Keller Date: Tue, 15 Dec 2020 14:05:09 +0800 Message-Id: <20201215060519.302145-18-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 17/27] net/ice/base: add functionality to check if DVM is supported X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" If a driver wants to configure double VLAN mode (DVM) it needs to first check if the DDP supports DVM. To do this the driver needs to read the package metadata section via the upload section AQ (0x04C1). If the DDP doesn't support configuring double VLAN mode (DVM), then there is nothing to do regarding configuring the VLAN mode of the device. The set_svm() or set_dvm() ops should only be called if the current configuration supports configuring the VLAN mode of the device. Signed-off-by: Dan Nowlin Signed-off-by: Brett Creeley Suggested-by: Jacob Keller Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_bitops.h | 45 ++++++++++++++++ drivers/net/ice/base/ice_flex_pipe.c | 63 +++++++++++++++++++++- drivers/net/ice/base/ice_flex_pipe.h | 11 ++++ drivers/net/ice/base/ice_flex_type.h | 26 ++++++++++ drivers/net/ice/base/ice_vlan_mode.c | 78 ++++++++++++++++++++++++++++ 5 files changed, 221 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_bitops.h b/drivers/net/ice/base/ice_bitops.h index 39548967cc..b786bf7a18 100644 --- a/drivers/net/ice/base/ice_bitops.h +++ b/drivers/net/ice/base/ice_bitops.h @@ -449,4 +449,49 @@ ice_cmp_bitmap(ice_bitmap_t *bmp1, ice_bitmap_t *bmp2, u16 size) return true; } +/** + * ice_bitmap_from_array32 - copies u32 array source into bitmap destination + * @dst: the destination bitmap + * @src: the source u32 array + * @size: size of the bitmap (in bits) + * + * This function copies the src bitmap stored in an u32 array into the dst + * bitmap stored as an ice_bitmap_t. + */ +static inline void +ice_bitmap_from_array32(ice_bitmap_t *dst, u32 *src, u16 size) +{ + u32 remaining_bits, i; + +#define BITS_PER_U32 (sizeof(u32) * BITS_PER_BYTE) + /* clear bitmap so we only have to set when iterating */ + ice_zero_bitmap(dst, size); + + for (i = 0; i < (u32)(size / BITS_PER_U32); i++) { + u32 bit_offset = i * BITS_PER_U32; + u32 entry = src[i]; + u32 j; + + for (j = 0; j < BITS_PER_U32; j++) { + if (entry & BIT(j)) + ice_set_bit((u16)(j + bit_offset), dst); + } + } + + /* still need to check the leftover bits (i.e. if size isn't evenly + * divisible by BITS_PER_U32 + **/ + remaining_bits = size % BITS_PER_U32; + if (remaining_bits) { + u32 bit_offset = i * BITS_PER_U32; + u32 entry = src[i]; + u32 j; + + for (j = 0; j < remaining_bits; j++) { + if (entry & BIT(j)) + ice_set_bit((u16)(j + bit_offset), dst); + } + } +} + #endif /* _ICE_BITOPS_H_ */ diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 6c7f83899d..e511b50a00 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -807,6 +807,28 @@ ice_aq_download_pkg(struct ice_hw *hw, struct ice_buf_hdr *pkg_buf, return status; } +/** + * ice_aq_upload_section + * @hw: pointer to the hardware structure + * @pkg_buf: the package buffer which will receive the section + * @buf_size: the size of the package buffer + * @cd: pointer to command details structure or NULL + * + * Upload Section (0x0C41) + */ +enum ice_status +ice_aq_upload_section(struct ice_hw *hw, struct ice_buf_hdr *pkg_buf, + u16 buf_size, struct ice_sq_cd *cd) +{ + struct ice_aq_desc desc; + + ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); + ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_upload_section); + desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); + + return ice_aq_send_cmd(hw, &desc, pkg_buf, buf_size, cd); +} + /** * ice_aq_update_pkg * @hw: pointer to the hardware structure @@ -1800,7 +1822,7 @@ void ice_init_prof_result_bm(struct ice_hw *hw) * * Frees a package buffer */ -static void ice_pkg_buf_free(struct ice_hw *hw, struct ice_buf_build *bld) +void ice_pkg_buf_free(struct ice_hw *hw, struct ice_buf_build *bld) { ice_free(hw, bld); } @@ -1899,6 +1921,43 @@ ice_pkg_buf_alloc_section(struct ice_buf_build *bld, u32 type, u16 size) return NULL; } +/** + * ice_pkg_buf_alloc_single_section + * @hw: pointer to the HW structure + * @type: the section type value + * @size: the size of the section to reserve (in bytes) + * @section: returns pointer to the section + * + * Allocates a package buffer with a single section. + * Note: all package contents must be in Little Endian form. + */ +struct ice_buf_build * +ice_pkg_buf_alloc_single_section(struct ice_hw *hw, u32 type, u16 size, + void **section) +{ + struct ice_buf_build *buf; + + if (!section) + return NULL; + + buf = ice_pkg_buf_alloc(hw); + if (!buf) + return NULL; + + if (ice_pkg_buf_reserve_section(buf, 1)) + goto ice_pkg_buf_alloc_single_section_err; + + *section = ice_pkg_buf_alloc_section(buf, type, size); + if (!*section) + goto ice_pkg_buf_alloc_single_section_err; + + return buf; + +ice_pkg_buf_alloc_single_section_err: + ice_pkg_buf_free(hw, buf); + return NULL; +} + /** * ice_pkg_buf_get_active_sections * @bld: pointer to pkg build (allocated by ice_pkg_buf_alloc()) @@ -1926,7 +1985,7 @@ static u16 ice_pkg_buf_get_active_sections(struct ice_buf_build *bld) * * Return a pointer to the buffer's header */ -static struct ice_buf *ice_pkg_buf(struct ice_buf_build *bld) +struct ice_buf *ice_pkg_buf(struct ice_buf_build *bld) { if (!bld) return NULL; diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h index 214c7a2837..d4679cc940 100644 --- a/drivers/net/ice/base/ice_flex_pipe.h +++ b/drivers/net/ice/base/ice_flex_pipe.h @@ -38,6 +38,12 @@ ice_init_prof_result_bm(struct ice_hw *hw); enum ice_status ice_get_sw_fv_list(struct ice_hw *hw, u8 *prot_ids, u16 ids_cnt, ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list); +enum ice_status +ice_pkg_buf_unreserve_section(struct ice_buf_build *bld, u16 count); +u16 ice_pkg_buf_get_free_space(struct ice_buf_build *bld); +enum ice_status +ice_aq_upload_section(struct ice_hw *hw, struct ice_buf_hdr *pkg_buf, + u16 buf_size, struct ice_sq_cd *cd); bool ice_get_open_tunnel_port(struct ice_hw *hw, enum ice_tunnel_type type, u16 *port); @@ -75,6 +81,11 @@ void ice_clear_hw_tbls(struct ice_hw *hw); void ice_free_hw_tbls(struct ice_hw *hw); enum ice_status ice_rem_prof(struct ice_hw *hw, enum ice_block blk, u64 id); +struct ice_buf_build * +ice_pkg_buf_alloc_single_section(struct ice_hw *hw, u32 type, u16 size, + void **section); +struct ice_buf *ice_pkg_buf(struct ice_buf_build *bld); +void ice_pkg_buf_free(struct ice_hw *hw, struct ice_buf_build *bld); enum ice_status ice_set_key(u8 *key, u16 size, u8 *val, u8 *upd, u8 *dc, u8 *nm, u16 off, diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h index 7d0204fa50..08db7f2c9a 100644 --- a/drivers/net/ice/base/ice_flex_type.h +++ b/drivers/net/ice/base/ice_flex_type.h @@ -787,4 +787,30 @@ enum ice_prof_type { ICE_PROF_TUN_ALL = 0xE, ICE_PROF_ALL = 0xFF, }; + +/* Number of bits/bytes contained in meta init entry. Note, this should be a + * multiple of 32 bits. + */ +#define ICE_META_INIT_BITS 192 +#define ICE_META_INIT_DW_CNT (ICE_META_INIT_BITS / (sizeof(__le32) * \ + BITS_PER_BYTE)) + +/* The meta init Flag field starts at this bit */ +#define ICE_META_FLAGS_ST 123 + +/* The entry and bit to check for Double VLAN Mode (DVM) support */ +#define ICE_META_VLAN_MODE_ENTRY 0 +#define ICE_META_FLAG_VLAN_MODE 60 +#define ICE_META_VLAN_MODE_BIT (ICE_META_FLAGS_ST + \ + ICE_META_FLAG_VLAN_MODE) + +struct ice_meta_init_entry { + __le32 bm[ICE_META_INIT_DW_CNT]; +}; + +struct ice_meta_init_section { + __le16 count; + __le16 offset; + struct ice_meta_init_entry entry[1]; +}; #endif /* _ICE_FLEX_TYPE_H_ */ diff --git a/drivers/net/ice/base/ice_vlan_mode.c b/drivers/net/ice/base/ice_vlan_mode.c index 603de74e25..363354ff3f 100644 --- a/drivers/net/ice/base/ice_vlan_mode.c +++ b/drivers/net/ice/base/ice_vlan_mode.c @@ -5,6 +5,81 @@ #include "ice_vlan_mode.h" #include "ice_common.h" +/** + * ice_pkg_supports_dvm - determine if DDP supports Double VLAN mode (DVM) + * @hw: pointer to the HW struct + * @dvm: output variable to determine if DDP supports DVM(true) or SVM(false) + */ +static enum ice_status +ice_pkg_get_supported_vlan_mode(struct ice_hw *hw, bool *dvm) +{ + u16 meta_init_size = sizeof(struct ice_meta_init_section); + struct ice_meta_init_section *sect; + struct ice_buf_build *bld; + enum ice_status status; + + /* if anything fails, we assume there is no DVM support */ + *dvm = false; + + bld = ice_pkg_buf_alloc_single_section(hw, + ICE_SID_RXPARSER_METADATA_INIT, + meta_init_size, (void **)§); + if (!bld) + return ICE_ERR_NO_MEMORY; + + /* only need to read a single section */ + sect->count = CPU_TO_LE16(1); + sect->offset = CPU_TO_LE16(ICE_META_VLAN_MODE_ENTRY); + + status = ice_aq_upload_section(hw, + (struct ice_buf_hdr *)ice_pkg_buf(bld), + ICE_PKG_BUF_SIZE, NULL); + if (!status) { + ice_declare_bitmap(entry, ICE_META_INIT_BITS); + u32 arr[ICE_META_INIT_DW_CNT]; + u16 i; + + /* convert to host bitmap format */ + for (i = 0; i < ICE_META_INIT_DW_CNT; i++) + arr[i] = LE32_TO_CPU(sect->entry[0].bm[i]); + + ice_bitmap_from_array32(entry, arr, (u16)ICE_META_INIT_BITS); + + /* check if DVM is supported */ + *dvm = ice_is_bit_set(entry, ICE_META_VLAN_MODE_BIT); + } + + ice_pkg_buf_free(hw, bld); + + return status; +} + +/** + * ice_is_dvm_supported - check if double VLAN mode is supported based on DDP + * @hw: pointer to the hardware structure + * + * Returns true if DVM is supported and false if only SVM is supported. This + * function should only be called while the global config lock is held and after + * the package has been successfully downloaded. + */ +static bool ice_is_dvm_supported(struct ice_hw *hw) +{ + enum ice_status status; + bool pkg_supports_dvm; + + status = ice_pkg_get_supported_vlan_mode(hw, &pkg_supports_dvm); + if (status) { + ice_debug(hw, ICE_DBG_PKG, "Failed to get supported VLAN mode, err %d\n", + status); + return false; + } + + if (!pkg_supports_dvm) + return false; + + return true; +} + /** * ice_set_svm - set single VLAN mode * @hw: pointer to the HW structure @@ -34,6 +109,9 @@ enum ice_status ice_set_vlan_mode(struct ice_hw *hw) { enum ice_status status = ICE_ERR_NOT_IMPL; + if (!ice_is_dvm_supported(hw)) + return ICE_SUCCESS; + if (hw->vlan_mode_ops.set_dvm) status = hw->vlan_mode_ops.set_dvm(hw); From patchwork Tue Dec 15 06:05:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85175 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 79625A09E9; Tue, 15 Dec 2020 07:07:58 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 00E5BCA60; Tue, 15 Dec 2020 07:02:00 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id BA292CA4B for ; Tue, 15 Dec 2020 07:01:56 +0100 (CET) IronPort-SDR: A8KU1t21YwAuv+fUnViA3jFPhRv2DNWIHe4HkpJUvnWmZCGQatZ4I2U+w1Z9TpY7NTv9Z7GTKS vzT1Tp+8C2nA== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200294" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200294" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:56 -0800 IronPort-SDR: cs6+Jt3s9Ich2uWzsdIDeoODJQVwmYY2Ni6rtu3ZgxqZKUKxWK0b/LuloVYgg93nEZq05IOQ1I 0EWukT9LDXPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723647" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:54 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Chinh T Cao Date: Tue, 15 Dec 2020 14:05:10 +0800 Message-Id: <20201215060519.302145-19-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 18/27] net/ice/base: resend some AQ commands when EBUSY X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Retry sending some AQ commands, as result of EBUSY AQ error. This change follows the latest guidelines from HW. It is better to retry the same AQ command several times, as the result of EBUSY, instead of returning error to the caller right away. Signed-off-by: Chinh T Cao Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_common.c | 87 ++++++++++++++++++++++++++++- drivers/net/ice/base/ice_common.h | 3 + drivers/net/ice/base/ice_controlq.c | 2 +- 3 files changed, 89 insertions(+), 3 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 16dc474425..8c6503afab 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -1344,6 +1344,89 @@ ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index) /* FW Admin Queue command wrappers */ +/** + * ice_should_retry_sq_send_cmd + * @opcode: AQ opcode + * + * Decide if we should retry the send command routine for the ATQ, depending + * on the opcode. + */ +static bool ice_should_retry_sq_send_cmd(u16 opcode) +{ + switch (opcode) { + case ice_aqc_opc_get_link_topo: + case ice_aqc_opc_lldp_stop: + case ice_aqc_opc_lldp_start: + case ice_aqc_opc_lldp_filter_ctrl: + return true; + } + + return false; +} + +/** + * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) + * @hw: pointer to the HW struct + * @cq: pointer to the specific Control queue + * @desc: prefilled descriptor describing the command + * @buf: buffer to use for indirect commands (or NULL for direct commands) + * @buf_size: size of buffer for indirect commands (or 0 for direct commands) + * @cd: pointer to command details structure + * + * Retry sending the FW Admin Queue command, multiple times, to the FW Admin + * Queue if the EBUSY AQ error is returned. + */ +static enum ice_status +ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, + struct ice_aq_desc *desc, void *buf, u16 buf_size, + struct ice_sq_cd *cd) +{ + struct ice_aq_desc desc_cpy; + enum ice_status status; + bool is_cmd_for_retry; + u8 *buf_cpy = NULL; + u8 idx = 0; + u16 opcode; + + opcode = LE16_TO_CPU(desc->opcode); + is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); + ice_memset(&desc_cpy, 0, sizeof(desc_cpy), ICE_NONDMA_MEM); + + if (is_cmd_for_retry) { + if (buf) { + buf_cpy = (u8 *)ice_malloc(hw, buf_size); + if (!buf_cpy) + return ICE_ERR_NO_MEMORY; + } + + ice_memcpy(&desc_cpy, desc, sizeof(desc_cpy), + ICE_NONDMA_TO_NONDMA); + } + + do { + status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); + + if (!is_cmd_for_retry || status == ICE_SUCCESS || + hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) + break; + + if (buf_cpy) + ice_memcpy(buf, buf_cpy, buf_size, + ICE_NONDMA_TO_NONDMA); + + ice_memcpy(desc, &desc_cpy, sizeof(desc_cpy), + ICE_NONDMA_TO_NONDMA); + + ice_msec_delay(ICE_SQ_SEND_DELAY_TIME_MS, false); + + } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); + + if (buf_cpy) + ice_free(hw, buf_cpy); + + return status; +} + /** * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue * @hw: pointer to the HW struct @@ -1380,7 +1463,7 @@ ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, return status; } - return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); + return ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); } /** @@ -2356,7 +2439,7 @@ ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); cmd->flags = flags; - ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_DMA); + ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); } diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index 765dc3054f..4f534a7f0b 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -11,6 +11,9 @@ #include "ice_switch.h" #include "ice_fdir.h" +#define ICE_SQ_SEND_DELAY_TIME_MS 10 +#define ICE_SQ_SEND_MAX_EXECUTE 3 + enum ice_fw_modes { ICE_FW_MODE_NORMAL, ICE_FW_MODE_DBG, diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c index 111288184b..4c4f92552b 100644 --- a/drivers/net/ice/base/ice_controlq.c +++ b/drivers/net/ice/base/ice_controlq.c @@ -1053,7 +1053,7 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq, * ice_sq_send_cmd - send command to Control Queue (ATQ) * @hw: pointer to the HW struct * @cq: pointer to the specific Control queue - * @desc: prefilled descriptor describing the command (non DMA mem) + * @desc: prefilled descriptor describing the command * @buf: buffer to use for indirect commands (or NULL for direct commands) * @buf_size: size of buffer for indirect commands (or 0 for direct commands) * @cd: pointer to command details structure From patchwork Tue Dec 15 06:05:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85176 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 54E89A09E9; Tue, 15 Dec 2020 07:08:16 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7CEE1CA64; Tue, 15 Dec 2020 07:02:01 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id D51B5CA4B for ; Tue, 15 Dec 2020 07:01:57 +0100 (CET) IronPort-SDR: Pu+fqEqeA7GJLcPllu6K8m4O10MUvUc0u3Rhic/PzXWjqggr+qyHpa4U9pVcivSlTmtOVoznT1 zwDvb8ZO51xA== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200298" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200298" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:57 -0800 IronPort-SDR: FG7goahuWOZlx60VrzsNe5cHBz+GKT4eMSOmUmLCIIDfTuGmmvw0eL1GaPsGChUps6vf/Cc9VT /hW1+w/nE1mg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723669" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:56 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Tony Nguyen Date: Tue, 15 Dec 2020 14:05:11 +0800 Message-Id: <20201215060519.302145-20-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 19/27] net/ice/base: change get PHY capability error level X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" As the user may be expected to take action on this issue, change the message to a warning so that the message is more easily accessible than a debug. Also, add the error code to further aide in identifying the problem. Signed-off-by: Tony Nguyen Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 8c6503afab..5c59dd63cb 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -782,7 +782,8 @@ enum ice_status ice_init_hw(struct ice_hw *hw) ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); ice_free(hw, pcaps); if (status) - ice_debug(hw, ICE_DBG_PHY, "Get PHY capabilities failed, continuing anyway\n"); + ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n", + status); /* Initialize port_info struct with link information */ status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); From patchwork Tue Dec 15 06:05:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85177 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D161EA09E9; Tue, 15 Dec 2020 07:08:33 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1033ECA74; Tue, 15 Dec 2020 07:02:03 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 08D4BCA5C for ; Tue, 15 Dec 2020 07:02:00 +0100 (CET) IronPort-SDR: TjHfsYZo/0mrMvNg5rjy/gDHN8K6uCRjJdRuQvwmwIyzy7RnClcmIQ9jTN8x3UXeiGIXOo9jmL NM8awgfSIdrg== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200301" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200301" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:01:59 -0800 IronPort-SDR: 7Ee+P8a8kyEYxD2R75AOE51zo2IMLUoq7oNp9KWI8bCjT3cISuR6fkli4tcqijcfTnMRMPekbR Mm/GfAMuAu7A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723690" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:57 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Victor Raj Date: Tue, 15 Dec 2020 14:05:12 +0800 Message-Id: <20201215060519.302145-21-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 20/27] net/ice/base: modify recursive way of adding nodes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove the recursive way of adding the nodes to the layer in order to reduce the stack usage. Instead the algorithm is modified to use a while loop. The previous code was scanning recursively the nodes horizontally. The total stack consumption will be based on number of nodes present on that layer. In some cases it can consume more stack. Signed-off-by: Victor Raj Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_sched.c | 124 +++++++++++++++++-------------- 1 file changed, 70 insertions(+), 54 deletions(-) diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index ac48bbe279..b75a44f54c 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -965,7 +965,7 @@ ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node, } /** - * ice_sched_add_nodes_to_layer - Add nodes to a given layer + * ice_sched_add_nodes_to_hw_layer - Add nodes to hw layer * @pi: port information structure * @tc_node: pointer to TC node * @parent: pointer to parent node @@ -974,82 +974,98 @@ ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node, * @first_node_teid: pointer to the first node TEID * @num_nodes_added: pointer to number of nodes added * - * This function add nodes to a given layer. + * Add nodes into specific hw layer. */ static enum ice_status -ice_sched_add_nodes_to_layer(struct ice_port_info *pi, - struct ice_sched_node *tc_node, - struct ice_sched_node *parent, u8 layer, - u16 num_nodes, u32 *first_node_teid, - u16 *num_nodes_added) +ice_sched_add_nodes_to_hw_layer(struct ice_port_info *pi, + struct ice_sched_node *tc_node, + struct ice_sched_node *parent, u8 layer, + u16 num_nodes, u32 *first_node_teid, + u16 *num_nodes_added) { - u32 *first_teid_ptr = first_node_teid; - u16 new_num_nodes, max_child_nodes; - enum ice_status status = ICE_SUCCESS; - struct ice_hw *hw = pi->hw; - u16 num_added = 0; - u32 temp; + u16 max_child_nodes; *num_nodes_added = 0; if (!num_nodes) - return status; + return ICE_SUCCESS; - if (!parent || layer < hw->sw_entry_point_layer) + if (!parent || layer < pi->hw->sw_entry_point_layer) return ICE_ERR_PARAM; /* max children per node per layer */ - max_child_nodes = hw->max_children[parent->tx_sched_layer]; + max_child_nodes = pi->hw->max_children[parent->tx_sched_layer]; - /* current number of children + required nodes exceed max children ? */ + /* current number of children + required nodes exceed max children */ if ((parent->num_children + num_nodes) > max_child_nodes) { /* Fail if the parent is a TC node */ if (parent == tc_node) return ICE_ERR_CFG; + return ICE_ERR_MAX_LIMIT; + } + + return ice_sched_add_elems(pi, tc_node, parent, layer, num_nodes, + num_nodes_added, first_node_teid); +} + +/** + * ice_sched_add_nodes_to_layer - Add nodes to a given layer + * @pi: port information structure + * @tc_node: pointer to TC node + * @parent: pointer to parent node + * @layer: layer number to add nodes + * @num_nodes: number of nodes to be added + * @first_node_teid: pointer to the first node TEID + * @num_nodes_added: pointer to number of nodes added + * + * This function add nodes to a given layer. + */ +static enum ice_status +ice_sched_add_nodes_to_layer(struct ice_port_info *pi, + struct ice_sched_node *tc_node, + struct ice_sched_node *parent, u8 layer, + u16 num_nodes, u32 *first_node_teid, + u16 *num_nodes_added) +{ + u32 *first_teid_ptr = first_node_teid; + u16 new_num_nodes = num_nodes; + enum ice_status status = ICE_SUCCESS; + *num_nodes_added = 0; + while (*num_nodes_added < num_nodes) { + u16 max_child_nodes, num_added = 0; + u32 temp; + + status = ice_sched_add_nodes_to_hw_layer(pi, tc_node, parent, + layer, new_num_nodes, + first_teid_ptr, + &num_added); + *num_nodes_added += num_added; + /* break if all the nodes are added successfully */ + if (status == ICE_SUCCESS && (*num_nodes_added == num_nodes)) + break; + /* break if the error is not max limit */ + if (status != ICE_SUCCESS && status != ICE_ERR_MAX_LIMIT) + break; + /* Exceeded the max children */ + max_child_nodes = pi->hw->max_children[parent->tx_sched_layer]; /* utilize all the spaces if the parent is not full */ if (parent->num_children < max_child_nodes) { new_num_nodes = max_child_nodes - parent->num_children; - /* this recursion is intentional, and wouldn't - * go more than 2 calls + } else { + /* This parent is full, try the next sibling */ + parent = parent->sibling; + /* Don't modify the first node TEID memory if the + * first node was added already in the above call. + * Instead send some temp memory for all other + * recursive calls. */ - status = ice_sched_add_nodes_to_layer(pi, tc_node, - parent, layer, - new_num_nodes, - first_node_teid, - &num_added); - if (status != ICE_SUCCESS) - return status; - - *num_nodes_added += num_added; - } - /* Don't modify the first node TEID memory if the first node was - * added already in the above call. Instead send some temp - * memory for all other recursive calls. - */ - if (num_added) - first_teid_ptr = &temp; - - new_num_nodes = num_nodes - num_added; - - /* This parent is full, try the next sibling */ - parent = parent->sibling; + if (num_added) + first_teid_ptr = &temp; - /* this recursion is intentional, for 1024 queues - * per VSI, it goes max of 16 iterations. - * 1024 / 8 = 128 layer 8 nodes - * 128 /8 = 16 (add 8 nodes per iteration) - */ - status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, - layer, new_num_nodes, - first_teid_ptr, - &num_added); - *num_nodes_added += num_added; - return status; + new_num_nodes = num_nodes - num_added; + } } - - status = ice_sched_add_elems(pi, tc_node, parent, layer, num_nodes, - num_nodes_added, first_node_teid); return status; } From patchwork Tue Dec 15 06:05:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85178 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 365A8A09E9; Tue, 15 Dec 2020 07:08:55 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E23F8C9FC; Tue, 15 Dec 2020 07:02:05 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id CB272CA68; Tue, 15 Dec 2020 07:02:01 +0100 (CET) IronPort-SDR: rRgnfsQ98DbOu0d9b5SRaLWIeEKrV/Z6kZ44mXi2rYlJZWaVOJcZNu16zWiFepWEUxsEkbuCNK 37rN9nxH3J+Q== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200306" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200306" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:02:01 -0800 IronPort-SDR: kvSb+EQ9IlKP9LM5ILBXd6Ft6bgsSEF1yvqQw5hU3Hgw+2IpbUKm9NIqVieM8//GrpPGp1KUB8 j4Wuzo1Lv/WA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723713" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:59 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , stable@dpdk.org, =?utf-8?q?Jacek_Bu=C5=82atek?= , Haiyue Wang Date: Tue, 15 Dec 2020 14:05:13 +0800 Message-Id: <20201215060519.302145-22-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 21/27] net/ice/base: fix for dereference of null pointer X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Added handling of allocation fault for ice_vsi_list_map_info Should also check dereference of NULL pointer to filters VSI list information for FWD_TO_VSI_LISt type only, otherwise, the FWD_TO_VSI type filters by the given VSI can't be located. Also the point *pi should not be NULL pointer, it is a reference to raw data field, so remove this variable, use the reference directly. Fixes: c7dd15931183 ("net/ice/base: add virtual switch code") Cc: stable@dpdk.org Signed-off-by: Jacek BuĊ‚atek Signed-off-by: Haiyue Wang Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_switch.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 45c44ca256..fd2c1ccceb 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -4090,6 +4090,9 @@ ice_add_update_vsi_list(struct ice_hw *hw, ice_create_vsi_list_map(hw, &vsi_handle_arr[0], 2, vsi_list_id); + if (!m_entry->vsi_list_info) + return ICE_ERR_NO_MEMORY; + /* If this entry was large action then the large action needs * to be updated to point to FWD to VSI list */ @@ -5423,6 +5426,7 @@ ice_vsi_uses_fltr(struct ice_fltr_mgmt_list_entry *fm_entry, u16 vsi_handle) return ((fm_entry->fltr_info.fltr_act == ICE_FWD_TO_VSI && fm_entry->fltr_info.vsi_handle == vsi_handle) || (fm_entry->fltr_info.fltr_act == ICE_FWD_TO_VSI_LIST && + fm_entry->vsi_list_info && (ice_is_bit_set(fm_entry->vsi_list_info->vsi_map, vsi_handle)))); } @@ -5497,14 +5501,12 @@ ice_add_to_vsi_fltr_list(struct ice_hw *hw, u16 vsi_handle, LIST_FOR_EACH_ENTRY(fm_entry, lkup_list_head, ice_fltr_mgmt_list_entry, list_entry) { - struct ice_fltr_info *fi; - - fi = &fm_entry->fltr_info; - if (!fi || !ice_vsi_uses_fltr(fm_entry, vsi_handle)) + if (!ice_vsi_uses_fltr(fm_entry, vsi_handle)) continue; status = ice_add_entry_to_vsi_fltr_list(hw, vsi_handle, - vsi_list_head, fi); + vsi_list_head, + &fm_entry->fltr_info); if (status) return status; } From patchwork Tue Dec 15 06:05:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85179 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5D415A09E9; Tue, 15 Dec 2020 07:09:16 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5A364CAA3; Tue, 15 Dec 2020 07:02:07 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 3DE89CA89 for ; Tue, 15 Dec 2020 07:02:03 +0100 (CET) IronPort-SDR: Vkp7/6cxBeJ7KIWrwbc13Eg5JcPeMT/cmbHYqcbia4BhWnXaBxEuTHoDM8TJaqxc+g8jlHHqS4 DKfAh12detrQ== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200308" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200308" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:02:02 -0800 IronPort-SDR: HyS89hRT+6tQXJ9F/Gqdme7oLFQ81lVb+XwUuR9IMNheUQlXNThTgHwv7sBM8y35fLmv2IZU5f vhPvtjhbCx0g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723729" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:02:01 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Mateusz Pacuszka Date: Tue, 15 Dec 2020 14:05:14 +0800 Message-Id: <20201215060519.302145-23-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 22/27] net/ice/base: use Mode 4 to get PHY Abilites X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In case of new link establishment flow we should use Report Default Configuration if FW AQ API version supports it. This patch adds check function for Report Default Configuration support and updates ice_set_fc(), ice_cfg_phy_fec() and ice_aq_get_phy_caps() accordingly. Signed-off-by: Mateusz Pacuszka Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 20 ++++++++------- drivers/net/ice/base/ice_common.c | 36 ++++++++++++++++++++++++--- drivers/net/ice/base/ice_common.h | 1 + drivers/net/ice/base/ice_type.h | 5 ++++ 4 files changed, 49 insertions(+), 13 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index ff0e712d7a..b07d7d7b60 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1213,16 +1213,18 @@ struct ice_aqc_get_phy_caps { __le16 param0; /* 18.0 - Report qualified modules */ #define ICE_AQC_GET_PHY_RQM BIT(0) - /* 18.1 - 18.2 : Report mode - * 00b - Report NVM capabilities - * 01b - Report topology capabilities - * 10b - Report SW configured + /* 18.1 - 18.3 : Report mode + * 000b - Report NVM capabilities + * 001b - Report topology capabilities + * 010b - Report SW configured + * 100b - Report default capabilities */ -#define ICE_AQC_REPORT_MODE_S 1 -#define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) -#define ICE_AQC_REPORT_NVM_CAP 0 -#define ICE_AQC_REPORT_TOPO_CAP BIT(1) -#define ICE_AQC_REPORT_SW_CFG BIT(2) +#define ICE_AQC_REPORT_MODE_S 1 +#define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) +#define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 +#define ICE_AQC_REPORT_TOPO_CAP BIT(1) +#define ICE_AQC_REPORT_SW_CFG BIT(2) +#define ICE_AQC_REPORT_DFLT_CFG BIT(3) __le32 reserved1; __le32 addr_high; __le32 addr_low; diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 5c59dd63cb..a1dce031fb 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -161,6 +161,10 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, return ICE_ERR_PARAM; hw = pi->hw; + if (report_mode == ICE_AQC_REPORT_DFLT_CFG && + !ice_fw_supports_report_dflt_cfg(hw)) + return ICE_ERR_PARAM; + ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); if (qual_mods) @@ -2965,8 +2969,9 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) return ICE_ERR_NO_MEMORY; /* Get the current PHY config */ - status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, - NULL); + status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, + pcaps, NULL); + if (status) { *aq_failures = ICE_SET_FC_AQ_FAIL_GET; goto out; @@ -3120,8 +3125,11 @@ ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, if (!pcaps) return ICE_ERR_NO_MEMORY; - status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps, - NULL); + status = ice_aq_get_phy_caps(pi, false, + (ice_fw_supports_report_dflt_cfg(hw) ? + ICE_AQC_REPORT_DFLT_CFG : + ICE_AQC_REPORT_TOPO_CAP), pcaps, NULL); + if (status) goto out; @@ -4951,3 +4959,23 @@ ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); } + +/** + * ice_fw_supports_report_dflt_cfg + * @hw: pointer to the hardware structure + * + * Checks if the firmware supports report default configuration + */ +bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) +{ + if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) { + if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN) + return true; + if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN && + hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH) + return true; + } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) { + return true; + } + return false; +} diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index 4f534a7f0b..ba56f82ad8 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -225,4 +225,5 @@ ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw); enum ice_status ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add); +bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw); #endif /* _ICE_COMMON_H_ */ diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 4552288b85..4c84466f0b 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -1243,4 +1243,9 @@ struct ice_aq_get_set_rss_lut_params { #define ICE_FW_API_LLDP_FLTR_MAJ 1 #define ICE_FW_API_LLDP_FLTR_MIN 7 #define ICE_FW_API_LLDP_FLTR_PATCH 1 + +/* AQ API version for report default configuration */ +#define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1 +#define ICE_FW_API_REPORT_DFLT_CFG_MIN 7 +#define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3 #endif /* _ICE_TYPE_H_ */ From patchwork Tue Dec 15 06:05:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85180 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id ED139A09E9; Tue, 15 Dec 2020 07:09:34 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A4DB1CAAE; Tue, 15 Dec 2020 07:02:08 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 795B8CA9B for ; Tue, 15 Dec 2020 07:02:06 +0100 (CET) IronPort-SDR: m7cEQ03I13dqDvrKk2/7wFYhCSdeMAJ0PKTyvqbesqLwftFng8+HJeoC6J6VqPrrGEp+esfKih 1HEcMfppgfmQ== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200311" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200311" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:02:04 -0800 IronPort-SDR: YXqFEq62dPUSz1yoe3CahzEOToo2noYAms9WW1AhU4/Bvb02cW3b2lP+89tcqH8bDcsNm41RRr j5fAdTRF/3Cw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723741" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:02:02 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Anirudh Venkataramanan Date: Tue, 15 Dec 2020 14:05:15 +0800 Message-Id: <20201215060519.302145-24-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 23/27] net/ice/base: align macro names to the specification X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" For get PHY abilities AQ, the specification defines "report modes" as "with media", "without media" and "active configuration". For clarity, rename macros to align with the specification. Signed-off-by: Anirudh Venkataramanan Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 4 ++-- drivers/net/ice/base/ice_common.c | 12 ++++++------ drivers/net/ice/ice_dcf_parent.c | 2 +- drivers/net/ice/ice_ethdev.c | 4 ++-- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index b07d7d7b60..ff5f495370 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1222,8 +1222,8 @@ struct ice_aqc_get_phy_caps { #define ICE_AQC_REPORT_MODE_S 1 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 -#define ICE_AQC_REPORT_TOPO_CAP BIT(1) -#define ICE_AQC_REPORT_SW_CFG BIT(2) +#define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) +#define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) #define ICE_AQC_REPORT_DFLT_CFG BIT(3) __le32 reserved1; __le32 addr_high; diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index a1dce031fb..f2fb132060 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -198,7 +198,7 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", pcaps->module_type[2]); - if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) { + if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low); pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high); ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type, @@ -783,7 +783,7 @@ enum ice_status ice_init_hw(struct ice_hw *hw) /* Initialize port_info struct with PHY capabilities */ status = ice_aq_get_phy_caps(hw->port_info, false, - ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); + ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL); ice_free(hw, pcaps); if (status) ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n", @@ -2777,7 +2777,7 @@ enum ice_status ice_update_link_info(struct ice_port_info *pi) if (!pcaps) return ICE_ERR_NO_MEMORY; - status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, + status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL); if (status == ICE_SUCCESS) @@ -2900,7 +2900,7 @@ ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, /* Query the value of FC that both the NIC and attached media * can do. */ - status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, + status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL); if (status) { ice_free(pi->hw, pcaps); @@ -2969,7 +2969,7 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) return ICE_ERR_NO_MEMORY; /* Get the current PHY config */ - status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, + status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, pcaps, NULL); if (status) { @@ -3128,7 +3128,7 @@ ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, status = ice_aq_get_phy_caps(pi, false, (ice_fw_supports_report_dflt_cfg(hw) ? ICE_AQC_REPORT_DFLT_CFG : - ICE_AQC_REPORT_TOPO_CAP), pcaps, NULL); + ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); if (status) goto out; diff --git a/drivers/net/ice/ice_dcf_parent.c b/drivers/net/ice/ice_dcf_parent.c index 30ead4c9fd..7d565028f6 100644 --- a/drivers/net/ice/ice_dcf_parent.c +++ b/drivers/net/ice/ice_dcf_parent.c @@ -202,7 +202,7 @@ ice_dcf_init_parent_hw(struct ice_hw *hw) /* Initialize port_info struct with PHY capabilities */ status = ice_aq_get_phy_caps(hw->port_info, false, - ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); + ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL); ice_free(hw, pcaps); if (status) goto err_unroll_alloc; diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 9a5d6a559f..bb9a065816 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -3840,8 +3840,8 @@ ice_force_phys_link_state(struct ice_hw *hw, bool link_up) if (!pcaps) return ICE_ERR_NO_MEMORY; - status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, - NULL); + status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, + pcaps, NULL); if (status) goto out; From patchwork Tue Dec 15 06:05:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85181 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B2BE7A09E9; Tue, 15 Dec 2020 07:09:52 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DBE13CABB; Tue, 15 Dec 2020 07:02:09 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 4A819CAAA for ; Tue, 15 Dec 2020 07:02:07 +0100 (CET) IronPort-SDR: 2Kmdb97mVQkuztP6UMO07hrDWwkabqijKzSoJN6jtV6R0+acbqvz9w1z/ouQmUBv8E65+LEZID h93tCWlXB35g== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200318" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200318" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:02:06 -0800 IronPort-SDR: WfiV66ULjhVxxVV//RCH3rlAvIxUnrSA84CBGcmeas7hGks3cqtbVIj7pL7VyGIS/hP6ST6BUs sfKknG7NJgsg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723746" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:02:04 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Yahui Cao Date: Tue, 15 Dec 2020 14:05:16 +0800 Message-Id: <20201215060519.302145-25-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 24/27] net/ice/base: add eCPRI over MAC type 0 flow support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds extracting field for flow type eCPRI over mac message type 0 and field PC_ID which is used for FDIR/RSS packet steering. This patch also removes redundant hdr bitmask ops for PPPOE hdr. Signed-off-by: Yahui Cao Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_fdir.c | 16 ++++++++++++++ drivers/net/ice/base/ice_fdir.h | 8 +++++++ drivers/net/ice/base/ice_flow.c | 28 ++++++++++++++++++++---- drivers/net/ice/base/ice_flow.h | 3 +++ drivers/net/ice/base/ice_protocol_type.h | 1 + drivers/net/ice/base/ice_type.h | 1 + 6 files changed, 53 insertions(+), 4 deletions(-) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index cccbcf5e7f..98369b1903 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -305,6 +305,13 @@ static const u8 ice_fdir_non_ip_l2_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; +static const u8 ice_fdir_ecpri_tp0_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xAE, 0xFE, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + static const u8 ice_fdir_tcpv6_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00, @@ -634,6 +641,11 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = { sizeof(ice_fdir_udp4_vxlan_pkt), ice_fdir_udp4_vxlan_pkt, sizeof(ice_fdir_udp4_vxlan_pkt), ice_fdir_udp4_vxlan_pkt, }, + { + ICE_FLTR_PTYPE_NONF_ECPRI_TP0, + sizeof(ice_fdir_ecpri_tp0_pkt), ice_fdir_ecpri_tp0_pkt, + sizeof(ice_fdir_ecpri_tp0_pkt), ice_fdir_ecpri_tp0_pkt, + }, { ICE_FLTR_PTYPE_NONF_IPV6_TCP, sizeof(ice_fdir_tcpv6_pkt), ice_fdir_tcpv6_pkt, @@ -1238,6 +1250,10 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, ice_pkt_insert_u16(loc, ICE_MAC_ETHTYPE_OFFSET, input->ext_data.ether_type); break; + case ICE_FLTR_PTYPE_NONF_ECPRI_TP0: + ice_pkt_insert_u16(loc, ICE_ECPRI_TP0_PC_ID_OFFSET, + input->ecpri_data.pc_id); + break; case ICE_FLTR_PTYPE_NONF_IPV6_TCP: ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, input->ip.v6.src_ip); diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index 1c8de8956d..a0ec519ed0 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -56,6 +56,7 @@ #define ICE_IPV4_NAT_T_ESP_SPI_OFFSET 42 #define ICE_IPV6_NAT_T_ESP_SPI_OFFSET 62 #define ICE_IPV4_VXLAN_VNI_OFFSET 45 +#define ICE_ECPRI_TP0_PC_ID_OFFSET 18 #define ICE_FDIR_MAX_FLTRS 16384 @@ -168,6 +169,10 @@ struct ice_fdir_udp_vxlan { __be32 vni; /* 8 bits reserved, always be zero */ }; +struct ice_fdir_ecpri { + __be16 pc_id; +}; + struct ice_fdir_extra { u8 dst_mac[ETH_ALEN]; /* dest MAC address */ u8 src_mac[ETH_ALEN]; /* src MAC address */ @@ -204,6 +209,9 @@ struct ice_fdir_fltr { struct ice_fdir_l2tpv3 l2tpv3_data; struct ice_fdir_l2tpv3 l2tpv3_mask; + struct ice_fdir_ecpri ecpri_data; + struct ice_fdir_ecpri ecpri_mask; + struct ice_fdir_extra ext_data; struct ice_fdir_extra ext_mask; diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index bce90d9335..eebb328dde 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -31,6 +31,7 @@ #define ICE_FLOW_FLD_SZ_AH_SPI 4 #define ICE_FLOW_FLD_SZ_NAT_T_ESP_SPI 4 #define ICE_FLOW_FLD_SZ_VXLAN_VNI 4 +#define ICE_FLOW_FLD_SZ_ECPRI_TP0_PC_ID 2 /* Describe properties of a protocol header field */ struct ice_flow_field_info { @@ -193,6 +194,10 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = { /* ICE_FLOW_FIELD_IDX_VXLAN_VNI */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_VXLAN, 12, ICE_FLOW_FLD_SZ_VXLAN_VNI), + /* ECPRI_TP0 */ + /* ICE_FLOW_FIELD_IDX_ECPRI_TP0_PC_ID */ + ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_ECPRI_TP0, 4, + ICE_FLOW_FLD_SZ_ECPRI_TP0_PC_ID), }; /* Bitmaps indicating relevant packet types for a particular protocol header @@ -202,7 +207,7 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = { static const u32 ice_ptypes_mac_ofos[] = { 0xFDC00846, 0xBFBF7F7E, 0xF70001DF, 0xFEFDFDFB, 0x0000077E, 0x000003FF, 0x00000000, 0x00000000, - 0x00400000, 0x03FFF000, 0xFFFFFFE0, 0x00000307, + 0x00400000, 0x03FFF000, 0xFFFFFFE0, 0x00000707, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -694,6 +699,17 @@ static const u32 ice_ptypes_gtpu_no_ip[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; +static const u32 ice_ptypes_ecpri_tp0[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000400, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + /* Manage parameters and info. used during the creation of a flow profile */ struct ice_flow_prof_params { enum ice_block blk; @@ -718,7 +734,8 @@ struct ice_flow_prof_params { ICE_FLOW_SEG_HDR_GTPC_TEID | ICE_FLOW_SEG_HDR_GTPU | \ ICE_FLOW_SEG_HDR_PFCP_SESSION | ICE_FLOW_SEG_HDR_L2TPV3 | \ ICE_FLOW_SEG_HDR_ESP | ICE_FLOW_SEG_HDR_AH | \ - ICE_FLOW_SEG_HDR_NAT_T_ESP | ICE_FLOW_SEG_HDR_GTPU_NON_IP) + ICE_FLOW_SEG_HDR_NAT_T_ESP | ICE_FLOW_SEG_HDR_GTPU_NON_IP | \ + ICE_FLOW_SEG_HDR_ECPRI_TP0) #define ICE_FLOW_SEG_HDRS_L2_MASK \ (ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN) @@ -848,8 +865,8 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params) ICE_FLOW_PTYPE_MAX); } - if (hdrs & ICE_FLOW_SEG_HDR_PPPOE) { - src = (const ice_bitmap_t *)ice_ptypes_pppoe; + if (hdrs & ICE_FLOW_SEG_HDR_ECPRI_TP0) { + src = (const ice_bitmap_t *)ice_ptypes_ecpri_tp0; ice_and_bitmap(params->ptypes, params->ptypes, src, ICE_FLOW_PTYPE_MAX); } @@ -1192,6 +1209,9 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, case ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI: prot_id = ICE_PROT_UDP_IL_OR_S; break; + case ICE_FLOW_FIELD_IDX_ECPRI_TP0_PC_ID: + prot_id = ICE_PROT_ECPRI; + break; case ICE_FLOW_FIELD_IDX_ARP_SIP: case ICE_FLOW_FIELD_IDX_ARP_DIP: case ICE_FLOW_FIELD_IDX_ARP_SHA: diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h index 23a98cfe89..eb63f67d42 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -183,6 +183,7 @@ enum ice_flow_seg_hdr { ICE_FLOW_SEG_HDR_ETH_NON_IP = 0x00800000, ICE_FLOW_SEG_HDR_GTPU_NON_IP = 0x01000000, ICE_FLOW_SEG_HDR_VXLAN = 0x02000000, + ICE_FLOW_SEG_HDR_ECPRI_TP0 = 0x04000000, /* The following is an additive bit for ICE_FLOW_SEG_HDR_IPV4 and * ICE_FLOW_SEG_HDR_IPV6 which include the IPV4 other PTYPEs */ @@ -273,6 +274,8 @@ enum ice_flow_field { ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI, /* VXLAN VNI */ ICE_FLOW_FIELD_IDX_VXLAN_VNI, + /* ECPRI_TP0 */ + ICE_FLOW_FIELD_IDX_ECPRI_TP0_PC_ID, /* The total number of enums must not exceed 64 */ ICE_FLOW_FIELD_IDX_MAX }; diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index e8caefd8f9..3c10264761 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -153,6 +153,7 @@ enum ice_prot_id { ICE_PROT_OSPF = 102, ICE_PROT_PPPOE = 103, ICE_PROT_L2TPV3 = 104, + ICE_PROT_ECPRI = 105, ICE_PROT_ATAOE_OF = 114, ICE_PROT_CTRL_OF = 116, ICE_PROT_LLDP_OF = 117, diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 4c84466f0b..4321916777 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -324,6 +324,7 @@ enum ice_fltr_ptype { ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE, ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION, ICE_FLTR_PTYPE_NON_IP_L2, + ICE_FLTR_PTYPE_NONF_ECPRI_TP0, ICE_FLTR_PTYPE_FRAG_IPV4, ICE_FLTR_PTYPE_NONF_IPV6_UDP, ICE_FLTR_PTYPE_NONF_IPV6_TCP, From patchwork Tue Dec 15 06:05:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85182 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3560BA09E9; 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14 Dec 2020 22:02:06 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Yahui Cao Date: Tue, 15 Dec 2020 14:05:17 +0800 Message-Id: <20201215060519.302145-26-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 25/27] net/ice/base: add eCPRI over UDP type 0 flow support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds extracting field for flow type eCPRI over udp message type 0 and field PC_ID which is used for FDIR/RSS packet steering. Signed-off-by: Yahui Cao Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_fdir.c | 57 +++++++++++++++++++++++++++- drivers/net/ice/base/ice_fdir.h | 1 + drivers/net/ice/base/ice_flex_pipe.c | 1 + drivers/net/ice/base/ice_flex_type.h | 1 + drivers/net/ice/base/ice_flow.c | 32 +++++++++++++--- drivers/net/ice/base/ice_flow.h | 3 ++ drivers/net/ice/base/ice_type.h | 1 + 7 files changed, 89 insertions(+), 7 deletions(-) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index 98369b1903..f78cf07d57 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -312,6 +312,16 @@ static const u8 ice_fdir_ecpri_tp0_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; +static const u8 ice_fdir_ipv4_udp_ecpri_tp0_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x1C, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + static const u8 ice_fdir_tcpv6_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00, @@ -646,6 +656,13 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = { sizeof(ice_fdir_ecpri_tp0_pkt), ice_fdir_ecpri_tp0_pkt, sizeof(ice_fdir_ecpri_tp0_pkt), ice_fdir_ecpri_tp0_pkt, }, + { + ICE_FLTR_PTYPE_NONF_IPV4_UDP_ECPRI_TP0, + sizeof(ice_fdir_ipv4_udp_ecpri_tp0_pkt), + ice_fdir_ipv4_udp_ecpri_tp0_pkt, + sizeof(ice_fdir_ipv4_udp_ecpri_tp0_pkt), + ice_fdir_ipv4_udp_ecpri_tp0_pkt, + }, { ICE_FLTR_PTYPE_NONF_IPV6_TCP, sizeof(ice_fdir_tcpv6_pkt), ice_fdir_tcpv6_pkt, @@ -997,6 +1014,33 @@ static void ice_pkt_insert_mac_addr(u8 *pkt, u8 *addr) ice_memcpy(pkt, addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); } +/** + * ice_fdir_get_open_tunnel_port + * @hw: pointer to the hardware structure + * @flow: flow ptype + * @port: returns open port + * + * returns an open tunnel port specified for this flow type + */ +static enum ice_status +ice_fdir_get_open_tunnel_port(struct ice_hw *hw, enum ice_fltr_ptype flow, + u16 *port) +{ + switch (flow) { + case ICE_FLTR_PTYPE_NONF_IPV4_UDP_ECPRI_TP0: + /* eCPRI tunnel */ + if (!ice_get_open_tunnel_port(hw, TNL_ECPRI, port)) + return ICE_ERR_DOES_NOT_EXIST; + break; + default: + if (!ice_get_open_tunnel_port(hw, TNL_VXLAN, port) && + !ice_get_open_tunnel_port(hw, TNL_GENEVE, port)) + return ICE_ERR_DOES_NOT_EXIST; + } + + return ICE_SUCCESS; +} + /** * ice_fdir_get_gen_prgm_pkt - generate a training packet * @hw: pointer to the hardware structure @@ -1058,8 +1102,12 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, ice_fdir_pkt[idx].pkt_len, ICE_NONDMA_TO_NONDMA); loc = pkt; } else { - if (!ice_get_open_tunnel_port(hw, TNL_ALL, &tnl_port)) - return ICE_ERR_DOES_NOT_EXIST; + enum ice_status ret; + + ret = ice_fdir_get_open_tunnel_port(hw, flow, &tnl_port); + if (ret) + return ret; + if (!ice_fdir_pkt[idx].tun_pkt) return ICE_ERR_PARAM; ice_memcpy(pkt, ice_fdir_pkt[idx].tun_pkt, @@ -1254,6 +1302,11 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, ice_pkt_insert_u16(loc, ICE_ECPRI_TP0_PC_ID_OFFSET, input->ecpri_data.pc_id); break; + case ICE_FLTR_PTYPE_NONF_IPV4_UDP_ECPRI_TP0: + /* Use pkt instead of loc, since PC_ID is in outter part */ + ice_pkt_insert_u16(pkt, ICE_IPV4_UDP_ECPRI_TP0_PC_ID_OFFSET, + input->ecpri_data.pc_id); + break; case ICE_FLTR_PTYPE_NONF_IPV6_TCP: ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, input->ip.v6.src_ip); diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index a0ec519ed0..e13863935d 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -57,6 +57,7 @@ #define ICE_IPV6_NAT_T_ESP_SPI_OFFSET 62 #define ICE_IPV4_VXLAN_VNI_OFFSET 45 #define ICE_ECPRI_TP0_PC_ID_OFFSET 18 +#define ICE_IPV4_UDP_ECPRI_TP0_PC_ID_OFFSET 46 #define ICE_FDIR_MAX_FLTRS 16384 diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index e511b50a00..96aed3b795 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -13,6 +13,7 @@ static const struct ice_tunnel_type_scan tnls[] = { { TNL_VXLAN, "TNL_VXLAN_PF" }, { TNL_GENEVE, "TNL_GENEVE_PF" }, + { TNL_ECPRI, "TNL_UDP_ECPRI_PF" }, { TNL_LAST, "" } }; diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h index 08db7f2c9a..62cc81b49c 100644 --- a/drivers/net/ice/base/ice_flex_type.h +++ b/drivers/net/ice/base/ice_flex_type.h @@ -516,6 +516,7 @@ struct ice_pkg_enum { enum ice_tunnel_type { TNL_VXLAN = 0, TNL_GENEVE, + TNL_ECPRI, TNL_GTP, TNL_LAST = 0xFF, TNL_ALL = 0xFF, diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index eebb328dde..15b43061c8 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -198,6 +198,10 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = { /* ICE_FLOW_FIELD_IDX_ECPRI_TP0_PC_ID */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_ECPRI_TP0, 4, ICE_FLOW_FLD_SZ_ECPRI_TP0_PC_ID), + /* UDP_ECPRI_TP0 */ + /* ICE_FLOW_FIELD_IDX_UDP_ECPRI_TP0_PC_ID */ + ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_UDP_ECPRI_TP0, 12, + ICE_FLOW_FLD_SZ_ECPRI_TP0_PC_ID), }; /* Bitmaps indicating relevant packet types for a particular protocol header @@ -207,7 +211,7 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = { static const u32 ice_ptypes_mac_ofos[] = { 0xFDC00846, 0xBFBF7F7E, 0xF70001DF, 0xFEFDFDFB, 0x0000077E, 0x000003FF, 0x00000000, 0x00000000, - 0x00400000, 0x03FFF000, 0xFFFFFFE0, 0x00000707, + 0x00400000, 0x03FFF000, 0xFFFFFFE0, 0x00100707, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -233,7 +237,7 @@ static const u32 ice_ptypes_macvlan_il[] = { static const u32 ice_ptypes_ipv4_ofos[] = { 0x1DC00000, 0x24000800, 0x00000000, 0x00000000, 0x00000000, 0x00000155, 0x00000000, 0x00000000, - 0x00000000, 0x000FC000, 0x000002A0, 0x00000000, + 0x00000000, 0x000FC000, 0x000002A0, 0x00100000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -259,7 +263,7 @@ static const u32 ice_ptypes_ipv4_ofos_all[] = { static const u32 ice_ptypes_ipv4_il[] = { 0xE0000000, 0xB807700E, 0x80000003, 0xE01DC03B, 0x0000000E, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x001FF800, 0x00000000, + 0x00000000, 0x00000000, 0x001FF800, 0x00100000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -373,7 +377,7 @@ static const u32 ice_ptypes_arp_of[] = { static const u32 ice_ptypes_udp_il[] = { 0x81000000, 0x20204040, 0x04000010, 0x80810102, 0x00000040, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00410000, 0x908427E0, 0x00000007, + 0x00000000, 0x00410000, 0x908427E0, 0x00100007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -710,6 +714,17 @@ static const u32 ice_ptypes_ecpri_tp0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; +static const u32 ice_ptypes_udp_ecpri_tp0[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00100000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + /* Manage parameters and info. used during the creation of a flow profile */ struct ice_flow_prof_params { enum ice_block blk; @@ -735,7 +750,7 @@ struct ice_flow_prof_params { ICE_FLOW_SEG_HDR_PFCP_SESSION | ICE_FLOW_SEG_HDR_L2TPV3 | \ ICE_FLOW_SEG_HDR_ESP | ICE_FLOW_SEG_HDR_AH | \ ICE_FLOW_SEG_HDR_NAT_T_ESP | ICE_FLOW_SEG_HDR_GTPU_NON_IP | \ - ICE_FLOW_SEG_HDR_ECPRI_TP0) + ICE_FLOW_SEG_HDR_ECPRI_TP0 | ICE_FLOW_SEG_HDR_UDP_ECPRI_TP0) #define ICE_FLOW_SEG_HDRS_L2_MASK \ (ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN) @@ -1011,6 +1026,10 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params) src = (const ice_bitmap_t *)ice_ptypes_vxlan_vni; ice_and_bitmap(params->ptypes, params->ptypes, src, ICE_FLOW_PTYPE_MAX); + } else if (hdrs & ICE_FLOW_SEG_HDR_UDP_ECPRI_TP0) { + src = (const ice_bitmap_t *)ice_ptypes_udp_ecpri_tp0; + ice_and_bitmap(params->ptypes, params->ptypes, + src, ICE_FLOW_PTYPE_MAX); } if (hdrs & ICE_FLOW_SEG_HDR_PFCP) { @@ -1212,6 +1231,9 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, case ICE_FLOW_FIELD_IDX_ECPRI_TP0_PC_ID: prot_id = ICE_PROT_ECPRI; break; + case ICE_FLOW_FIELD_IDX_UDP_ECPRI_TP0_PC_ID: + prot_id = ICE_PROT_UDP_IL_OR_S; + break; case ICE_FLOW_FIELD_IDX_ARP_SIP: case ICE_FLOW_FIELD_IDX_ARP_DIP: case ICE_FLOW_FIELD_IDX_ARP_SHA: diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h index eb63f67d42..6d02252ecf 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -184,6 +184,7 @@ enum ice_flow_seg_hdr { ICE_FLOW_SEG_HDR_GTPU_NON_IP = 0x01000000, ICE_FLOW_SEG_HDR_VXLAN = 0x02000000, ICE_FLOW_SEG_HDR_ECPRI_TP0 = 0x04000000, + ICE_FLOW_SEG_HDR_UDP_ECPRI_TP0 = 0x08000000, /* The following is an additive bit for ICE_FLOW_SEG_HDR_IPV4 and * ICE_FLOW_SEG_HDR_IPV6 which include the IPV4 other PTYPEs */ @@ -276,6 +277,8 @@ enum ice_flow_field { ICE_FLOW_FIELD_IDX_VXLAN_VNI, /* ECPRI_TP0 */ ICE_FLOW_FIELD_IDX_ECPRI_TP0_PC_ID, + /* UDP_ECPRI_TP0 */ + ICE_FLOW_FIELD_IDX_UDP_ECPRI_TP0_PC_ID, /* The total number of enums must not exceed 64 */ ICE_FLOW_FIELD_IDX_MAX }; diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 4321916777..bb2cfd07fd 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -325,6 +325,7 @@ enum ice_fltr_ptype { ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION, ICE_FLTR_PTYPE_NON_IP_L2, ICE_FLTR_PTYPE_NONF_ECPRI_TP0, + ICE_FLTR_PTYPE_NONF_IPV4_UDP_ECPRI_TP0, ICE_FLTR_PTYPE_FRAG_IPV4, ICE_FLTR_PTYPE_NONF_IPV6_UDP, ICE_FLTR_PTYPE_NONF_IPV6_TCP, From patchwork Tue Dec 15 06:05:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85183 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E3DB5A09E9; Tue, 15 Dec 2020 07:10:25 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A7B99CAC7; Tue, 15 Dec 2020 07:02:12 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id BBC2FCAB7 for ; Tue, 15 Dec 2020 07:02:09 +0100 (CET) IronPort-SDR: xX9w2pRwn5k1o1H71U6aigS8mFwClXl2EroJWM1seavSWyN5TjkMeaV+2qliiPSqrJl36j9Xrh /3oOjew81H2A== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200327" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200327" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:02:09 -0800 IronPort-SDR: eFHDbJDdUwUv/zHo+iXmWh6sW8/C2WRJoHInEO0489EUG2L5neNeNRL3Tpmbc5pzf8BCLKaytf 6D+fjNL+9LoA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723761" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:02:08 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Jesse Brandeburg Date: Tue, 15 Dec 2020 14:05:18 +0800 Message-Id: <20201215060519.302145-27-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 26/27] net/ice/base: remove unused struct member X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The only time you can ever have a rq_last_status is if a firmware event was somehow reporting a status on the receive queue, which are generally firmware initiated events or mailbox messages from a VF. Mostly this struct member was unused. Fix this problem by still printing the value of the field in a debug print, but don't store the value forever in a struct, potentially creating opportunities for callers to use the wrong struct member. Signed-off-by: Jesse Brandeburg Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_controlq.c | 6 +++--- drivers/net/ice/base/ice_controlq.h | 1 - 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c index 4c4f92552b..59e7c5f88d 100644 --- a/drivers/net/ice/base/ice_controlq.c +++ b/drivers/net/ice/base/ice_controlq.c @@ -1110,6 +1110,7 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, struct ice_rq_event_info *e, u16 *pending) { u16 ntc = cq->rq.next_to_clean; + enum ice_aq_err rq_last_status; enum ice_status ret_code = ICE_SUCCESS; struct ice_aq_desc *desc; struct ice_dma_mem *bi; @@ -1143,13 +1144,12 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, desc = ICE_CTL_Q_DESC(cq->rq, ntc); desc_idx = ntc; - cq->rq_last_status = (enum ice_aq_err)LE16_TO_CPU(desc->retval); + rq_last_status = (enum ice_aq_err)LE16_TO_CPU(desc->retval); flags = LE16_TO_CPU(desc->flags); if (flags & ICE_AQ_FLAG_ERR) { ret_code = ICE_ERR_AQ_ERROR; ice_debug(hw, ICE_DBG_AQ_MSG, "Control Receive Queue Event 0x%04X received with error 0x%X\n", - LE16_TO_CPU(desc->opcode), - cq->rq_last_status); + LE16_TO_CPU(desc->opcode), rq_last_status); } ice_memcpy(&e->desc, desc, sizeof(e->desc), ICE_DMA_TO_NONDMA); datalen = LE16_TO_CPU(desc->datalen); diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h index 84c114f7a4..161c1bebff 100644 --- a/drivers/net/ice/base/ice_controlq.h +++ b/drivers/net/ice/base/ice_controlq.h @@ -84,7 +84,6 @@ struct ice_rq_event_info { /* Control Queue information */ struct ice_ctl_q_info { enum ice_ctl_q qtype; - enum ice_aq_err rq_last_status; /* last status on receive queue */ struct ice_ctl_q_ring rq; /* receive queue */ struct ice_ctl_q_ring sq; /* send queue */ u32 sq_cmd_timeout; /* send queue cmd write back timeout */ From patchwork Tue Dec 15 06:05:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 85184 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9E68FA09E9; Tue, 15 Dec 2020 07:10:46 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 61DF4CAD4; Tue, 15 Dec 2020 07:02:14 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 35A33CACA for ; Tue, 15 Dec 2020 07:02:13 +0100 (CET) IronPort-SDR: 7V6Hv+LZLJYeHIkROf6A6khuNAvEe56YPnBCOIqIRCl8ezhVTViVgFR+nVOaRO5C7aqeSAIWkf iZqbcv3eDG+w== X-IronPort-AV: E=McAfee;i="6000,8403,9835"; a="193200330" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="193200330" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 22:02:11 -0800 IronPort-SDR: cD85jiEHZLEPT1NTEeM0kFfIoKxlQNnGVVW1Ilaf6KkqrgsRkZNgI+IzX0OIz67xXc2fmM6YYz 8CPnqnN9FHaA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208";a="351723767" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:02:09 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang Date: Tue, 15 Dec 2020 14:05:19 +0800 Message-Id: <20201215060519.302145-28-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com> References: <20201215060519.302145-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 27/27] net/ice/base: change a structure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The change is for kernel driver RDMA usage, DPDK driver does not enable RDMA, just for code sync. Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index ff5f495370..32c88bfe6e 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1008,7 +1008,8 @@ struct ice_aqc_txsched_move_grp_info_hdr { __le32 src_parent_teid; __le32 dest_parent_teid; __le16 num_elems; - __le16 reserved; + u8 flags; + u8 reserved; }; struct ice_aqc_move_elem {