From patchwork Fri Jan 8 04:35:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 86147 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E523DA0524; Fri, 8 Jan 2021 05:31:28 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CBFEE140DCA; Fri, 8 Jan 2021 05:31:21 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id A7D8C140DAF for ; Fri, 8 Jan 2021 05:31:19 +0100 (CET) IronPort-SDR: H4g8yzIySSSocyJ/5OuClyzvpPs+TeCSA5zA0Q04YSTnLQMQZjUePpTRnoAvvdTPZe36b1ABuN 2PhEw6yhDbZw== X-IronPort-AV: E=McAfee;i="6000,8403,9857"; a="262309365" X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="262309365" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2021 20:31:19 -0800 IronPort-SDR: xm+5bkn1jm/k1Soq49Ms1WA1FH9JHbF3+Z+Ayrz7HVA8Cdv1AJi1gGP/T9hw++ZNPabUmjn0bR W0xkO601qOPw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="398858702" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga002.fm.intel.com with ESMTP; 07 Jan 2021 20:31:17 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: haiyue.wang@intel.com, jia.guo@intel.com, dev@dpdk.org, ferruh.yigit@intel.com, Qi Zhang , Amir Shay Date: Fri, 8 Jan 2021 12:35:00 +0800 Message-Id: <20210108043508.301227-2-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210108043508.301227-1-qi.z.zhang@intel.com> References: <20210108043508.301227-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 1/9] net/ice/base: align add VSI and update VSI AQ command buffer X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Aligned the buffer the following admin commands to their new definitions: * 0x210 = add_vsi * 0x211 = update_vsi Signed-off-by: Amir Shay Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 209 +++++++++++++------------- drivers/net/ice/ice_ethdev.c | 88 +++++------ 2 files changed, 152 insertions(+), 145 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 32c88bfe6e..cb9924562a 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -432,144 +432,151 @@ struct ice_aqc_vsi_props { #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) u8 sw_flags2; #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 -#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ - (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) +#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) u8 veb_stat_id; #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 -#define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) +#define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) /* security section */ u8 sec_flags; #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) -#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 -#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) +#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 +#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) u8 sec_reserved; /* VLAN section */ - __le16 pvid; /* VLANS include priority bits */ - u8 pvlan_reserved[2]; - u8 vlan_flags; -#define ICE_AQ_VSI_VLAN_MODE_S 0 -#define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) -#define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 -#define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 -#define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 -#define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) -#define ICE_AQ_VSI_VLAN_EMOD_S 3 -#define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) -#define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) -#define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) -#define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) -#define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) - u8 pvlan_reserved2[3]; + __le16 port_based_inner_vlan; /* VLANS include priority bits */ + u8 inner_vlan_reserved[2]; + u8 inner_vlan_flags; +#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 +#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) +#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 +#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 +#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 +#define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) +#define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 +#define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) +#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) +#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) +#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) +#define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) +#define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5) + u8 inner_vlan_reserved2[3]; /* ingress egress up sections */ __le32 ingress_table; /* bitmap, 3 bits per up */ -#define ICE_AQ_VSI_UP_TABLE_UP0_S 0 -#define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) -#define ICE_AQ_VSI_UP_TABLE_UP1_S 3 -#define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) -#define ICE_AQ_VSI_UP_TABLE_UP2_S 6 -#define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) -#define ICE_AQ_VSI_UP_TABLE_UP3_S 9 -#define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) -#define ICE_AQ_VSI_UP_TABLE_UP4_S 12 -#define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) -#define ICE_AQ_VSI_UP_TABLE_UP5_S 15 -#define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) -#define ICE_AQ_VSI_UP_TABLE_UP6_S 18 -#define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) -#define ICE_AQ_VSI_UP_TABLE_UP7_S 21 -#define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) +#define ICE_AQ_VSI_UP_TABLE_UP0_S 0 +#define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) +#define ICE_AQ_VSI_UP_TABLE_UP1_S 3 +#define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) +#define ICE_AQ_VSI_UP_TABLE_UP2_S 6 +#define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) +#define ICE_AQ_VSI_UP_TABLE_UP3_S 9 +#define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) +#define ICE_AQ_VSI_UP_TABLE_UP4_S 12 +#define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) +#define ICE_AQ_VSI_UP_TABLE_UP5_S 15 +#define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) +#define ICE_AQ_VSI_UP_TABLE_UP6_S 18 +#define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) +#define ICE_AQ_VSI_UP_TABLE_UP7_S 21 +#define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) __le32 egress_table; /* same defines as for ingress table */ /* outer tags section */ - __le16 outer_tag; - u8 outer_tag_flags; -#define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 -#define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) -#define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 -#define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 -#define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 -#define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 -#define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) -#define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 -#define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 -#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 -#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 -#define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) -#define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) - u8 outer_tag_reserved; + __le16 port_based_outer_vlan; + u8 outer_vlan_flags; +#define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 +#define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) +#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 +#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 +#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 +#define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 +#define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 +#define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) +#define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 +#define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 +#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 +#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 +#define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) +#define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST BIT(4) +#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 +#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) +#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 +#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 +#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 +#define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) + u8 outer_vlan_reserved; /* queue mapping section */ __le16 mapping_flags; -#define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 -#define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) +#define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 +#define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) __le16 q_mapping[16]; -#define ICE_AQ_VSI_Q_S 0 -#define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) +#define ICE_AQ_VSI_Q_S 0 +#define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) __le16 tc_mapping[8]; -#define ICE_AQ_VSI_TC_Q_OFFSET_S 0 -#define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) -#define ICE_AQ_VSI_TC_Q_NUM_S 11 -#define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) +#define ICE_AQ_VSI_TC_Q_OFFSET_S 0 +#define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) +#define ICE_AQ_VSI_TC_Q_NUM_S 11 +#define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) /* queueing option section */ u8 q_opt_rss; -#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 -#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) -#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 -#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 -#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 -#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 -#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) -#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 -#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) -#define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) -#define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) -#define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) -#define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) +#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 +#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) +#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 +#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 +#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 +#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 +#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) +#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 +#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) +#define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) +#define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) +#define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) +#define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) u8 q_opt_tc; -#define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 -#define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) -#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) +#define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 +#define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) +#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) u8 q_opt_flags; -#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) +#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) u8 q_opt_reserved[3]; /* outer up section */ __le32 outer_up_table; /* same structure and defines as ingress tbl */ /* ACL section */ __le16 acl_def_act; -#define ICE_AQ_VSI_ACL_DEF_RX_PROF_S 0 -#define ICE_AQ_VSI_ACL_DEF_RX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_PROF_S) -#define ICE_AQ_VSI_ACL_DEF_RX_TABLE_S 4 -#define ICE_AQ_VSI_ACL_DEF_RX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_TABLE_S) -#define ICE_AQ_VSI_ACL_DEF_TX_PROF_S 8 -#define ICE_AQ_VSI_ACL_DEF_TX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_PROF_S) -#define ICE_AQ_VSI_ACL_DEF_TX_TABLE_S 12 -#define ICE_AQ_VSI_ACL_DEF_TX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_TABLE_S) +#define ICE_AQ_VSI_ACL_DEF_RX_PROF_S 0 +#define ICE_AQ_VSI_ACL_DEF_RX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_PROF_S) +#define ICE_AQ_VSI_ACL_DEF_RX_TABLE_S 4 +#define ICE_AQ_VSI_ACL_DEF_RX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_TABLE_S) +#define ICE_AQ_VSI_ACL_DEF_TX_PROF_S 8 +#define ICE_AQ_VSI_ACL_DEF_TX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_PROF_S) +#define ICE_AQ_VSI_ACL_DEF_TX_TABLE_S 12 +#define ICE_AQ_VSI_ACL_DEF_TX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_TABLE_S) /* flow director section */ __le16 fd_options; -#define ICE_AQ_VSI_FD_ENABLE BIT(0) -#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) -#define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) +#define ICE_AQ_VSI_FD_ENABLE BIT(0) +#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) +#define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) __le16 max_fd_fltr_dedicated; __le16 max_fd_fltr_shared; __le16 fd_def_q; -#define ICE_AQ_VSI_FD_DEF_Q_S 0 -#define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) -#define ICE_AQ_VSI_FD_DEF_GRP_S 12 -#define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) +#define ICE_AQ_VSI_FD_DEF_Q_S 0 +#define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) +#define ICE_AQ_VSI_FD_DEF_GRP_S 12 +#define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) __le16 fd_report_opt; -#define ICE_AQ_VSI_FD_REPORT_Q_S 0 -#define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) -#define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 -#define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) -#define ICE_AQ_VSI_FD_DEF_DROP BIT(15) +#define ICE_AQ_VSI_FD_REPORT_Q_S 0 +#define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) +#define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 +#define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) +#define ICE_AQ_VSI_FD_DEF_DROP BIT(15) /* PASID section */ __le32 pasid_id; -#define ICE_AQ_VSI_PASID_ID_S 0 -#define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) -#define ICE_AQ_VSI_PASID_ID_VALID BIT(31) +#define ICE_AQ_VSI_PASID_ID_S 0 +#define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) +#define ICE_AQ_VSI_PASID_ID_VALID BIT(31) u8 reserved[24]; }; diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index dad808dae7..587f485ee3 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -1128,28 +1128,28 @@ ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on) if (vsi->info.valid_sections & rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { if (on) { - if ((vsi->info.outer_tag_flags & - ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) == - ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) + if ((vsi->info.outer_vlan_flags & + ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST) == + ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST) return 0; /* already on */ } else { - if (!(vsi->info.outer_tag_flags & - ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)) + if (!(vsi->info.outer_vlan_flags & + ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST)) return 0; /* already off */ } } if (on) - qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST; + qinq_flags = ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST; else qinq_flags = 0; /* clear global insertion and use per packet insertion */ - vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT); - vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST); - vsi->info.outer_tag_flags |= qinq_flags; + vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT); + vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST); + vsi->info.outer_vlan_flags |= qinq_flags; /* use default vlan type 0x8100 */ - vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); - vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << + vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); + vsi->info.outer_vlan_flags |= ICE_DFLT_OUTER_TAG_TYPE << ICE_AQ_VSI_OUTER_TAG_TYPE_S; (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); ctxt.info.valid_sections = @@ -1181,27 +1181,27 @@ ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on) if (vsi->info.valid_sections & rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) { if (on) { - if ((vsi->info.outer_tag_flags & - ICE_AQ_VSI_OUTER_TAG_MODE_M) == - ICE_AQ_VSI_OUTER_TAG_COPY) + if ((vsi->info.outer_vlan_flags & + ICE_AQ_VSI_OUTER_VLAN_EMODE_M) == + ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW) return 0; /* already on */ } else { - if ((vsi->info.outer_tag_flags & - ICE_AQ_VSI_OUTER_TAG_MODE_M) == - ICE_AQ_VSI_OUTER_TAG_NOTHING) + if ((vsi->info.outer_vlan_flags & + ICE_AQ_VSI_OUTER_VLAN_EMODE_M) == + ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH) return 0; /* already off */ } } if (on) - qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY; + qinq_flags = ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW; else - qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING; - vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M); - vsi->info.outer_tag_flags |= qinq_flags; + qinq_flags = ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH; + vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M); + vsi->info.outer_vlan_flags |= qinq_flags; /* use default vlan type 0x8100 */ - vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); - vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE << + vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M); + vsi->info.outer_vlan_flags |= ICE_DFLT_OUTER_TAG_TYPE << ICE_AQ_VSI_OUTER_TAG_TYPE_S; (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); ctxt.info.valid_sections = @@ -1579,8 +1579,8 @@ ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) vsi_ctx.info.sw_id = hw->port_info->sw_id; vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; /* Allow all untagged or tagged packets */ - vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL; - vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING; + vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL; + vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING; vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF | ICE_AQ_VSI_Q_OPT_RSS_TPLZ; @@ -4090,24 +4090,24 @@ ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on) if (vsi->info.valid_sections & rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) { if (on) { - if ((vsi->info.vlan_flags & - ICE_AQ_VSI_VLAN_EMOD_M) == - ICE_AQ_VSI_VLAN_EMOD_STR_BOTH) + if ((vsi->info.inner_vlan_flags & + ICE_AQ_VSI_INNER_VLAN_EMODE_M) == + ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH) return 0; /* already on */ } else { - if ((vsi->info.vlan_flags & - ICE_AQ_VSI_VLAN_EMOD_M) == - ICE_AQ_VSI_VLAN_EMOD_NOTHING) + if ((vsi->info.inner_vlan_flags & + ICE_AQ_VSI_INNER_VLAN_EMODE_M) == + ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING) return 0; /* already off */ } } if (on) - vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH; + vlan_flags = ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH; else - vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING; - vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M); - vsi->info.vlan_flags |= vlan_flags; + vlan_flags = ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING; + vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_EMODE_M); + vsi->info.inner_vlan_flags |= vlan_flags; (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID); @@ -4586,24 +4586,24 @@ ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info) } if (info->on) { - vsi->info.pvid = info->config.pvid; + vsi->info.port_based_inner_vlan = info->config.pvid; /** * If insert pvid is enabled, only tagged pkts are * allowed to be sent out. */ - vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID | - ICE_AQ_VSI_VLAN_MODE_UNTAGGED; + vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID | + ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED; } else { - vsi->info.pvid = 0; + vsi->info.port_based_inner_vlan = 0; if (info->config.reject.tagged == 0) - vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED; + vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED; if (info->config.reject.untagged == 0) - vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED; + vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED; } - vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID | - ICE_AQ_VSI_VLAN_MODE_M); - vsi->info.vlan_flags |= vlan_flags; + vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID | + ICE_AQ_VSI_INNER_VLAN_EMODE_M); + vsi->info.inner_vlan_flags |= vlan_flags; memset(&ctxt, 0, sizeof(ctxt)); rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info)); ctxt.info.valid_sections = From patchwork Fri Jan 8 04:35:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 86148 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 82B1EA0524; Fri, 8 Jan 2021 05:31:37 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EDBF8140DE5; Fri, 8 Jan 2021 05:31:22 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 4A7CC140DCA for ; Fri, 8 Jan 2021 05:31:21 +0100 (CET) IronPort-SDR: Ju908VH0KayrRUdcvkdOq8gydWEPGPT3IIawajSRc3IwVw+2cd59FnJ208jcBtsVCER9AQtDCn Mdfq5xpFOwlA== X-IronPort-AV: E=McAfee;i="6000,8403,9857"; a="262309370" X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="262309370" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2021 20:31:21 -0800 IronPort-SDR: 75ISntlOeFwRt88qGVAL1ira9ljqZ58y5bizRS2vghomo/qPeYIEDhV3Fc1eTs4C++I676BcKV ZPtMropgyUTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="398858709" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga002.fm.intel.com with ESMTP; 07 Jan 2021 20:31:19 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: haiyue.wang@intel.com, jia.guo@intel.com, dev@dpdk.org, ferruh.yigit@intel.com, Qi Zhang Date: Fri, 8 Jan 2021 12:35:01 +0800 Message-Id: <20210108043508.301227-3-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210108043508.301227-1-qi.z.zhang@intel.com> References: <20210108043508.301227-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 2/9] net/ice/base: remove the deprecated field X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" hw_vsi_id is used to replace vsi_id, so remove the deprecated vsi_id. Signed-off-by: Haiyue Wang Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_switch.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index be9b74fd4c..a3c4713f5e 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -182,7 +182,6 @@ struct ice_fltr_info { */ u16 q_id:11; u16 hw_vsi_id:10; - u16 vsi_id:10; u16 vsi_list_id:10; } fwd_id; From patchwork Fri Jan 8 04:35:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 86149 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6BD99A0524; Fri, 8 Jan 2021 05:31:45 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 16F4C140DED; Fri, 8 Jan 2021 05:31:24 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 1A1B0140DE9 for ; Fri, 8 Jan 2021 05:31:22 +0100 (CET) IronPort-SDR: IhGNzUD1ejltOcPnvfJBkPW4bu2gw6NEeKx1zi6jBjiz/kISfpnwEkL0SaehugDS06doAZvuMl Sei6bpbSv53g== X-IronPort-AV: E=McAfee;i="6000,8403,9857"; a="262309374" X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="262309374" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2021 20:31:22 -0800 IronPort-SDR: YLdXWKy/urCT2gFSoOj3SlgKPduzqXp87siW+1usV0mi0E2SlRPCV1OsG43XVU55EzlmiBNxwx TwxJcJjnW8hw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="398858715" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga002.fm.intel.com with ESMTP; 07 Jan 2021 20:31:21 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: haiyue.wang@intel.com, jia.guo@intel.com, dev@dpdk.org, ferruh.yigit@intel.com, Qi Zhang Date: Fri, 8 Jan 2021 12:35:02 +0800 Message-Id: <20210108043508.301227-4-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210108043508.301227-1-qi.z.zhang@intel.com> References: <20210108043508.301227-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 3/9] net/ice/base: add package PTYPE enable information X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Scan the 'Marker PType TCAM' session to retrieve the Rx parser PTYPE enable information from the current package. Signed-off-by: Haiyue Wang Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flex_pipe.c | 79 ++++++++++++++++++++++++++++ drivers/net/ice/base/ice_flex_pipe.h | 3 ++ drivers/net/ice/base/ice_flex_type.h | 19 +++++++ drivers/net/ice/base/ice_type.h | 1 + 4 files changed, 102 insertions(+) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 96aed3b795..427b688535 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -316,6 +316,84 @@ ice_pkg_enum_entry(struct ice_seg *ice_seg, struct ice_pkg_enum *state, return entry; } +/** + * ice_hw_ptype_ena - check if the PTYPE is enabled or not + * @hw: pointer to the HW structure + * @ptype: the hardware PTYPE + */ +bool ice_hw_ptype_ena(struct ice_hw *hw, u16 ptype) +{ + return ptype < ICE_FLOW_PTYPE_MAX && + ice_is_bit_set(hw->hw_ptype, ptype); +} + +/** + * ice_marker_ptype_tcam_handler + * @sect_type: section type + * @section: pointer to section + * @index: index of the Marker PType TCAM entry to be returned + * @offset: pointer to receive absolute offset, always 0 for ptype TCAM sections + * + * This is a callback function that can be passed to ice_pkg_enum_entry. + * Handles enumeration of individual Marker PType TCAM entries. + */ +static void * +ice_marker_ptype_tcam_handler(u32 sect_type, void *section, u32 index, + u32 *offset) +{ + struct ice_marker_ptype_tcam_section *marker_ptype; + + if (!section) + return NULL; + + if (sect_type != ICE_SID_RXPARSER_MARKER_PTYPE) + return NULL; + + /* cppcheck-suppress nullPointer */ + if (index > ICE_MAX_MARKER_PTYPE_TCAMS_IN_BUF) + return NULL; + + if (offset) + *offset = 0; + + marker_ptype = (struct ice_marker_ptype_tcam_section *)section; + if (index >= LE16_TO_CPU(marker_ptype->count)) + return NULL; + + return marker_ptype->tcam + index; +} + +/** + * ice_fill_hw_ptype - fill the enabled PTYPE bit information + * @hw: pointer to the HW structure + */ +static void +ice_fill_hw_ptype(struct ice_hw *hw) +{ + struct ice_marker_ptype_tcam_entry *tcam; + struct ice_seg *seg = hw->seg; + struct ice_pkg_enum state; + + ice_zero_bitmap(hw->hw_ptype, ICE_FLOW_PTYPE_MAX); + if (!seg) + return; + + ice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM); + + do { + tcam = (struct ice_marker_ptype_tcam_entry *) + ice_pkg_enum_entry(seg, &state, + ICE_SID_RXPARSER_MARKER_PTYPE, NULL, + ice_marker_ptype_tcam_handler); + if (tcam && + LE16_TO_CPU(tcam->addr) < ICE_MARKER_PTYPE_TCAM_ADDR_MAX && + LE16_TO_CPU(tcam->ptype) < ICE_FLOW_PTYPE_MAX) + ice_set_bit(LE16_TO_CPU(tcam->ptype), hw->hw_ptype); + + seg = NULL; + } while (tcam); +} + /** * ice_boost_tcam_handler * @sect_type: section type @@ -1541,6 +1619,7 @@ enum ice_status ice_init_pkg(struct ice_hw *hw, u8 *buf, u32 len) */ ice_init_pkg_regs(hw); ice_fill_blk_tbls(hw); + ice_fill_hw_ptype(hw); ice_get_prof_index_max(hw); } else { ice_debug(hw, ICE_DBG_INIT, "package load failed, %d\n", diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h index d4679cc940..066ff95e13 100644 --- a/drivers/net/ice/base/ice_flex_pipe.h +++ b/drivers/net/ice/base/ice_flex_pipe.h @@ -54,6 +54,9 @@ bool ice_tunnel_port_in_use(struct ice_hw *hw, u16 port, u16 *index); bool ice_tunnel_get_type(struct ice_hw *hw, u16 port, enum ice_tunnel_type *type); +/* RX parser PType functions */ +bool ice_hw_ptype_ena(struct ice_hw *hw, u16 ptype); + /* XLT2/VSI group functions */ enum ice_status ice_vsig_find_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 *vsig); diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h index 62cc81b49c..9b9503b3ba 100644 --- a/drivers/net/ice/base/ice_flex_type.h +++ b/drivers/net/ice/base/ice_flex_type.h @@ -472,6 +472,25 @@ struct ice_boost_tcam_section { sizeof(struct ice_boost_tcam_entry), \ sizeof(struct ice_boost_tcam_entry)) +/* package Marker PType TCAM entry */ +struct ice_marker_ptype_tcam_entry { +#define ICE_MARKER_PTYPE_TCAM_ADDR_MAX 1024 + __le16 addr; + __le16 ptype; + u8 keys[20]; +}; + +struct ice_marker_ptype_tcam_section { + __le16 count; + __le16 reserved; + struct ice_marker_ptype_tcam_entry tcam[STRUCT_HACK_VAR_LEN]; +}; + +#define ICE_MAX_MARKER_PTYPE_TCAMS_IN_BUF ICE_MAX_ENTRIES_IN_BUF( \ + ice_struct_size((struct ice_marker_ptype_tcam_section *)0, tcam, 1) - \ + sizeof(struct ice_marker_ptype_tcam_entry), \ + sizeof(struct ice_marker_ptype_tcam_entry)) + struct ice_xlt1_section { __le16 count; __le16 offset; diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index bb2cfd07fd..86e93c34a1 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -995,6 +995,7 @@ struct ice_hw { struct ice_lock rss_locks; /* protect RSS configuration */ struct LIST_HEAD_TYPE rss_list_head; struct ice_vlan_mode_ops vlan_mode_ops; + ice_declare_bitmap(hw_ptype, ICE_FLOW_PTYPE_MAX); }; /* Statistics collected by each port, VSI, VEB, and S-channel */ From patchwork Fri Jan 8 04:35:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 86150 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B7A87A0524; Fri, 8 Jan 2021 05:31:56 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9A40A140DF4; Fri, 8 Jan 2021 05:31:27 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 52CCA140DF8; Fri, 8 Jan 2021 05:31:25 +0100 (CET) IronPort-SDR: /KwcFEpYOPsWtsUi4xBvdQ4bxUh5qWjOTk3zleDfDgXQWm2nW3S7bqpDmz36qrcKg74viKdRcP 6t/LG/raK28A== X-IronPort-AV: E=McAfee;i="6000,8403,9857"; a="262309382" X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="262309382" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2021 20:31:25 -0800 IronPort-SDR: mtjRBLDefU8eRV6cs3wAoUYI0Av1fgGhhhIOTQDpVoaxedRPkSBxUnndTJPwZ1y5sB1OvgeP16 iv7EYeGqfE3g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="398858724" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga002.fm.intel.com with ESMTP; 07 Jan 2021 20:31:22 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: haiyue.wang@intel.com, jia.guo@intel.com, dev@dpdk.org, ferruh.yigit@intel.com, Qi Zhang , stable@dpdk.org, Andrii Pypchenko Date: Fri, 8 Jan 2021 12:35:03 +0800 Message-Id: <20210108043508.301227-5-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210108043508.301227-1-qi.z.zhang@intel.com> References: <20210108043508.301227-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 4/9] net/ice/base: fix for memory handling X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Fixed memory handling when memory allocated in user space was handled as memory allocated in kernel space within QV os_dep implementation of the ice_memdup function. Fixes: 93e84b1bfc92 ("net/ice/base: add basic Tx scheduler") Cc: stable@dpdk.org Signed-off-by: Andrii Pypchenko Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_sched.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index b75a44f54c..1cce8eaff1 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -1361,7 +1361,7 @@ enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw) ice_memdup(hw, buf->layer_props, (hw->num_tx_sched_layers * sizeof(*hw->layer_info)), - ICE_DMA_TO_DMA); + ICE_NONDMA_TO_NONDMA); if (!hw->layer_info) { status = ICE_ERR_NO_MEMORY; goto sched_query_out; From patchwork Fri Jan 8 04:35:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 86151 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 27054A0524; Fri, 8 Jan 2021 05:32:05 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DD376140E01; Fri, 8 Jan 2021 05:31:28 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 1C42F140DF8 for ; Fri, 8 Jan 2021 05:31:26 +0100 (CET) IronPort-SDR: g15huDcSynS51SZG3r1//1RzHB4VrxOLa37jpQLC8ywjtXhyVUqzGFWWdQIUtzYH+JTwLlQc/e xzCkg16n05iw== X-IronPort-AV: E=McAfee;i="6000,8403,9857"; a="262309387" X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="262309387" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2021 20:31:26 -0800 IronPort-SDR: tcGjHs//PUSKEi1bJQCaQMgUK+WVIYhExPEPvW9b1c/u78YlcACPzHc0qMyyOuDrypYqSwESdn n6e/lsyIwcvQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="398858728" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga002.fm.intel.com with ESMTP; 07 Jan 2021 20:31:25 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: haiyue.wang@intel.com, jia.guo@intel.com, dev@dpdk.org, ferruh.yigit@intel.com, Qi Zhang , Jeb Cramer Date: Fri, 8 Jan 2021 12:35:04 +0800 Message-Id: <20210108043508.301227-6-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210108043508.301227-1-qi.z.zhang@intel.com> References: <20210108043508.301227-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 5/9] net/ice/base: limit forced overrides based on FW version X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Beyond a specific version of firmware, there is no need to provide override values to the firmware when setting PHY capabilities. In this case, we do not need to indicate whether we're in Strict or Lenient Link Mode. In the case of translating capabilities to the configuration structure, the module compliance enforcement is already correctly set by firmware, so the extra code block is redundant. Signed-off-by: Jeb Cramer Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_common.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index f2fb132060..b71feb3476 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -3088,17 +3088,6 @@ ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, cfg->link_fec_opt = caps->link_fec_options; cfg->module_compliance_enforcement = caps->module_compliance_enforcement; - - if (ice_fw_supports_link_override(pi->hw)) { - struct ice_link_default_override_tlv tlv; - - if (ice_get_link_default_override(&tlv, pi)) - return; - - if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) - cfg->module_compliance_enforcement |= - ICE_LINK_OVERRIDE_STRICT_MODE; - } } /** @@ -3168,7 +3157,8 @@ ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, break; } - if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) { + if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw) && + !ice_fw_supports_report_dflt_cfg(pi->hw)) { struct ice_link_default_override_tlv tlv; if (ice_get_link_default_override(&tlv, pi)) From patchwork Fri Jan 8 04:35:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 86152 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C0D54A0524; Fri, 8 Jan 2021 05:32:12 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1434B140DFD; Fri, 8 Jan 2021 05:31:32 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 52FA9140E06 for ; Fri, 8 Jan 2021 05:31:29 +0100 (CET) IronPort-SDR: EQVtWs7kGOnrLWFEigJL8GmC6jWjXNfFojS/OyUSJh7xjwnV0U9udMxWz5Su2K4MEYwTcVw13T VoYJjaxuFW3g== X-IronPort-AV: E=McAfee;i="6000,8403,9857"; a="262309393" X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="262309393" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2021 20:31:29 -0800 IronPort-SDR: MWD6MHksjBLgMhfY5b6fhFBIIWESFw8ZxswHj33P6QSWJ8fb1Q107wuXTqzwQYHgLYU3qydm77 VXxpEJWr1UqQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="398858734" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga002.fm.intel.com with ESMTP; 07 Jan 2021 20:31:26 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: haiyue.wang@intel.com, jia.guo@intel.com, dev@dpdk.org, ferruh.yigit@intel.com, Qi Zhang , Junfeng Guo Date: Fri, 8 Jan 2021 12:35:05 +0800 Message-Id: <20210108043508.301227-7-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210108043508.301227-1-qi.z.zhang@intel.com> References: <20210108043508.301227-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 6/9] net/ice/base: support GTPU inner for AVF FDIR X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add dummy packets for IPV4_GTPU with inner IPV4/UDP/TCP with all kinds of GTPU (EH) type (i.e., IP/EH/DL/UL) for AVF FDIR. Signed-off-by: Junfeng Guo Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_fdir.c | 355 +++++++++++++++++++++++++++++--- drivers/net/ice/base/ice_type.h | 18 ++ 2 files changed, 342 insertions(+), 31 deletions(-) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index aa34075e6d..3037f81f72 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -57,6 +57,18 @@ static const u8 ice_fdir_udp4_vxlan_pkt[] = { 0x00, 0x00, 0x00, 0x00, }; +static const u8 ice_fdir_ipv4_gtpu4_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x38, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11, + 0x7c, 0xb2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x24, + 0xbf, 0xc0, 0x30, 0xff, 0x00, 0x14, 0x00, 0x00, + 0x00, 0x00, 0x45, 0x00, 0x00, 0x14, 0x00, 0x01, + 0x00, 0x00, 0x40, 0x00, 0x3a, 0x3d, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + static const u8 ice_fdir_udp4_gtpu4_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, @@ -88,6 +100,143 @@ static const u8 ice_fdir_tcp4_gtpu4_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; +static const u8 ice_fdir_ipv4_gtpu4_eh_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x44, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11, + 0x39, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x30, + 0x76, 0x6c, 0x34, 0xff, 0x00, 0x20, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, + 0x00, 0x14, 0x00, 0x01, 0x00, 0x00, 0x40, 0x00, + 0x3a, 0x3d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 ice_fdir_udp4_gtpu4_eh_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x4c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11, + 0x39, 0xf3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x38, + 0xb7, 0x1a, 0x34, 0xff, 0x00, 0x28, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, + 0x00, 0x1c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11, + 0x3a, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + 0xbe, 0xc7, 0x00, 0x00, +}; + +static const u8 ice_fdir_tcp4_gtpu4_eh_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x58, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11, + 0x39, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x44, + 0xb6, 0xf7, 0x34, 0xff, 0x00, 0x34, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, + 0x00, 0x28, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06, + 0x3a, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02, + 0x20, 0x00, 0x4e, 0xd2, 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 ice_fdir_ipv4_gtpu4_eh_dw_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x58, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11, + 0x39, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x44, + 0xb6, 0xf7, 0x34, 0xff, 0x00, 0x34, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, + 0x00, 0x28, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06, + 0x3a, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02, + 0x20, 0x00, 0x4e, 0xd2, 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 ice_fdir_udp4_gtpu4_eh_dw_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x4c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11, + 0x39, 0xf3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x38, + 0xb7, 0x1a, 0x34, 0xff, 0x00, 0x28, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, + 0x00, 0x1c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11, + 0x3a, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + 0xbe, 0xc7, 0x00, 0x00, +}; + +static const u8 ice_fdir_tcp4_gtpu4_eh_dw_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x58, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11, + 0x39, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x44, + 0xb6, 0xf7, 0x34, 0xff, 0x00, 0x34, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, + 0x00, 0x28, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06, + 0x3a, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02, + 0x20, 0x00, 0x4e, 0xd2, 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 ice_fdir_ipv4_gtpu4_eh_up_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x44, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11, + 0x39, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x30, + 0x76, 0x5c, 0x34, 0xff, 0x00, 0x20, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, + 0x00, 0x14, 0x00, 0x01, 0x00, 0x00, 0x40, 0x00, + 0x3a, 0x3d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 ice_fdir_udp4_gtpu4_eh_up_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x4c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11, + 0x39, 0xf3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x38, + 0xb7, 0x0a, 0x34, 0xff, 0x00, 0x28, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, + 0x00, 0x1c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11, + 0x3a, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + 0xbe, 0xc7, 0x00, 0x00, +}; + +static const u8 ice_fdir_tcp4_gtpu4_eh_up_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x58, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11, + 0x39, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x44, + 0xb6, 0xe7, 0x34, 0xff, 0x00, 0x34, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, + 0x00, 0x28, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06, + 0x3a, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02, + 0x20, 0x00, 0x4e, 0xd2, 0x00, 0x00, 0x00, 0x00, +}; + static const u8 ice_fdir_icmp4_gtpu4_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, @@ -103,68 +252,78 @@ static const u8 ice_fdir_icmp4_gtpu4_pkt[] = { 0x00, 0x00, }; -static const u8 ice_fdir_ipv4_gtpu4_pkt[] = { +static const u8 ice_fdir_ipv6_gtpu6_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00, + 0x00, 0x00, 0x00, 0x38, 0x11, 0x40, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x68, + 0x08, 0x68, 0x00, 0x38, 0x22, 0x43, 0x30, 0xff, + 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x3b, 0x40, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, - 0x00, 0x44, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x00, - 0x00, 0x00, 0x33, 0xff, 0x00, 0x20, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x45, 0x00, - 0x00, 0x14, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, }; -static const u8 ice_fdir_ipv6_gtpu6_pkt[] = { +static const u8 ice_fdir_ipv6_gtpu6_eh_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00, 0x00, 0x00, 0x00, 0x44, 0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x08, 0x68, - 0x08, 0x68, 0x00, 0x44, 0x7f, 0xed, 0x33, 0xff, - 0x00, 0x34, 0x12, 0x34, 0x56, 0x78, 0x00, 0x00, - 0x00, 0x85, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x68, + 0x08, 0x68, 0x00, 0x44, 0x1b, 0x9a, 0x34, 0xff, + 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x85, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, }; -static const u8 ice_fdir_ipv4_gtpu4_eh_pkt[] = { +static const u8 ice_fdir_ipv6_gtpu6_eh_dw_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, - 0x00, 0x44, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11, + 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00, + 0x00, 0x00, 0x00, 0x44, 0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x00, - 0x00, 0x00, 0x34, 0xff, 0x00, 0x28, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x02, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, - 0x00, 0x14, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x68, + 0x08, 0x68, 0x00, 0x44, 0x1b, 0x9a, 0x34, 0xff, + 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x85, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x3b, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, }; -static const u8 ice_fdir_ipv6_gtpu6_eh_pkt[] = { +static const u8 ice_fdir_ipv6_gtpu6_eh_up_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00, 0x00, 0x00, 0x00, 0x44, 0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x08, 0x68, - 0x08, 0x68, 0x00, 0x44, 0x7f, 0xed, 0x34, 0xff, - 0x00, 0x34, 0x12, 0x34, 0x56, 0x78, 0x00, 0x00, - 0x00, 0x85, 0x02, 0x00, 0x33, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x68, + 0x08, 0x68, 0x00, 0x44, 0x1b, 0x8a, 0x34, 0xff, + 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x85, 0x02, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, }; static const u8 ice_fdir_ipv4_l2tpv3_pkt[] = { @@ -520,6 +679,41 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = { sizeof(ice_fdir_ipv4_pkt), ice_fdir_ipv4_pkt, sizeof(ice_fdir_ip4_tun_pkt), ice_fdir_ip4_tun_pkt, }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU, + sizeof(ice_fdir_ipv4_gtpu4_pkt), + ice_fdir_ipv4_gtpu4_pkt, + sizeof(ice_fdir_ipv4_gtpu4_pkt), + ice_fdir_ipv4_gtpu4_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH, + sizeof(ice_fdir_ipv4_gtpu4_eh_pkt), + ice_fdir_ipv4_gtpu4_eh_pkt, + sizeof(ice_fdir_ipv4_gtpu4_eh_pkt), + ice_fdir_ipv4_gtpu4_eh_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW, + sizeof(ice_fdir_ipv4_gtpu4_eh_dw_pkt), + ice_fdir_ipv4_gtpu4_eh_dw_pkt, + sizeof(ice_fdir_ipv4_gtpu4_eh_dw_pkt), + ice_fdir_ipv4_gtpu4_eh_dw_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP, + sizeof(ice_fdir_ipv4_gtpu4_eh_up_pkt), + ice_fdir_ipv4_gtpu4_eh_up_pkt, + sizeof(ice_fdir_ipv4_gtpu4_eh_up_pkt), + ice_fdir_ipv4_gtpu4_eh_up_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4, + sizeof(ice_fdir_ipv4_gtpu4_pkt), + ice_fdir_ipv4_gtpu4_pkt, + sizeof(ice_fdir_ipv4_gtpu4_pkt), + ice_fdir_ipv4_gtpu4_pkt, + }, { ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP, sizeof(ice_fdir_udp4_gtpu4_pkt), @@ -534,6 +728,69 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = { sizeof(ice_fdir_tcp4_gtpu4_pkt), ice_fdir_tcp4_gtpu4_pkt, }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4, + sizeof(ice_fdir_ipv4_gtpu4_eh_pkt), + ice_fdir_ipv4_gtpu4_eh_pkt, + sizeof(ice_fdir_ipv4_gtpu4_eh_pkt), + ice_fdir_ipv4_gtpu4_eh_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_UDP, + sizeof(ice_fdir_udp4_gtpu4_eh_pkt), + ice_fdir_udp4_gtpu4_eh_pkt, + sizeof(ice_fdir_udp4_gtpu4_eh_pkt), + ice_fdir_udp4_gtpu4_eh_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_TCP, + sizeof(ice_fdir_tcp4_gtpu4_eh_pkt), + ice_fdir_tcp4_gtpu4_eh_pkt, + sizeof(ice_fdir_tcp4_gtpu4_eh_pkt), + ice_fdir_tcp4_gtpu4_eh_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4, + sizeof(ice_fdir_ipv4_gtpu4_eh_dw_pkt), + ice_fdir_ipv4_gtpu4_eh_dw_pkt, + sizeof(ice_fdir_ipv4_gtpu4_eh_dw_pkt), + ice_fdir_ipv4_gtpu4_eh_dw_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_UDP, + sizeof(ice_fdir_udp4_gtpu4_eh_dw_pkt), + ice_fdir_udp4_gtpu4_eh_dw_pkt, + sizeof(ice_fdir_udp4_gtpu4_eh_dw_pkt), + ice_fdir_udp4_gtpu4_eh_dw_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_TCP, + sizeof(ice_fdir_tcp4_gtpu4_eh_dw_pkt), + ice_fdir_tcp4_gtpu4_eh_dw_pkt, + sizeof(ice_fdir_tcp4_gtpu4_eh_dw_pkt), + ice_fdir_tcp4_gtpu4_eh_dw_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4, + sizeof(ice_fdir_ipv4_gtpu4_eh_up_pkt), + ice_fdir_ipv4_gtpu4_eh_up_pkt, + sizeof(ice_fdir_ipv4_gtpu4_eh_up_pkt), + ice_fdir_ipv4_gtpu4_eh_up_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_UDP, + sizeof(ice_fdir_udp4_gtpu4_eh_up_pkt), + ice_fdir_udp4_gtpu4_eh_up_pkt, + sizeof(ice_fdir_udp4_gtpu4_eh_up_pkt), + ice_fdir_udp4_gtpu4_eh_up_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_TCP, + sizeof(ice_fdir_tcp4_gtpu4_eh_up_pkt), + ice_fdir_tcp4_gtpu4_eh_up_pkt, + sizeof(ice_fdir_tcp4_gtpu4_eh_up_pkt), + ice_fdir_tcp4_gtpu4_eh_up_pkt, + }, { ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP, sizeof(ice_fdir_icmp4_gtpu4_pkt), @@ -548,6 +805,34 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = { sizeof(ice_fdir_ipv4_gtpu4_pkt), ice_fdir_ipv4_gtpu4_pkt, }, + { + ICE_FLTR_PTYPE_NONF_IPV6_GTPU, + sizeof(ice_fdir_ipv6_gtpu6_pkt), + ice_fdir_ipv6_gtpu6_pkt, + sizeof(ice_fdir_ipv6_gtpu6_pkt), + ice_fdir_ipv6_gtpu6_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH, + sizeof(ice_fdir_ipv6_gtpu6_eh_pkt), + ice_fdir_ipv6_gtpu6_eh_pkt, + sizeof(ice_fdir_ipv6_gtpu6_eh_pkt), + ice_fdir_ipv6_gtpu6_eh_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_DW, + sizeof(ice_fdir_ipv6_gtpu6_eh_dw_pkt), + ice_fdir_ipv6_gtpu6_eh_dw_pkt, + sizeof(ice_fdir_ipv6_gtpu6_eh_dw_pkt), + ice_fdir_ipv6_gtpu6_eh_dw_pkt, + }, + { + ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_UP, + sizeof(ice_fdir_ipv6_gtpu6_eh_up_pkt), + ice_fdir_ipv6_gtpu6_eh_up_pkt, + sizeof(ice_fdir_ipv6_gtpu6_eh_up_pkt), + ice_fdir_ipv6_gtpu6_eh_up_pkt, + }, { ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER, sizeof(ice_fdir_ipv6_gtpu6_pkt), @@ -1205,6 +1490,7 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, ice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac); ice_pkt_insert_mac_addr(loc + ETH_ALEN, input->ext_data.src_mac); break; + case ICE_FLTR_PTYPE_NONF_IPV4_GTPU: case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER: ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET, input->ip.v4.src_ip); @@ -1213,6 +1499,9 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, ice_pkt_insert_u32(loc, ICE_IPV4_GTPU_TEID_OFFSET, input->gtpu_data.teid); break; + case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH: + case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW: + case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP: case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP: case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP: case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP: @@ -1226,6 +1515,7 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, ice_pkt_insert_u6_qfi(loc, ICE_IPV4_GTPU_QFI_OFFSET, input->gtpu_data.qfi); break; + case ICE_FLTR_PTYPE_NONF_IPV6_GTPU: case ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER: ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, input->ip.v6.src_ip); @@ -1234,6 +1524,9 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, ice_pkt_insert_u32(loc, ICE_IPV6_GTPU_TEID_OFFSET, input->gtpu_data.teid); break; + case ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH: + case ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_DW: + case ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_UP: case ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_IPV6_OTHER: ice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET, input->ip.v6.src_ip); diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 86e93c34a1..ce232cd958 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -304,8 +304,26 @@ enum ice_fltr_ptype { ICE_FLTR_PTYPE_NONF_IPV4_TCP, ICE_FLTR_PTYPE_NONF_IPV4_SCTP, ICE_FLTR_PTYPE_NONF_IPV4_OTHER, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP, + ICE_FLTR_PTYPE_NONF_IPV6_GTPU, + ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH, + ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_DW, + ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_UP, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4, ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP, ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_UDP, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_TCP, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_UDP, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_TCP, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_UDP, + ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_TCP, ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP, ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER, ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER, From patchwork Fri Jan 8 04:35:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 86153 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C63B9A0524; Fri, 8 Jan 2021 05:32:20 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3E0AC140E10; Fri, 8 Jan 2021 05:31:33 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 3D6B8140DFD for ; Fri, 8 Jan 2021 05:31:31 +0100 (CET) IronPort-SDR: drZ+6I+1e+v0NMe8s4ykGTwMcrgr0bkShBbKx0OqkEWjZFFkadwlB1/YkdMV95mmDgNEN6MTCN +Da7VpM2LMgw== X-IronPort-AV: E=McAfee;i="6000,8403,9857"; a="262309395" X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="262309395" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2021 20:31:30 -0800 IronPort-SDR: pgYu9ncTDo10w8PqQwmTaRU6oC0SQXZwAuG9qsCxGs1/KCi3eZLwhPwPDvUhX680lOx4+fF+d9 TJ0Og4FlDlXg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="398858740" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga002.fm.intel.com with ESMTP; 07 Jan 2021 20:31:29 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: haiyue.wang@intel.com, jia.guo@intel.com, dev@dpdk.org, ferruh.yigit@intel.com, Qi Zhang , Bruce Allan Date: Fri, 8 Jan 2021 12:35:06 +0800 Message-Id: <20210108043508.301227-8-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210108043508.301227-1-qi.z.zhang@intel.com> References: <20210108043508.301227-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 7/9] net/ice/base: cleanup style issues X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" A few style issues reported by checkpatch have snuck into the code, resolve the style issues. PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses Signed-off-by: Bruce Allan Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_controlq.h | 4 ++-- drivers/net/ice/base/ice_flex_type.h | 4 ++-- drivers/net/ice/base/ice_flow.c | 6 +++--- drivers/net/ice/base/ice_sched.c | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h index 161c1bebff..94e8bfcc98 100644 --- a/drivers/net/ice/base/ice_controlq.h +++ b/drivers/net/ice/base/ice_controlq.h @@ -15,8 +15,8 @@ (&(((struct ice_aq_desc *)((R).desc_buf.va))[i])) #define ICE_CTL_Q_DESC_UNUSED(R) \ - (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ - (R)->next_to_clean - (R)->next_to_use - 1) + ((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ + (R)->next_to_clean - (R)->next_to_use - 1)) /* Defines that help manage the driver vs FW API checks. * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage. diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h index 9b9503b3ba..53d396daef 100644 --- a/drivers/net/ice/base/ice_flex_type.h +++ b/drivers/net/ice/base/ice_flex_type.h @@ -670,8 +670,8 @@ struct ice_xlt1 { #define ICE_PF_NUM_S 13 #define ICE_PF_NUM_M (0x07 << ICE_PF_NUM_S) #define ICE_VSIG_VALUE(vsig, pf_id) \ - (u16)((((u16)(vsig)) & ICE_VSIG_IDX_M) | \ - (((u16)(pf_id) << ICE_PF_NUM_S) & ICE_PF_NUM_M)) + ((u16)((((u16)(vsig)) & ICE_VSIG_IDX_M) | \ + (((u16)(pf_id) << ICE_PF_NUM_S) & ICE_PF_NUM_M))) #define ICE_DEFAULT_VSIG 0 /* XLT2 Table */ diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 15b43061c8..ad31856777 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -3533,9 +3533,9 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof) * 3 for tunneled with outer ipv6 */ #define ICE_FLOW_GEN_PROFID(hash, hdr, encap) \ - (u64)(((u64)(hash) & ICE_FLOW_PROF_HASH_M) | \ - (((u64)(hdr) << ICE_FLOW_PROF_HDR_S) & ICE_FLOW_PROF_HDR_M) | \ - (((u64)(encap) << ICE_FLOW_PROF_ENCAP_S) & ICE_FLOW_PROF_ENCAP_M)) + ((u64)(((u64)(hash) & ICE_FLOW_PROF_HASH_M) | \ + (((u64)(hdr) << ICE_FLOW_PROF_HDR_S) & ICE_FLOW_PROF_HDR_M) | \ + (((u64)(encap) << ICE_FLOW_PROF_ENCAP_S) & ICE_FLOW_PROF_ENCAP_M))) static void ice_rss_config_xor_word(struct ice_hw *hw, u8 prof_id, u8 src, u8 dst) diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index 1cce8eaff1..53d76d17ee 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -4289,7 +4289,7 @@ ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node, ice_sched_rm_unused_rl_prof(hw); layer_num = ice_sched_get_rl_prof_layer(pi, rl_type, - node->tx_sched_layer); + node->tx_sched_layer); if (layer_num >= hw->num_tx_sched_layers) return ICE_ERR_PARAM; From patchwork Fri Jan 8 04:35:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 86154 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0C40AA0524; Fri, 8 Jan 2021 05:32:32 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2783D140E2B; Fri, 8 Jan 2021 05:31:35 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 4A2D4140E15; Fri, 8 Jan 2021 05:31:33 +0100 (CET) IronPort-SDR: FLlXa9uOxdWAeXLc8Z98k3UyuvJbx2Tl2hWNVOkZubpT9I6kgE+5AXC/v/BFWOK9y+XznN451U FMqH2MXtoCpw== X-IronPort-AV: E=McAfee;i="6000,8403,9857"; a="262309398" X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="262309398" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2021 20:31:33 -0800 IronPort-SDR: VxPiAlayFQ6IQAr4MOWzX4AoNca0uqpE9MT+08Ri4Za1lBtmwuCveiCZ777vKRv0ls/x3+ZDow JNocTHa19RcQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="398858760" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga002.fm.intel.com with ESMTP; 07 Jan 2021 20:31:31 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: haiyue.wang@intel.com, jia.guo@intel.com, dev@dpdk.org, ferruh.yigit@intel.com, Qi Zhang , stable@dpdk.org, Victor Raj Date: Fri, 8 Jan 2021 12:35:07 +0800 Message-Id: <20210108043508.301227-9-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210108043508.301227-1-qi.z.zhang@intel.com> References: <20210108043508.301227-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 8/9] net/ice/base: updated the add scheduler node counter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The number of nodes added counter was updated incorrectly. This issue was exposed when the driver tried to add more than 128 queues per TC. Fix added to update the counter correctly. Fixes: 93e84b1bfc92 ("net/ice/base: add basic Tx scheduler") Cc: stable@dpdk.org Signed-off-by: Victor Raj Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_sched.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index 53d76d17ee..7d4721e60c 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -1040,7 +1040,15 @@ ice_sched_add_nodes_to_layer(struct ice_port_info *pi, layer, new_num_nodes, first_teid_ptr, &num_added); - *num_nodes_added += num_added; + if (status == ICE_SUCCESS) + *num_nodes_added += num_added; + /* added more nodes than requested ? */ + if (*num_nodes_added > num_nodes) { + ice_debug(pi->hw, ICE_DBG_SCHED, "added extra nodes %d %d\n", num_nodes, + *num_nodes_added); + status = ICE_ERR_CFG; + break; + } /* break if all the nodes are added successfully */ if (status == ICE_SUCCESS && (*num_nodes_added == num_nodes)) break; @@ -1063,7 +1071,7 @@ ice_sched_add_nodes_to_layer(struct ice_port_info *pi, if (num_added) first_teid_ptr = &temp; - new_num_nodes = num_nodes - num_added; + new_num_nodes = num_nodes - *num_nodes_added; } } return status; From patchwork Fri Jan 8 04:35:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 86155 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 82845A0524; Fri, 8 Jan 2021 05:32:41 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5BF3F140E35; Fri, 8 Jan 2021 05:31:37 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 6B1F7140E31 for ; Fri, 8 Jan 2021 05:31:35 +0100 (CET) IronPort-SDR: 3oz1nXdfOskfWQVX0lrXAM5iyl77lWz76UeTfdEx8PGBzNv1EnpFQpK8Eos/A10GtKneJrJbT+ 0Y7rrag/2sfg== X-IronPort-AV: E=McAfee;i="6000,8403,9857"; a="262309401" X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="262309401" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2021 20:31:35 -0800 IronPort-SDR: Gka3twu3FiB1rkuk83J9yD7XF04J3bpX227iW5O+CdwMOXgbl1+NkTQrnB/YWKM8daqMlNZp7K GdxPnDO6fBcQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,330,1602572400"; d="scan'208";a="398858769" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga002.fm.intel.com with ESMTP; 07 Jan 2021 20:31:33 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: haiyue.wang@intel.com, jia.guo@intel.com, dev@dpdk.org, ferruh.yigit@intel.com, Qi Zhang Date: Fri, 8 Jan 2021 12:35:08 +0800 Message-Id: <20210108043508.301227-10-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210108043508.301227-1-qi.z.zhang@intel.com> References: <20210108043508.301227-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 9/9] net/ice/base: update Copyright date X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Updated the Copyright for 2021 Updated FreeBSD ice driver version. Signed-off-by: Qi Zhang --- drivers/net/ice/base/README | 4 ++-- drivers/net/ice/base/ice_acl.c | 2 +- drivers/net/ice/base/ice_acl.h | 2 +- drivers/net/ice/base/ice_acl_ctrl.c | 2 +- drivers/net/ice/base/ice_adminq_cmd.h | 2 +- drivers/net/ice/base/ice_alloc.h | 2 +- drivers/net/ice/base/ice_bitops.h | 2 +- drivers/net/ice/base/ice_common.c | 2 +- drivers/net/ice/base/ice_common.h | 2 +- drivers/net/ice/base/ice_controlq.c | 2 +- drivers/net/ice/base/ice_controlq.h | 2 +- drivers/net/ice/base/ice_dcb.c | 2 +- drivers/net/ice/base/ice_dcb.h | 2 +- drivers/net/ice/base/ice_devids.h | 2 +- drivers/net/ice/base/ice_fdir.c | 2 +- drivers/net/ice/base/ice_fdir.h | 2 +- drivers/net/ice/base/ice_flex_pipe.c | 2 +- drivers/net/ice/base/ice_flex_pipe.h | 2 +- drivers/net/ice/base/ice_flex_type.h | 2 +- drivers/net/ice/base/ice_flow.c | 2 +- drivers/net/ice/base/ice_flow.h | 2 +- drivers/net/ice/base/ice_hw_autogen.h | 2 +- drivers/net/ice/base/ice_lan_tx_rx.h | 2 +- drivers/net/ice/base/ice_nvm.c | 2 +- drivers/net/ice/base/ice_nvm.h | 2 +- drivers/net/ice/base/ice_osdep.h | 2 +- drivers/net/ice/base/ice_protocol_type.h | 2 +- drivers/net/ice/base/ice_sbq_cmd.h | 2 +- drivers/net/ice/base/ice_sched.c | 2 +- drivers/net/ice/base/ice_sched.h | 2 +- drivers/net/ice/base/ice_status.h | 2 +- drivers/net/ice/base/ice_switch.c | 2 +- drivers/net/ice/base/ice_switch.h | 2 +- drivers/net/ice/base/ice_type.h | 2 +- drivers/net/ice/base/ice_vlan_mode.c | 2 +- drivers/net/ice/base/ice_vlan_mode.h | 2 +- drivers/net/ice/base/meson.build | 2 +- 37 files changed, 38 insertions(+), 38 deletions(-) diff --git a/drivers/net/ice/base/README b/drivers/net/ice/base/README index 5229e5fe7d..bc42736bdd 100644 --- a/drivers/net/ice/base/README +++ b/drivers/net/ice/base/README @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2020 Intel Corporation + * Copyright(c) 2020-2021 Intel Corporation */ Intel® ICE driver ================== This directory contains source code of FreeBSD ice driver of version -2020.10.21 released by the team which develops +2021.01.07 released by the team which develops basic drivers for any ice NIC. The directory of base/ contains the original source package. This driver is valid for the product(s) listed below diff --git a/drivers/net/ice/base/ice_acl.c b/drivers/net/ice/base/ice_acl.c index 763cd2af9e..6e1d1ad393 100644 --- a/drivers/net/ice/base/ice_acl.c +++ b/drivers/net/ice/base/ice_acl.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #include "ice_acl.h" diff --git a/drivers/net/ice/base/ice_acl.h b/drivers/net/ice/base/ice_acl.h index 21aa5088f7..a63b90faf8 100644 --- a/drivers/net/ice/base/ice_acl.h +++ b/drivers/net/ice/base/ice_acl.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_ACL_H_ diff --git a/drivers/net/ice/base/ice_acl_ctrl.c b/drivers/net/ice/base/ice_acl_ctrl.c index 3c4d45cc0d..27aa6b62d4 100644 --- a/drivers/net/ice/base/ice_acl_ctrl.c +++ b/drivers/net/ice/base/ice_acl_ctrl.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #include "ice_acl.h" diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index cb9924562a..09d0f176c9 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_ADMINQ_CMD_H_ diff --git a/drivers/net/ice/base/ice_alloc.h b/drivers/net/ice/base/ice_alloc.h index cfe9199403..7fca491ac6 100644 --- a/drivers/net/ice/base/ice_alloc.h +++ b/drivers/net/ice/base/ice_alloc.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_ALLOC_H_ diff --git a/drivers/net/ice/base/ice_bitops.h b/drivers/net/ice/base/ice_bitops.h index b786bf7a18..21ec2014e1 100644 --- a/drivers/net/ice/base/ice_bitops.h +++ b/drivers/net/ice/base/ice_bitops.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_BITOPS_H_ diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index b71feb3476..d3178240b2 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index ba56f82ad8..5b720c3b09 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_COMMON_H_ diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c index 59e7c5f88d..93f7bc0274 100644 --- a/drivers/net/ice/base/ice_controlq.c +++ b/drivers/net/ice/base/ice_controlq.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h index 94e8bfcc98..0d54e713ca 100644 --- a/drivers/net/ice/base/ice_controlq.h +++ b/drivers/net/ice/base/ice_controlq.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_CONTROLQ_H_ diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c index 351038528b..7a85e56abf 100644 --- a/drivers/net/ice/base/ice_dcb.c +++ b/drivers/net/ice/base/ice_dcb.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_dcb.h b/drivers/net/ice/base/ice_dcb.h index 8f0e09d50a..658211966d 100644 --- a/drivers/net/ice/base/ice_dcb.h +++ b/drivers/net/ice/base/ice_dcb.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_DCB_H_ diff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h index 84028e9906..93110055e2 100644 --- a/drivers/net/ice/base/ice_devids.h +++ b/drivers/net/ice/base/ice_devids.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_DEVIDS_H_ diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index 3037f81f72..500b081e54 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index e13863935d..37875cb94a 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_FDIR_H_ diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 427b688535..31047d1eda 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h index 066ff95e13..58e3c1d1ec 100644 --- a/drivers/net/ice/base/ice_flex_pipe.h +++ b/drivers/net/ice/base/ice_flex_pipe.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_FLEX_PIPE_H_ diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h index 53d396daef..ad620f7892 100644 --- a/drivers/net/ice/base/ice_flex_type.h +++ b/drivers/net/ice/base/ice_flex_type.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_FLEX_TYPE_H_ diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index ad31856777..a081fbe5a4 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h index 6d02252ecf..c3bce13194 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_FLOW_H_ diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h index 572f481b7b..cbca4b0629 100644 --- a/drivers/net/ice/base/ice_hw_autogen.h +++ b/drivers/net/ice/base/ice_hw_autogen.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ /* Machine-generated file; do not edit */ diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h index ec0c9f3ab0..107826acd0 100644 --- a/drivers/net/ice/base/ice_lan_tx_rx.h +++ b/drivers/net/ice/base/ice_lan_tx_rx.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_LAN_TX_RX_H_ diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index 45310bfc6b..aeb4da9ed1 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h index 48b71950e9..af18344cf8 100644 --- a/drivers/net/ice/base/ice_nvm.h +++ b/drivers/net/ice/base/ice_nvm.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_NVM_H_ diff --git a/drivers/net/ice/base/ice_osdep.h b/drivers/net/ice/base/ice_osdep.h index c0f1e77257..46ac868349 100644 --- a/drivers/net/ice/base/ice_osdep.h +++ b/drivers/net/ice/base/ice_osdep.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2018-2020 Intel Corporation + * Copyright(c) 2018-2021 Intel Corporation */ #ifndef _ICE_OSDEP_H_ diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index 3c10264761..d769ad0580 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_PROTOCOL_TYPE_H_ diff --git a/drivers/net/ice/base/ice_sbq_cmd.h b/drivers/net/ice/base/ice_sbq_cmd.h index 22bfcebc3c..a5fe43bf26 100644 --- a/drivers/net/ice/base/ice_sbq_cmd.h +++ b/drivers/net/ice/base/ice_sbq_cmd.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_SBQ_CMD_H_ diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index 7d4721e60c..38d1f2cc54 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #include "ice_sched.h" diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h index 8b275637a4..1441b5f191 100644 --- a/drivers/net/ice/base/ice_sched.h +++ b/drivers/net/ice/base/ice_sched.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_SCHED_H_ diff --git a/drivers/net/ice/base/ice_status.h b/drivers/net/ice/base/ice_status.h index 3ca1b5db71..9df878be01 100644 --- a/drivers/net/ice/base/ice_status.h +++ b/drivers/net/ice/base/ice_status.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_STATUS_H_ diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index fd2c1ccceb..692a147e66 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #include "ice_switch.h" diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index a3c4713f5e..c11c064725 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_SWITCH_H_ diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index ce232cd958..8d259397a6 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_TYPE_H_ diff --git a/drivers/net/ice/base/ice_vlan_mode.c b/drivers/net/ice/base/ice_vlan_mode.c index 363354ff3f..503c6c1b28 100644 --- a/drivers/net/ice/base/ice_vlan_mode.c +++ b/drivers/net/ice/base/ice_vlan_mode.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #include "ice_vlan_mode.h" diff --git a/drivers/net/ice/base/ice_vlan_mode.h b/drivers/net/ice/base/ice_vlan_mode.h index 1b9db4d36f..fc1069fb6b 100644 --- a/drivers/net/ice/base/ice_vlan_mode.h +++ b/drivers/net/ice/base/ice_vlan_mode.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2020 Intel Corporation + * Copyright(c) 2001-2021 Intel Corporation */ #ifndef _ICE_VLAN_MODE_H_ diff --git a/drivers/net/ice/base/meson.build b/drivers/net/ice/base/meson.build index ad5e5da25b..b82d05fe73 100644 --- a/drivers/net/ice/base/meson.build +++ b/drivers/net/ice/base/meson.build @@ -1,5 +1,5 @@ # SPDX-License-Identifier: BSD-3-Clause -# Copyright(c) 2018-2020 Intel Corporation +# Copyright(c) 2018-2021 Intel Corporation sources = [ 'ice_controlq.c',