From patchwork Fri Apr 30 13:59:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 92547 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D807AA0546; Fri, 30 Apr 2021 15:58:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A6E6D411C4; Fri, 30 Apr 2021 15:55:44 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id E91D541132 for ; Fri, 30 Apr 2021 15:55:41 +0200 (CEST) IronPort-SDR: LzNIwGoS3dGgXq1N2j1b9bjyMcuUp5Zk1OnK/xbWuCFvfeFZ/fW3b74RW+TMJCLgaAPG7serzi 6zjABx7SMfWQ== X-IronPort-AV: E=McAfee;i="6200,9189,9970"; a="218021262" X-IronPort-AV: E=Sophos;i="5.82,262,1613462400"; d="scan'208";a="218021262" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2021 06:55:41 -0700 IronPort-SDR: oe9uLyGO4ZwunjChb2qmC8R3o3gDaAFZBx9nKteRCULTZDs4VBUmGA6lcjSD5kZqn4Cp0xAqXB vg+6AQvuwB+g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,262,1613462400"; d="scan'208";a="459443755" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga002.fm.intel.com with ESMTP; 30 Apr 2021 06:55:40 -0700 From: Qi Zhang To: ferruh.yigit@intel.com Cc: qiming.yang@intel.com, dev@dpdk.org, Qi Zhang , Ting Xu , Jeff Guo Date: Fri, 30 Apr 2021 21:59:17 +0800 Message-Id: <20210430135922.2990103-2-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210430135922.2990103-1-qi.z.zhang@intel.com> References: <20210429004143.2921260-1-qi.z.zhang@intel.com> <20210430135922.2990103-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 1/6] net/ice/base: add IP fragment flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add the IPv6 fragment flags and the IPv4 fragment field shift. Signed-off-by: Ting Xu Signed-off-by: Jeff Guo Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_fdir.c | 2 +- drivers/net/ice/base/ice_fdir.h | 16 ++++++++++++---- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index 8f9c0d346b..f6a6ff3831 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -1505,7 +1505,7 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, ice_pkt_insert_u8(loc, ICE_IPV4_TTL_OFFSET, input->ip.v4.ttl); ice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac); if (frag) - loc[20] = ICE_FDIR_IPV4_PKT_FLAG_DF; + loc[20] = ICE_FDIR_IPV4_PKT_FLAG_MF; break; case ICE_FLTR_PTYPE_NONF_IPV4_UDP: ice_pkt_insert_mac_addr(pkt, input->ext_data_outer.dst_mac); diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index 6573f96bc1..b679a8a1bd 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -83,12 +83,20 @@ #define ICE_FDIR_MAX_FLTRS 16384 -/* IP v4 has 2 flag bits that enable fragment processing: DF and MF. DF +/* IPv4 has 2 flag bits that enable fragment processing: DF and MF. DF * requests that the packet not be fragmented. MF indicates that a packet has - * been fragmented. + * been fragmented, except that for the last fragment has a non-zero + * Fragment Offset field with zero MF. */ -#define ICE_FDIR_IPV4_PKT_FLAG_DF 0x20 -#define ICE_FDIR_IPV4_PKT_FLAG_MF 0x40 +#define ICE_FDIR_IPV4_PKT_FLAG_MF 0x20 +#define ICE_FDIR_IPV4_PKT_FLAG_MF_SHIFT 8 +#define ICE_FDIR_IPV4_PKT_FLAG_DF 0x40 + +/* For IPv6 fragmented packets, all fragments except the last have + * the MF flag set. + */ +#define ICE_FDIR_IPV6_PKT_FLAG_MF 0x100 +#define ICE_FDIR_IPV6_PKT_FLAG_MF_SHIFT 8 enum ice_fltr_prgm_desc_dest { ICE_FLTR_PRGM_DESC_DEST_DROP_PKT, From patchwork Fri Apr 30 13:59:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 92548 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B5437A0546; Fri, 30 Apr 2021 15:58:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CB88841297; Fri, 30 Apr 2021 15:55:45 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 80AC141133 for ; Fri, 30 Apr 2021 15:55:43 +0200 (CEST) IronPort-SDR: 2IEFHnwoUVDrNQxNA9XJbgGCYU9J6/uTFEOlDg1CO7/10jvq4g4AqLWT5UDp5Vmbu5Hs6PAPyM /A9rHtFn7uMQ== X-IronPort-AV: E=McAfee;i="6200,9189,9970"; a="218021268" X-IronPort-AV: E=Sophos;i="5.82,262,1613462400"; d="scan'208";a="218021268" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2021 06:55:43 -0700 IronPort-SDR: 121oHpkrebB/6bGT8DZ2oC/fmHGPgflpxAQCG6UgRsfyLXUVh5dqmqihHl5cVBEOsUZANI8qq2 nBSaMdpWSS+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,262,1613462400"; d="scan'208";a="459443765" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga002.fm.intel.com with ESMTP; 30 Apr 2021 06:55:41 -0700 From: Qi Zhang To: ferruh.yigit@intel.com Cc: qiming.yang@intel.com, dev@dpdk.org, Qi Zhang , Brett Creeley Date: Fri, 30 Apr 2021 21:59:18 +0800 Message-Id: <20210430135922.2990103-3-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210430135922.2990103-1-qi.z.zhang@intel.com> References: <20210429004143.2921260-1-qi.z.zhang@intel.com> <20210430135922.2990103-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 2/6] net/ice/base: add function for post DDP download VLAN mode configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently it's not clear that only the first PF downloads the package and configures the VLAN mode. When this is happening all other PFs are blocked on the global configuration lock. Once the package is successfully downloaded and the global configuration lock has been released then all PFs resume initialization. This includes some post package download VLAN mode configuration. To make this more obvious add the new function ice_post_pkg_dwnld_vlan_mode_cfg() so any/all post download VLAN mode configuration code can be put in here. This also makes it more clear that all PFs will call this new function. Signed-off-by: Brett Creeley Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_flex_pipe.c | 5 +---- drivers/net/ice/base/ice_vlan_mode.c | 23 ++++++++++++++++++++++- drivers/net/ice/base/ice_vlan_mode.h | 2 +- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index b489c8ddb2..b3cea731f3 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -1242,10 +1242,7 @@ ice_download_pkg(struct ice_hw *hw, struct ice_seg *ice_seg) status = ice_dwnld_cfg_bufs(hw, ice_buf_tbl->buf_array, LE32_TO_CPU(ice_buf_tbl->buf_count)); - ice_cache_vlan_mode(hw); - - if (ice_is_dvm_ena(hw)) - ice_change_proto_id_to_dvm(); + ice_post_pkg_dwnld_vlan_mode_cfg(hw); return status; } diff --git a/drivers/net/ice/base/ice_vlan_mode.c b/drivers/net/ice/base/ice_vlan_mode.c index ce150009c2..0a035ad4ab 100644 --- a/drivers/net/ice/base/ice_vlan_mode.c +++ b/drivers/net/ice/base/ice_vlan_mode.c @@ -124,7 +124,7 @@ bool ice_is_dvm_ena(struct ice_hw *hw) * configuration lock has been released because all ports on a device need to * cache the VLAN mode. */ -void ice_cache_vlan_mode(struct ice_hw *hw) +static void ice_cache_vlan_mode(struct ice_hw *hw) { hw->dvm_ena = ice_aq_is_dvm_ena(hw) ? true : false; } @@ -374,3 +374,24 @@ enum ice_status ice_set_vlan_mode(struct ice_hw *hw) return ice_set_svm(hw); } + +/** + * ice_post_pkg_dwnld_vlan_mode_cfg - configure VLAN mode after DDP download + * @hw: pointer to the HW structure + * + * This function is meant to configure any VLAN mode specific functionality + * after the global configuration lock has been released and the DDP has been + * downloaded. + * + * Since only one PF downloads the DDP and configures the VLAN mode there needs + * to be a way to configure the other PFs after the DDP has been downloaded and + * the global configuration lock has been released. All such code should go in + * this function. + */ +void ice_post_pkg_dwnld_vlan_mode_cfg(struct ice_hw *hw) +{ + ice_cache_vlan_mode(hw); + + if (ice_is_dvm_ena(hw)) + ice_change_proto_id_to_dvm(); +} diff --git a/drivers/net/ice/base/ice_vlan_mode.h b/drivers/net/ice/base/ice_vlan_mode.h index e9f13e7814..0e41b84000 100644 --- a/drivers/net/ice/base/ice_vlan_mode.h +++ b/drivers/net/ice/base/ice_vlan_mode.h @@ -10,7 +10,7 @@ struct ice_hw; bool ice_is_dvm_ena(struct ice_hw *hw); -void ice_cache_vlan_mode(struct ice_hw *hw); enum ice_status ice_set_vlan_mode(struct ice_hw *hw); +void ice_post_pkg_dwnld_vlan_mode_cfg(struct ice_hw *hw); #endif /* _ICE_VLAN_MODE_H */ From patchwork Fri Apr 30 13:59:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 92549 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9BDD7A0546; Fri, 30 Apr 2021 15:58:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1C68A412C5; Fri, 30 Apr 2021 15:55:49 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 2974041263 for ; Fri, 30 Apr 2021 15:55:45 +0200 (CEST) IronPort-SDR: CoJIFvddGYfjBjfkpJ+X7r5XlLcsHbfmJvl2Tg1PTgPKyn3GS7tbPh8f1kOVOl+TL626fSkO7a B7bc9dVBR2eA== X-IronPort-AV: E=McAfee;i="6200,9189,9970"; a="218021269" X-IronPort-AV: E=Sophos;i="5.82,262,1613462400"; d="scan'208";a="218021269" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2021 06:55:44 -0700 IronPort-SDR: HSGQrhDtDcpIUVVoYGlG/o4snt+eogyCj7ko0ZLuVNfq0DOVcVLJFBU+vfuJW4miHYs0iZJ1Ty iW6t/a32b+Hg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,262,1613462400"; d="scan'208";a="459443774" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga002.fm.intel.com with ESMTP; 30 Apr 2021 06:55:43 -0700 From: Qi Zhang To: ferruh.yigit@intel.com Cc: qiming.yang@intel.com, dev@dpdk.org, Qi Zhang , Brett Creeley Date: Fri, 30 Apr 2021 21:59:19 +0800 Message-Id: <20210430135922.2990103-4-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210430135922.2990103-1-qi.z.zhang@intel.com> References: <20210429004143.2921260-1-qi.z.zhang@intel.com> <20210430135922.2990103-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 3/6] net/ice/base: add print if DDP/FW don't support QinQ as expected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently if the driver supports QinQ there is no message/information if the DDP and/or FW don't support QinQ. Add functionality that prints if the DDP and/or FW don't support QinQ if the driver attempts to configured DVM. This will make it more obvious to users in the field that they need to update their DDP and/or FW. This required a small refactor so some of the existing code could be shared and used by this new print functionality. Signed-off-by: Brett Creeley Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_vlan_mode.c | 77 +++++++++++++++++++++++----- 1 file changed, 65 insertions(+), 12 deletions(-) diff --git a/drivers/net/ice/base/ice_vlan_mode.c b/drivers/net/ice/base/ice_vlan_mode.c index 0a035ad4ab..29c6509fc5 100644 --- a/drivers/net/ice/base/ice_vlan_mode.c +++ b/drivers/net/ice/base/ice_vlan_mode.c @@ -130,18 +130,11 @@ static void ice_cache_vlan_mode(struct ice_hw *hw) } /** - * ice_is_dvm_supported - check if Double VLAN Mode is supported - * @hw: pointer to the hardware structure - * - * Returns true if Double VLAN Mode (DVM) is supported and false if only Single - * VLAN Mode (SVM) is supported. In order for DVM to be supported the DDP and - * firmware must support it, otherwise only SVM is supported. This function - * should only be called while the global config lock is held and after the - * package has been successfully downloaded. + * ice_pkg_supports_dvm - find out if DDP supports DVM + * @hw: pointer to the HW structure */ -static bool ice_is_dvm_supported(struct ice_hw *hw) +static bool ice_pkg_supports_dvm(struct ice_hw *hw) { - struct ice_aqc_get_vlan_mode get_vlan_mode = { 0 }; enum ice_status status; bool pkg_supports_dvm; @@ -152,8 +145,17 @@ static bool ice_is_dvm_supported(struct ice_hw *hw) return false; } - if (!pkg_supports_dvm) - return false; + return pkg_supports_dvm; +} + +/** + * ice_fw_supports_dvm - find out if FW supports DVM + * @hw: pointer to the HW structure + */ +static bool ice_fw_supports_dvm(struct ice_hw *hw) +{ + struct ice_aqc_get_vlan_mode get_vlan_mode = { 0 }; + enum ice_status status; /* If firmware returns success, then it supports DVM, else it only * supports SVM @@ -168,6 +170,31 @@ static bool ice_is_dvm_supported(struct ice_hw *hw) return true; } +/** + * ice_is_dvm_supported - check if Double VLAN Mode is supported + * @hw: pointer to the hardware structure + * + * Returns true if Double VLAN Mode (DVM) is supported and false if only Single + * VLAN Mode (SVM) is supported. In order for DVM to be supported the DDP and + * firmware must support it, otherwise only SVM is supported. This function + * should only be called while the global config lock is held and after the + * package has been successfully downloaded. + */ +static bool ice_is_dvm_supported(struct ice_hw *hw) +{ + if (!ice_pkg_supports_dvm(hw)) { + ice_debug(hw, ICE_DBG_PKG, "DDP doesn't support DVM\n"); + return false; + } + + if (!ice_fw_supports_dvm(hw)) { + ice_debug(hw, ICE_DBG_PKG, "FW doesn't support DVM\n"); + return false; + } + + return true; +} + #define ICE_EXTERNAL_VLAN_ID_FV_IDX 11 #define ICE_SW_LKUP_VLAN_LOC_LKUP_IDX 1 #define ICE_SW_LKUP_VLAN_PKT_FLAGS_LKUP_IDX 2 @@ -375,6 +402,30 @@ enum ice_status ice_set_vlan_mode(struct ice_hw *hw) return ice_set_svm(hw); } +/** + * ice_print_dvm_not_supported - print if DDP and/or FW doesn't support DVM + * @hw: pointer to the HW structure + * + * The purpose of this function is to print that QinQ is not supported due to + * incompatibilty from the DDP and/or FW. This will give a hint to the user to + * update one and/or both components if they expect QinQ functionality. + */ +static void ice_print_dvm_not_supported(struct ice_hw *hw) +{ + bool pkg_supports_dvm = ice_pkg_supports_dvm(hw); + bool fw_supports_dvm = ice_fw_supports_dvm(hw); + + if (!fw_supports_dvm && !pkg_supports_dvm) + ice_info(hw, "QinQ functionality cannot be enabled on this device. " + "Update your DDP package and NVM to versions that support QinQ.\n"); + else if (!pkg_supports_dvm) + ice_info(hw, "QinQ functionality cannot be enabled on this device. " + "Update your DDP package to a version that supports QinQ.\n"); + else if (!fw_supports_dvm) + ice_info(hw, "QinQ functionality cannot be enabled on this device. " + "Update your NVM to a version that supports QinQ.\n"); +} + /** * ice_post_pkg_dwnld_vlan_mode_cfg - configure VLAN mode after DDP download * @hw: pointer to the HW structure @@ -394,4 +445,6 @@ void ice_post_pkg_dwnld_vlan_mode_cfg(struct ice_hw *hw) if (ice_is_dvm_ena(hw)) ice_change_proto_id_to_dvm(); + else + ice_print_dvm_not_supported(hw); } From patchwork Fri Apr 30 13:59:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 92550 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 78B24A0546; Fri, 30 Apr 2021 15:58:19 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5074C41375; Fri, 30 Apr 2021 15:55:50 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id F28A6412BC for ; Fri, 30 Apr 2021 15:55:46 +0200 (CEST) IronPort-SDR: DkIMIZxMCIIikDvdB3XZWDlViCldoZH79yNgMW9D/t90iYBRPC59DnzVJBoIcks0NLUIBQZ1zR vDFtUxW5ZF6Q== X-IronPort-AV: E=McAfee;i="6200,9189,9970"; a="218021272" X-IronPort-AV: E=Sophos;i="5.82,262,1613462400"; d="scan'208";a="218021272" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2021 06:55:46 -0700 IronPort-SDR: T2xutsHQNL7M1pKTaEfKkMck82v/poXsLR0kAa8PzDeIounUYhV8shml/IAwAM5FUHWFPNM/ss 9ayU9zY+rbHg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,262,1613462400"; d="scan'208";a="459443786" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga002.fm.intel.com with ESMTP; 30 Apr 2021 06:55:45 -0700 From: Qi Zhang To: ferruh.yigit@intel.com Cc: qiming.yang@intel.com, dev@dpdk.org, Qi Zhang , Dave Ertman , Anirudh Venkataramanan Date: Fri, 30 Apr 2021 21:59:20 +0800 Message-Id: <20210430135922.2990103-5-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210430135922.2990103-1-qi.z.zhang@intel.com> References: <20210429004143.2921260-1-qi.z.zhang@intel.com> <20210430135922.2990103-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 4/6] net/ice/base: support L3 DSCP QoS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The base code support to build configuration TLVs in DSCP mode has not been implemented before, so the functions to do so and the flow control to determine if we are in VLAN or DSCP mode need to be added. The current value for maximum number of DCB APPs (ICE_DCBX_MAX_APPS) is not sufficient when supporting DSCP mode. Each DSCP->TC mapping will come in as a single APP value. So, there can be up to 64 APPs for DSCP mapping. Need to keep track of the current DSCP to TC mapping so that TLVs can be built up to send to the FW. Add an u8 array to hold this info. A u64 is also needed to keep track of the DSCP values that have had an APP submitted to map its value to a TC. Since it would be unwise to allow an APP to be overwritten by subsequent APPs, reject mappings for a DSCP value that already has a user mapped value. This will allow us to easily track which DSCP values have been mapped, and when the last one has been deleted. Signed-off-by: Dave Ertman Signed-off-by: Anirudh Venkataramanan Signed-off-by: Qi Zhang Acked-by: Qi Zhang --- drivers/net/ice/base/ice_dcb.c | 185 +++++++++++++++++++++++++++++--- drivers/net/ice/base/ice_dcb.h | 16 +++ drivers/net/ice/base/ice_type.h | 10 +- 3 files changed, 194 insertions(+), 17 deletions(-) diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c index d5e2cb6e5d..0aaa5ae8c1 100644 --- a/drivers/net/ice/base/ice_dcb.c +++ b/drivers/net/ice/base/ice_dcb.c @@ -1207,7 +1207,140 @@ ice_add_ieee_app_pri_tlv(struct ice_lldp_org_tlv *tlv, } /** - * ice_add_dcb_tlv - Add all IEEE TLVs + * ice_add_dscp_up_tlv - Prepare DSCP to UP TLV + * @tlv: location to build the TLV data + * @dcbcfg: location of data to convert to TLV + */ +static void +ice_add_dscp_up_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg) +{ + u8 *buf = tlv->tlvinfo; + u32 ouisubtype; + u16 typelen; + int i; + + typelen = ((ICE_TLV_TYPE_ORG << ICE_LLDP_TLV_TYPE_S) | + ICE_DSCP_UP_TLV_LEN); + tlv->typelen = HTONS(typelen); + + ouisubtype = (u32)((ICE_DSCP_OUI << ICE_LLDP_TLV_OUI_S) | + ICE_DSCP_SUBTYPE_DSCP2UP); + tlv->ouisubtype = HTONL(ouisubtype); + + /* bytes 0 - 63 - IPv4 DSCP2UP LUT */ + for (i = 0; i < ICE_DSCP_NUM_VAL; i++) { + /* IPv4 mapping */ + buf[i] = dcbcfg->dscp_map[i]; + /* IPv6 mapping */ + buf[i + ICE_DSCP_IPV6_OFFSET] = dcbcfg->dscp_map[i]; + } + + /* byte 64 - IPv4 untagged traffic */ + buf[i] = 0; + + /* byte 144 - IPv6 untagged traffic */ + buf[i + ICE_DSCP_IPV6_OFFSET] = 0; +} + +#define ICE_BYTES_PER_TC 8 +/** + * ice_add_dscp_enf_tlv - Prepare DSCP Enforcement TLV + * @tlv: location to build the TLV data + */ +static void +ice_add_dscp_enf_tlv(struct ice_lldp_org_tlv *tlv) +{ + u8 *buf = tlv->tlvinfo; + u32 ouisubtype; + u16 typelen; + + typelen = ((ICE_TLV_TYPE_ORG << ICE_LLDP_TLV_TYPE_S) | + ICE_DSCP_ENF_TLV_LEN); + tlv->typelen = HTONS(typelen); + + ouisubtype = (u32)((ICE_DSCP_OUI << ICE_LLDP_TLV_OUI_S) | + ICE_DSCP_SUBTYPE_ENFORCE); + tlv->ouisubtype = HTONL(ouisubtype); + + /* Allow all DSCP values to be valid for all TC's (IPv4 and IPv6) */ + memset(buf, 0, 2 * (ICE_MAX_TRAFFIC_CLASS * ICE_BYTES_PER_TC)); +} + +/** + * ice_add_dscp_tc_bw_tlv - Prepare DSCP BW for TC TLV + * @tlv: location to build the TLV data + * @dcbcfg: location of the data to convert to TLV + */ +static void +ice_add_dscp_tc_bw_tlv(struct ice_lldp_org_tlv *tlv, + struct ice_dcbx_cfg *dcbcfg) +{ + struct ice_dcb_ets_cfg *etscfg; + u8 *buf = tlv->tlvinfo; + u32 ouisubtype; + u8 offset = 0; + u16 typelen; + int i; + + typelen = ((ICE_TLV_TYPE_ORG << ICE_LLDP_TLV_TYPE_S) | + ICE_DSCP_TC_BW_TLV_LEN); + tlv->typelen = HTONS(typelen); + + ouisubtype = (u32)((ICE_DSCP_OUI << ICE_LLDP_TLV_OUI_S) | + ICE_DSCP_SUBTYPE_TCBW); + tlv->ouisubtype = HTONL(ouisubtype); + + /* First Octet after subtype + * ---------------------------- + * | RSV | CBS | RSV | Max TCs | + * | 1b | 1b | 3b | 3b | + * ---------------------------- + */ + etscfg = &dcbcfg->etscfg; + buf[0] = etscfg->maxtcs & ICE_IEEE_ETS_MAXTC_M; + + /* bytes 1 - 4 reserved */ + offset = 5; + + /* TC BW table + * bytes 0 - 7 for TC 0 - 7 + * + * TSA Assignment table + * bytes 8 - 15 for TC 0 - 7 + */ + for (i = 0; i < ICE_MAX_TRAFFIC_CLASS; i++) { + buf[offset] = etscfg->tcbwtable[i]; + buf[offset + ICE_MAX_TRAFFIC_CLASS] = etscfg->tsatable[i]; + offset++; + } +} + +/** + * ice_add_dscp_pfc_tlv - Prepare DSCP PFC TLV + * @tlv: Fill PFC TLV in IEEE format + * @dcbcfg: Local store which holds the PFC CFG data + */ +static void +ice_add_dscp_pfc_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg) +{ + u8 *buf = tlv->tlvinfo; + u32 ouisubtype; + u16 typelen; + + typelen = ((ICE_TLV_TYPE_ORG << ICE_LLDP_TLV_TYPE_S) | + ICE_DSCP_PFC_TLV_LEN); + tlv->typelen = HTONS(typelen); + + ouisubtype = (u32)((ICE_DSCP_OUI << ICE_LLDP_TLV_OUI_S) | + ICE_DSCP_SUBTYPE_PFC); + tlv->ouisubtype = HTONL(ouisubtype); + + buf[0] = dcbcfg->pfc.pfccap & 0xF; + buf[1] = dcbcfg->pfc.pfcena & 0xF; +} + +/** + * ice_add_dcb_tlv - Add all IEEE or DSCP TLVs * @tlv: Fill TLV data in IEEE format * @dcbcfg: Local store which holds the DCB Config * @tlvid: Type of IEEE TLV @@ -1218,21 +1351,41 @@ static void ice_add_dcb_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg, u16 tlvid) { - switch (tlvid) { - case ICE_IEEE_TLV_ID_ETS_CFG: - ice_add_ieee_ets_tlv(tlv, dcbcfg); - break; - case ICE_IEEE_TLV_ID_ETS_REC: - ice_add_ieee_etsrec_tlv(tlv, dcbcfg); - break; - case ICE_IEEE_TLV_ID_PFC_CFG: - ice_add_ieee_pfc_tlv(tlv, dcbcfg); - break; - case ICE_IEEE_TLV_ID_APP_PRI: - ice_add_ieee_app_pri_tlv(tlv, dcbcfg); - break; - default: - break; + if (dcbcfg->pfc_mode == ICE_QOS_MODE_VLAN) { + switch (tlvid) { + case ICE_IEEE_TLV_ID_ETS_CFG: + ice_add_ieee_ets_tlv(tlv, dcbcfg); + break; + case ICE_IEEE_TLV_ID_ETS_REC: + ice_add_ieee_etsrec_tlv(tlv, dcbcfg); + break; + case ICE_IEEE_TLV_ID_PFC_CFG: + ice_add_ieee_pfc_tlv(tlv, dcbcfg); + break; + case ICE_IEEE_TLV_ID_APP_PRI: + ice_add_ieee_app_pri_tlv(tlv, dcbcfg); + break; + default: + break; + } + } else { + /* pfc_mode == ICE_QOS_MODE_DSCP */ + switch (tlvid) { + case ICE_TLV_ID_DSCP_UP: + ice_add_dscp_up_tlv(tlv, dcbcfg); + break; + case ICE_TLV_ID_DSCP_ENF: + ice_add_dscp_enf_tlv(tlv); + break; + case ICE_TLV_ID_DSCP_TC_BW: + ice_add_dscp_tc_bw_tlv(tlv, dcbcfg); + break; + case ICE_TLV_ID_DSCP_TO_PFC: + ice_add_dscp_pfc_tlv(tlv, dcbcfg); + break; + default: + break; + } } } diff --git a/drivers/net/ice/base/ice_dcb.h b/drivers/net/ice/base/ice_dcb.h index 658211966d..a053adbb30 100644 --- a/drivers/net/ice/base/ice_dcb.h +++ b/drivers/net/ice/base/ice_dcb.h @@ -29,6 +29,13 @@ #define ICE_CEE_DCBX_OUI 0x001B21 #define ICE_CEE_DCBX_TYPE 2 +#define ICE_DSCP_OUI 0xFFFFFF +#define ICE_DSCP_SUBTYPE_DSCP2UP 0x41 +#define ICE_DSCP_SUBTYPE_ENFORCE 0x42 +#define ICE_DSCP_SUBTYPE_TCBW 0x43 +#define ICE_DSCP_SUBTYPE_PFC 0x44 +#define ICE_DSCP_IPV6_OFFSET 80 + #define ICE_CEE_SUBTYPE_CTRL 1 #define ICE_CEE_SUBTYPE_PG_CFG 2 #define ICE_CEE_SUBTYPE_PFC_CFG 3 @@ -97,11 +104,20 @@ #define ICE_IEEE_TLV_ID_APP_PRI 6 #define ICE_TLV_ID_END_OF_LLDPPDU 7 #define ICE_TLV_ID_START ICE_IEEE_TLV_ID_ETS_CFG +#define ICE_TLV_ID_DSCP_UP 3 +#define ICE_TLV_ID_DSCP_ENF 4 +#define ICE_TLV_ID_DSCP_TC_BW 5 +#define ICE_TLV_ID_DSCP_TO_PFC 6 #define ICE_IEEE_ETS_TLV_LEN 25 #define ICE_IEEE_PFC_TLV_LEN 6 #define ICE_IEEE_APP_TLV_LEN 11 +#define ICE_DSCP_UP_TLV_LEN 148 +#define ICE_DSCP_ENF_TLV_LEN 132 +#define ICE_DSCP_TC_BW_TLV_LEN 25 +#define ICE_DSCP_PFC_TLV_LEN 6 + #pragma pack(1) /* IEEE 802.1AB LLDP Organization specific TLV */ struct ice_lldp_org_tlv { diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 3c534a7711..637dd306d4 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -797,7 +797,8 @@ struct ice_dcb_app_priority_table { }; #define ICE_MAX_USER_PRIORITY 8 -#define ICE_DCBX_MAX_APPS 32 +#define ICE_DCBX_MAX_APPS 64 +#define ICE_DSCP_NUM_VAL 64 #define ICE_LLDPDU_SIZE 1500 #define ICE_TLV_STATUS_OPER 0x1 #define ICE_TLV_STATUS_SYNC 0x2 @@ -817,7 +818,14 @@ struct ice_dcbx_cfg { struct ice_dcb_ets_cfg etscfg; struct ice_dcb_ets_cfg etsrec; struct ice_dcb_pfc_cfg pfc; +#define ICE_QOS_MODE_VLAN 0x0 +#define ICE_QOS_MODE_DSCP 0x1 + u8 pfc_mode; struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; + /* when DSCP mapping defined by user set its bit to 1 */ + ice_declare_bitmap(dscp_mapped, ICE_DSCP_NUM_VAL); + /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */ + u8 dscp_map[ICE_DSCP_NUM_VAL]; u8 dcbx_mode; #define ICE_DCBX_MODE_CEE 0x1 #define ICE_DCBX_MODE_IEEE 0x2 From patchwork Fri Apr 30 13:59:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 92551 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ECED9A0546; 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30 Apr 2021 06:55:46 -0700 From: Qi Zhang To: ferruh.yigit@intel.com Cc: qiming.yang@intel.com, dev@dpdk.org, Qi Zhang , Stefan Wegrzyn Date: Fri, 30 Apr 2021 21:59:21 +0800 Message-Id: <20210430135922.2990103-6-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210430135922.2990103-1-qi.z.zhang@intel.com> References: <20210429004143.2921260-1-qi.z.zhang@intel.com> <20210430135922.2990103-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 5/6] net/ice/base: sign external device package programming X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" External topology devices (e.g. PHYs) connected to 100G or to SoC that includes 100G IP might have a firmware engine within the device and the firmware is usually loaded from NVM connected to the topology device. The topology device NVM images can be updated using SW tools but such solution poses a security risk if there is no validation of the integrity of an image before programming it to the device NVM. In order to prevent security risk, the topology device NVM image might be included as part of 100G NVM image. When the topology device NVM image is present in the 100G NVM image, it is authenticated and might be loaded to the topology device at startup or on command of SW using dedicated AQ. This patch provides support for this functionality. Signed-off-by: Stefan Wegrzyn Signed-off-by: Qi Zhang Acked-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 39 +++++---- drivers/net/ice/base/ice_common.c | 119 +++++++++++++++++++++++++- drivers/net/ice/base/ice_common.h | 10 +++ drivers/net/ice/base/ice_type.h | 13 +++ 4 files changed, 162 insertions(+), 19 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 6b662b3889..3805fc9c5c 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -113,6 +113,10 @@ struct ice_aqc_list_caps_elem { #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 +#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0 0x0081 +#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1 0x0082 +#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2 0x0083 +#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3 0x0084 u8 major_ver; u8 minor_ver; @@ -1614,7 +1618,7 @@ struct ice_aqc_set_mac_lb { u8 reserved[15]; }; -struct ice_aqc_link_topo_addr { +struct ice_aqc_link_topo_params { u8 lport_num; u8 lport_num_valid; #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) @@ -1640,6 +1644,10 @@ struct ice_aqc_link_topo_addr { #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 u8 index; +}; + +struct ice_aqc_link_topo_addr { + struct ice_aqc_link_topo_params topo_params; __le16 handle; #define ICE_AQC_LINK_TOPO_HANDLE_S 0 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) @@ -1754,23 +1762,18 @@ struct ice_aqc_sw_gpio { u8 rsvd[12]; }; -/* Program topology device NVM (direct, 0x06F2) */ -struct ice_aqc_program_topology_device_nvm { - u8 lport_num; - u8 lport_num_valid; - u8 node_type_ctx; - u8 index; +/* Program Topology Device NVM (direct, 0x06F2) */ +struct ice_aqc_prog_topo_dev_nvm { + struct ice_aqc_link_topo_params topo_params; u8 rsvd[12]; }; -/* Read topology device NVM (indirect, 0x06F3) */ -struct ice_aqc_read_topology_device_nvm { - u8 lport_num; - u8 lport_num_valid; - u8 node_type_ctx; - u8 index; +/* Read Topology Device NVM (direct, 0x06F3) */ +struct ice_aqc_read_topo_dev_nvm { + struct ice_aqc_link_topo_params topo_params; __le32 start_address; - u8 data_read[8]; +#define ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE 8 + u8 data_read[ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE]; }; /* NVM Read command (indirect 0x0701) @@ -2744,6 +2747,8 @@ struct ice_aqc_set_health_status_config { #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117 +#define ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG 0x120 +#define ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD 0x121 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502 @@ -2946,6 +2951,8 @@ struct ice_aq_desc { get_supported_health_status_codes; struct ice_aqc_get_health_status get_health_status; struct ice_aqc_clear_health_status clear_health_status; + struct ice_aqc_prog_topo_dev_nvm prog_topo_dev_nvm; + struct ice_aqc_read_topo_dev_nvm read_topo_dev_nvm; } params; }; @@ -3122,8 +3129,8 @@ enum ice_adminq_opc { ice_aqc_opc_sff_eeprom = 0x06EE, ice_aqc_opc_sw_set_gpio = 0x06EF, ice_aqc_opc_sw_get_gpio = 0x06F0, - ice_aqc_opc_program_topology_device_nvm = 0x06F2, - ice_aqc_opc_read_topology_device_nvm = 0x06F3, + ice_aqc_opc_prog_topo_dev_nvm = 0x06F2, + ice_aqc_opc_read_topo_dev_nvm = 0x06F3, /* NVM commands */ ice_aqc_opc_nvm_read = 0x0701, diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 2424f3b4b3..ac412a1aa7 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -237,11 +237,13 @@ ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); - cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << - ICE_AQC_LINK_TOPO_NODE_CTX_S); + cmd->addr.topo_params.node_type_ctx = + (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << + ICE_AQC_LINK_TOPO_NODE_CTX_S); /* set node type */ - cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); + cmd->addr.topo_params.node_type_ctx |= + (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); } @@ -2000,6 +2002,47 @@ ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", prefix, caps->max_mtu); break; + case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0: + case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1: + case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2: + case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3: + { + u8 index = cap - ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0; + + if (index >= ICE_EXT_TOPO_DEV_IMG_COUNT) + break; + + caps->ext_topo_dev_img_ver_high[index] = number; + caps->ext_topo_dev_img_ver_low[index] = logical_id; + caps->ext_topo_dev_img_part_num[index] = + (phys_id & ICE_EXT_TOPO_DEV_IMG_PART_NUM_M) >> + ICE_EXT_TOPO_DEV_IMG_PART_NUM_S; + caps->ext_topo_dev_img_load_en[index] = + (phys_id & ICE_EXT_TOPO_DEV_IMG_LOAD_EN) != 0; + caps->ext_topo_dev_img_prog_en[index] = + (phys_id & ICE_EXT_TOPO_DEV_IMG_PROG_EN) != 0; + ice_debug(hw, ICE_DBG_INIT, + "%s: ext_topo_dev_img_ver_high[%d] = %d\n", + prefix, index, + caps->ext_topo_dev_img_ver_high[index]); + ice_debug(hw, ICE_DBG_INIT, + "%s: ext_topo_dev_img_ver_low[%d] = %d\n", + prefix, index, + caps->ext_topo_dev_img_ver_low[index]); + ice_debug(hw, ICE_DBG_INIT, + "%s: ext_topo_dev_img_part_num[%d] = %d\n", + prefix, index, + caps->ext_topo_dev_img_part_num[index]); + ice_debug(hw, ICE_DBG_INIT, + "%s: ext_topo_dev_img_load_en[%d] = %d\n", + prefix, index, + caps->ext_topo_dev_img_load_en[index]); + ice_debug(hw, ICE_DBG_INIT, + "%s: ext_topo_dev_img_prog_en[%d] = %d\n", + prefix, index, + caps->ext_topo_dev_img_prog_en[index]); + break; + } default: /* Not one of the recognized common capabilities */ found = false; @@ -3364,6 +3407,76 @@ ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, return status; } +/** + * ice_aq_prog_topo_dev_nvm + * @hw: pointer to the hardware structure + * @topo_params: pointer to structure storing topology parameters for a device + * @cd: pointer to command details structure or NULL + * + * Program Topology Device NVM (0x06F2) + * + */ +enum ice_status +ice_aq_prog_topo_dev_nvm(struct ice_hw *hw, + struct ice_aqc_link_topo_params *topo_params, + struct ice_sq_cd *cd) +{ + struct ice_aqc_prog_topo_dev_nvm *cmd; + struct ice_aq_desc desc; + + cmd = &desc.params.prog_topo_dev_nvm; + + ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_prog_topo_dev_nvm); + + ice_memcpy(&cmd->topo_params, topo_params, sizeof(*topo_params), + ICE_NONDMA_TO_NONDMA); + + return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); +} + +/** + * ice_aq_read_topo_dev_nvm + * @hw: pointer to the hardware structure + * @topo_params: pointer to structure storing topology parameters for a device + * @start_address: byte offset in the topology device NVM + * @data: pointer to data buffer + * @data_size: number of bytes to be read from the topology device NVM + * @cd: pointer to command details structure or NULL + * Read Topology Device NVM (0x06F3) + * + */ +enum ice_status +ice_aq_read_topo_dev_nvm(struct ice_hw *hw, + struct ice_aqc_link_topo_params *topo_params, + u32 start_address, u8 *data, u8 data_size, + struct ice_sq_cd *cd) +{ + struct ice_aqc_read_topo_dev_nvm *cmd; + struct ice_aq_desc desc; + enum ice_status status; + + if (!data || data_size == 0 || + data_size > ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE) + return ICE_ERR_PARAM; + + cmd = &desc.params.read_topo_dev_nvm; + + ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_topo_dev_nvm); + + desc.datalen = data_size; + ice_memcpy(&cmd->topo_params, topo_params, sizeof(*topo_params), + ICE_NONDMA_TO_NONDMA); + cmd->start_address = CPU_TO_LE32(start_address); + + status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); + if (status) + return status; + + ice_memcpy(data, cmd->data_read, data_size, ICE_NONDMA_TO_NONDMA); + + return ICE_SUCCESS; +} + /** * __ice_aq_get_set_rss_lut * @hw: pointer to the hardware structure diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index 62b5052797..22ea89cbbb 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -187,6 +187,16 @@ ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, bool write, struct ice_sq_cd *cd); +enum ice_status +ice_aq_prog_topo_dev_nvm(struct ice_hw *hw, + struct ice_aqc_link_topo_params *topo_params, + struct ice_sq_cd *cd); +enum ice_status +ice_aq_read_topo_dev_nvm(struct ice_hw *hw, + struct ice_aqc_link_topo_params *topo_params, + u32 start_address, u8 *buf, u8 buf_size, + struct ice_sq_cd *cd); + enum ice_status ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info); enum ice_status diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 637dd306d4..f64f215528 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -449,6 +449,19 @@ struct ice_hw_common_caps { #define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0) #define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1) #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) + + /* External topology device images within the NVM */ +#define ICE_EXT_TOPO_DEV_IMG_COUNT 4 + u32 ext_topo_dev_img_ver_high[ICE_EXT_TOPO_DEV_IMG_COUNT]; + u32 ext_topo_dev_img_ver_low[ICE_EXT_TOPO_DEV_IMG_COUNT]; + u8 ext_topo_dev_img_part_num[ICE_EXT_TOPO_DEV_IMG_COUNT]; +#define ICE_EXT_TOPO_DEV_IMG_PART_NUM_S 8 +#define ICE_EXT_TOPO_DEV_IMG_PART_NUM_M \ + MAKEMASK(0xFF, ICE_EXT_TOPO_DEV_IMG_PART_NUM_S) + bool ext_topo_dev_img_load_en[ICE_EXT_TOPO_DEV_IMG_COUNT]; +#define ICE_EXT_TOPO_DEV_IMG_LOAD_EN BIT(0) + bool ext_topo_dev_img_prog_en[ICE_EXT_TOPO_DEV_IMG_COUNT]; +#define ICE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1) }; /* Function specific capabilities */ From patchwork Fri Apr 30 13:59:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 92552 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B63D8A0546; Fri, 30 Apr 2021 15:58:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B6B904137F; Fri, 30 Apr 2021 15:55:53 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id C30A541376 for ; Fri, 30 Apr 2021 15:55:50 +0200 (CEST) IronPort-SDR: hVtn82jfMzW+qPNTwDNkn7ClW9ZFSi/UzQPqbTAR7narfExNrfy92C199+uUO/j3yYkb08y8x0 66JmZojZp1TQ== X-IronPort-AV: E=McAfee;i="6200,9189,9970"; a="218021274" X-IronPort-AV: E=Sophos;i="5.82,262,1613462400"; d="scan'208";a="218021274" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2021 06:55:50 -0700 IronPort-SDR: Ix3qh1g7Oc/HhTNP8so/iXqIB2i0kttvfJ3WJjb2MoAbx07xp8yv/Z1wGMB+vlLVvCVnoEq8ib vbf+zroEEZTg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,262,1613462400"; d="scan'208";a="459443810" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga002.fm.intel.com with ESMTP; 30 Apr 2021 06:55:48 -0700 From: Qi Zhang To: ferruh.yigit@intel.com Cc: qiming.yang@intel.com, dev@dpdk.org, Qi Zhang , Ting Xu , Jeff Guo Date: Fri, 30 Apr 2021 21:59:22 +0800 Message-Id: <20210430135922.2990103-7-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210430135922.2990103-1-qi.z.zhang@intel.com> References: <20210429004143.2921260-1-qi.z.zhang@intel.com> <20210430135922.2990103-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 6/6] net/ice/base: support IP fragment RSS and FDIR X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for IP fragment RSS hash and FDIR function. Separate IP fragment and IP other packet types. The patch also update the release date in README. Signed-off-by: Ting Xu Signed-off-by: Jeff Guo Signed-off-by: Qi Zhang Acked-by: Qi Zhang --- drivers/net/ice/base/README | 2 +- drivers/net/ice/base/ice_fdir.c | 49 ++++++++++++++++++++++++++++++- drivers/net/ice/base/ice_fdir.h | 4 +++ drivers/net/ice/base/ice_flow.c | 51 ++++++++++++++++++++++++++++++++- drivers/net/ice/base/ice_flow.h | 9 ++++-- drivers/net/ice/base/ice_type.h | 1 + 6 files changed, 110 insertions(+), 6 deletions(-) diff --git a/drivers/net/ice/base/README b/drivers/net/ice/base/README index 7d32e58a52..87a1cebfac 100644 --- a/drivers/net/ice/base/README +++ b/drivers/net/ice/base/README @@ -6,7 +6,7 @@ Intel® ICE driver ================== This directory contains source code of FreeBSD ice driver of version -2021.01.20 released by the team which develops +2021.04.29 released by the team which develops basic drivers for any ice NIC. The directory of base/ contains the original source package. This driver is valid for the product(s) listed below diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index f6a6ff3831..180508243d 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -518,6 +518,25 @@ static const u8 ice_fdir_ipv4_udp_ecpri_tp0_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; +static const u8 ice_fdir_ipv6_frag_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x2C, 0x40, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3B, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 ice_fdir_ipv4_frag_pkt[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x14, 0x00, 0x00, 0x20, 0x00, 0x40, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00 +}; + static const u8 ice_fdir_tcpv6_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00, @@ -716,6 +735,16 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = { sizeof(ice_fdir_ipv4_pkt), ice_fdir_ipv4_pkt, sizeof(ice_fdir_ip4_tun_pkt), ice_fdir_ip4_tun_pkt, }, + { + ICE_FLTR_PTYPE_FRAG_IPV4, + sizeof(ice_fdir_ipv4_frag_pkt), ice_fdir_ipv4_frag_pkt, + sizeof(ice_fdir_ipv4_frag_pkt), ice_fdir_ipv4_frag_pkt, + }, + { + ICE_FLTR_PTYPE_FRAG_IPV6, + sizeof(ice_fdir_ipv6_frag_pkt), ice_fdir_ipv6_frag_pkt, + sizeof(ice_fdir_ipv6_frag_pkt), ice_fdir_ipv6_frag_pkt, + }, { ICE_FLTR_PTYPE_NONF_IPV4_GTPU, sizeof(ice_fdir_ipv4_gtpu4_pkt), @@ -1808,6 +1837,23 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, input->ip.v6.proto); ice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac); break; + case ICE_FLTR_PTYPE_FRAG_IPV4: + ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET, + input->ip.v4.src_ip); + ice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET, + input->ip.v4.dst_ip); + ice_pkt_insert_u8(loc, ICE_IPV4_TOS_OFFSET, input->ip.v4.tos); + ice_pkt_insert_u16(loc, ICE_IPV4_ID_OFFSET, + input->ip.v4.packet_id); + ice_pkt_insert_u8(loc, ICE_IPV4_TTL_OFFSET, input->ip.v4.ttl); + ice_pkt_insert_u8(loc, ICE_IPV4_PROTO_OFFSET, + input->ip.v4.proto); + ice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac); + break; + case ICE_FLTR_PTYPE_FRAG_IPV6: + ice_pkt_insert_u32(loc, ICE_IPV6_ID_OFFSET, + input->ip.v6.packet_id); + break; default: return ICE_ERR_PARAM; } @@ -1838,7 +1884,8 @@ ice_fdir_get_prgm_pkt(struct ice_fdir_fltr *input, u8 *pkt, bool frag) */ bool ice_fdir_has_frag(enum ice_fltr_ptype flow) { - if (flow == ICE_FLTR_PTYPE_NONF_IPV4_OTHER) + if (flow == ICE_FLTR_PTYPE_FRAG_IPV4 || + flow == ICE_FLTR_PTYPE_FRAG_IPV6) return true; else return false; diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index b679a8a1bd..0ebf7f326c 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -42,10 +42,12 @@ #define ICE_MAC_ETHTYPE_OFFSET 12 #define ICE_IPV4_TOS_OFFSET 15 +#define ICE_IPV4_ID_OFFSET 18 #define ICE_IPV4_TTL_OFFSET 22 #define ICE_IPV6_TC_OFFSET 14 #define ICE_IPV6_HLIM_OFFSET 21 #define ICE_IPV6_PROTO_OFFSET 20 +#define ICE_IPV6_ID_OFFSET 58 /* For TUN inner (without inner MAC) */ #define ICE_IPV4_NO_MAC_TOS_OFFSET 1 #define ICE_IPV4_NO_MAC_TTL_OFFSET 8 @@ -158,6 +160,7 @@ struct ice_fdir_v4 { u8 ip_ver; u8 proto; u8 ttl; + __be16 packet_id; }; #define ICE_IPV6_ADDR_LEN_AS_U32 4 @@ -172,6 +175,7 @@ struct ice_fdir_v6 { u8 tc; u8 proto; u8 hlim; + __be32 packet_id; }; struct ice_fdir_udp_gtp { diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 6dba9e7b84..d6242744cd 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -13,6 +13,8 @@ #define ICE_FLOW_FLD_SZ_IPV6_PRE32_ADDR 4 #define ICE_FLOW_FLD_SZ_IPV6_PRE48_ADDR 6 #define ICE_FLOW_FLD_SZ_IPV6_PRE64_ADDR 8 +#define ICE_FLOW_FLD_SZ_IPV4_ID 2 +#define ICE_FLOW_FLD_SZ_IPV6_ID 4 #define ICE_FLOW_FLD_SZ_IP_DSCP 1 #define ICE_FLOW_FLD_SZ_IP_TTL 1 #define ICE_FLOW_FLD_SZ_IP_PROT 1 @@ -96,6 +98,12 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = { ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV6, 8, ICE_FLOW_FLD_SZ_IPV6_ADDR), /* ICE_FLOW_FIELD_IDX_IPV6_DA */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV6, 24, ICE_FLOW_FLD_SZ_IPV6_ADDR), + /* ICE_FLOW_FIELD_IDX_IPV4_FRAG */ + ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV_FRAG, 4, + ICE_FLOW_FLD_SZ_IPV4_ID), + /* ICE_FLOW_FIELD_IDX_IPV6_FRAG */ + ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV_FRAG, 4, + ICE_FLOW_FLD_SZ_IPV6_ID), /* ICE_FLOW_FIELD_IDX_IPV6_PRE32_SA */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV6, 8, ICE_FLOW_FLD_SZ_IPV6_PRE32_ADDR), @@ -747,6 +755,28 @@ static const u32 ice_ptypes_ppp[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; +static const u32 ice_ptypes_ipv4_frag[] = { + 0x00400000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static const u32 ice_ptypes_ipv6_frag[] = { + 0x00000000, 0x00000000, 0x01000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + /* Manage parameters and info. used during the creation of a flow profile */ struct ice_flow_prof_params { enum ice_block blk; @@ -922,6 +952,16 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params) (const ice_bitmap_t *)ice_ptypes_ipv6_ofos_all; ice_and_bitmap(params->ptypes, params->ptypes, src, ICE_FLOW_PTYPE_MAX); + } else if ((hdrs & ICE_FLOW_SEG_HDR_IPV4) && + (hdrs & ICE_FLOW_SEG_HDR_IPV_FRAG)) { + src = (const ice_bitmap_t *)ice_ptypes_ipv4_frag; + ice_and_bitmap(params->ptypes, params->ptypes, src, + ICE_FLOW_PTYPE_MAX); + } else if ((hdrs & ICE_FLOW_SEG_HDR_IPV6) && + (hdrs & ICE_FLOW_SEG_HDR_IPV_FRAG)) { + src = (const ice_bitmap_t *)ice_ptypes_ipv6_frag; + ice_and_bitmap(params->ptypes, params->ptypes, src, + ICE_FLOW_PTYPE_MAX); } else if ((hdrs & ICE_FLOW_SEG_HDR_IPV4) && !(hdrs & ICE_FLOW_SEG_HDRS_L4_MASK_NO_OTHER)) { src = !i ? (const ice_bitmap_t *)ice_ptypes_ipv4_ofos_no_l4 : @@ -1210,6 +1250,9 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, case ICE_FLOW_FIELD_IDX_IPV4_DA: prot_id = seg == 0 ? ICE_PROT_IPV4_OF_OR_S : ICE_PROT_IPV4_IL; break; + case ICE_FLOW_FIELD_IDX_IPV4_ID: + prot_id = ICE_PROT_IPV4_OF_OR_S; + break; case ICE_FLOW_FIELD_IDX_IPV6_SA: case ICE_FLOW_FIELD_IDX_IPV6_DA: case ICE_FLOW_FIELD_IDX_IPV6_PRE32_SA: @@ -1220,6 +1263,9 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, case ICE_FLOW_FIELD_IDX_IPV6_PRE64_DA: prot_id = seg == 0 ? ICE_PROT_IPV6_OF_OR_S : ICE_PROT_IPV6_IL; break; + case ICE_FLOW_FIELD_IDX_IPV6_ID: + prot_id = ICE_PROT_IPV6_FRAG; + break; case ICE_FLOW_FIELD_IDX_TCP_SRC_PORT: case ICE_FLOW_FIELD_IDX_TCP_DST_PORT: case ICE_FLOW_FIELD_IDX_TCP_FLAGS: @@ -3429,13 +3475,16 @@ ice_flow_set_rss_seg_info(struct ice_flow_seg_info *segs, u8 seg_cnt, /* set outer most header */ if (cfg->hdr_type == ICE_RSS_INNER_HEADERS_W_OUTER_IPV4) segs[ICE_RSS_OUTER_HEADERS].hdrs |= ICE_FLOW_SEG_HDR_IPV4 | + ICE_FLOW_SEG_HDR_IPV_FRAG | ICE_FLOW_SEG_HDR_IPV_OTHER; else if (cfg->hdr_type == ICE_RSS_INNER_HEADERS_W_OUTER_IPV6) segs[ICE_RSS_OUTER_HEADERS].hdrs |= ICE_FLOW_SEG_HDR_IPV6 | + ICE_FLOW_SEG_HDR_IPV_FRAG | ICE_FLOW_SEG_HDR_IPV_OTHER; if (seg->hdrs & ~ICE_FLOW_RSS_SEG_HDR_VAL_MASKS & - ~ICE_FLOW_RSS_HDRS_INNER_MASK & ~ICE_FLOW_SEG_HDR_IPV_OTHER) + ~ICE_FLOW_RSS_HDRS_INNER_MASK & ~ICE_FLOW_SEG_HDR_IPV_OTHER & + ~ICE_FLOW_SEG_HDR_IPV_FRAG) return ICE_ERR_PARAM; val = (u64)(seg->hdrs & ICE_FLOW_RSS_SEG_HDR_L3_MASKS); diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h index 448e06028a..878c79d19e 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -186,11 +186,12 @@ enum ice_flow_seg_hdr { ICE_FLOW_SEG_HDR_ECPRI_TP0 = 0x04000000, ICE_FLOW_SEG_HDR_UDP_ECPRI_TP0 = 0x08000000, ICE_FLOW_SEG_HDR_L2TPV2 = 0x10000000, - ICE_FLOW_SEG_HDR_PPP = 0x40000000, + ICE_FLOW_SEG_HDR_PPP = 0x20000000, /* The following is an additive bit for ICE_FLOW_SEG_HDR_IPV4 and - * ICE_FLOW_SEG_HDR_IPV6 which include the IPV4 other PTYPEs + * ICE_FLOW_SEG_HDR_IPV6. */ - ICE_FLOW_SEG_HDR_IPV_OTHER = 0x20000000, + ICE_FLOW_SEG_HDR_IPV_FRAG = 0x40000000, + ICE_FLOW_SEG_HDR_IPV_OTHER = 0x80000000, }; /* These segements all have the same PTYPES, but are otherwise distinguished by @@ -227,6 +228,8 @@ enum ice_flow_field { ICE_FLOW_FIELD_IDX_IPV4_DA, ICE_FLOW_FIELD_IDX_IPV6_SA, ICE_FLOW_FIELD_IDX_IPV6_DA, + ICE_FLOW_FIELD_IDX_IPV4_ID, + ICE_FLOW_FIELD_IDX_IPV6_ID, ICE_FLOW_FIELD_IDX_IPV6_PRE32_SA, ICE_FLOW_FIELD_IDX_IPV6_PRE32_DA, ICE_FLOW_FIELD_IDX_IPV6_PRE48_SA, diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index f64f215528..ce508a02e5 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -347,6 +347,7 @@ enum ice_fltr_ptype { ICE_FLTR_PTYPE_NONF_ECPRI_TP0, ICE_FLTR_PTYPE_NONF_IPV4_UDP_ECPRI_TP0, ICE_FLTR_PTYPE_FRAG_IPV4, + ICE_FLTR_PTYPE_FRAG_IPV6, ICE_FLTR_PTYPE_NONF_IPV6_UDP, ICE_FLTR_PTYPE_NONF_IPV6_TCP, ICE_FLTR_PTYPE_NONF_IPV6_SCTP,