From patchwork Wed May 12 08:28:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: fengchengwen X-Patchwork-Id: 93194 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7D229A0A0E; Wed, 12 May 2021 10:31:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 16F9D4003F; Wed, 12 May 2021 10:31:53 +0200 (CEST) Received: from szxga06-in.huawei.com (szxga06-in.huawei.com [45.249.212.32]) by mails.dpdk.org (Postfix) with ESMTP id 3704A4003E for ; Wed, 12 May 2021 10:31:51 +0200 (CEST) Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4Fg7J23RlHzldZK; Wed, 12 May 2021 16:29:38 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.498.0; Wed, 12 May 2021 16:31:46 +0800 From: Chengwen Feng To: , CC: , , , , , Date: Wed, 12 May 2021 16:28:45 +0800 Message-ID: <1620808126-18876-2-git-send-email-fengchengwen@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1620808126-18876-1-git-send-email-fengchengwen@huawei.com> References: <1620808126-18876-1-git-send-email-fengchengwen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 1/2] config/arm: add non-SVE march for soc kunpeng930 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently, the soc_kunpeng930 declares '-march=armv8.2-a+crypto+sve', but some compiler doesn't recognize the march because it doesn't support sve. This patch adds '-march=armv8.2-a+crypto' before '-march=armv8.2-a+crypto+sve' so that: 1. If compiler doesn't support '-march=armv8.2-a+crypto+sve', then it will fallback supports 'armv8.2-a+crypto'. 2. If compiler supports '-march=armv8.2-a+crypto+sve', then it will compile SVE-related code. Fixes: 7cf32a22b240 ("config/arm: add Hisilicon kunpeng") Signed-off-by: Chengwen Feng --- config/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 3f34ec9..fe6c29b 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -158,7 +158,7 @@ implementer_hisilicon = { ] }, '0xd02': { - 'machine_args': ['-march=armv8.2-a+crypto+sve'], + 'machine_args': ['-march=armv8.2-a+crypto', '-march=armv8.2-a+crypto+sve'], 'flags': [ ['RTE_MACHINE', '"Kunpeng 930"'], ['RTE_ARM_FEATURE_ATOMICS', true], From patchwork Wed May 12 08:28:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: fengchengwen X-Patchwork-Id: 93196 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 27E27A0A0E; Wed, 12 May 2021 10:32:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 60B3741104; Wed, 12 May 2021 10:31:55 +0200 (CEST) Received: from szxga06-in.huawei.com (szxga06-in.huawei.com [45.249.212.32]) by mails.dpdk.org (Postfix) with ESMTP id A36634003E for ; Wed, 12 May 2021 10:31:52 +0200 (CEST) Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4Fg7J22xTnzldYl; Wed, 12 May 2021 16:29:38 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.498.0; Wed, 12 May 2021 16:31:47 +0800 From: Chengwen Feng To: , CC: , , , , , Date: Wed, 12 May 2021 16:28:46 +0800 Message-ID: <1620808126-18876-3-git-send-email-fengchengwen@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1620808126-18876-1-git-send-email-fengchengwen@huawei.com> References: <1620808126-18876-1-git-send-email-fengchengwen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 2/2] net/hns3: refactor SVE code compile method X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently, the SVE code is compiled only when -march supports SVE (e.g. '-march=armv8.2a+sve'), there maybe some problem[1] with this approach. The solution: a. If the minimum instruction set support SVE then compiles it. b. Else if the compiler support SVE then compiles it. c. Otherwise don't compile it. [1] https://mails.dpdk.org/archives/dev/2021-April/208189.html Fixes: 8c25b02b082a ("net/hns3: fix enabling SVE Rx/Tx") Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") Cc: stable@dpdk.org Signed-off-by: Chengwen Feng --- drivers/net/hns3/hns3_rxtx.c | 2 +- drivers/net/hns3/meson.build | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 1d7a769..4ef20c6 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2808,7 +2808,7 @@ hns3_get_default_vec_support(void) static bool hns3_get_sve_support(void) { -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) +#if defined(CC_SVE_SUPPORT) if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) return false; if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build index 53c7df7..8563d70 100644 --- a/drivers/net/hns3/meson.build +++ b/drivers/net/hns3/meson.build @@ -35,7 +35,20 @@ deps += ['hash'] if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64') sources += files('hns3_rxtx_vec.c') + + # compile SVE when: + # a. support SVE in minimum instruction set baseline + # b. it's not minimum instruction set, but compiler support if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' + cflags += ['-DCC_SVE_SUPPORT'] sources += files('hns3_rxtx_vec_sve.c') + elif cc.has_argument('-march=armv8.2-a+sve') + cflags += ['-DCC_SVE_SUPPORT'] + hns3_sve_lib = static_library('hns3_sve_lib', + 'hns3_rxtx_vec_sve.c', + dependencies: [static_rte_ethdev], + include_directories: includes, + c_args: [cflags, '-march=armv8.2-a+sve']) + objs += hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c') endif endif