From patchwork Mon May 24 13:23:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: fengchengwen X-Patchwork-Id: 93423 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 07FC1A0547; Mon, 24 May 2021 15:26:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8EF0C4110A; Mon, 24 May 2021 15:26:34 +0200 (CEST) Received: from szxga06-in.huawei.com (szxga06-in.huawei.com [45.249.212.32]) by mails.dpdk.org (Postfix) with ESMTP id 5F48A4003C for ; Mon, 24 May 2021 15:26:31 +0200 (CEST) Received: from dggems701-chm.china.huawei.com (unknown [172.30.72.59]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4FpdGJ3VYxzmZ7Q; Mon, 24 May 2021 21:24:08 +0800 (CST) Received: from dggpeml500024.china.huawei.com (7.185.36.10) by dggems701-chm.china.huawei.com (10.3.19.178) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 24 May 2021 21:26:28 +0800 Received: from localhost.localdomain (10.67.165.24) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 24 May 2021 21:26:27 +0800 From: Chengwen Feng To: , CC: , , , , , , , , Date: Mon, 24 May 2021 21:23:21 +0800 Message-ID: <1621862602-51782-2-git-send-email-fengchengwen@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1621862602-51782-1-git-send-email-fengchengwen@huawei.com> References: <1620808126-18876-1-git-send-email-fengchengwen@huawei.com> <1621862602-51782-1-git-send-email-fengchengwen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v8 1/2] config/arm: select most suitable -march for kunpeng soc X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently, the soc_kunpeng930 declares '-march=armv8.2-a+crypto+sve', but some compiler doesn't recognize the march because it doesn't support sve. To solve this bug we use the following scheme: 1. Define 'march_base' tuple which defines support march, it should arrange from lower to higher. e.g. 'march_base': ['-march=armv8.1-a', '-march=armv8.2-a'] 2. Define 'march_feature' tuple which defines support feature. e.g. 'march_feature': ['crypto', 'sve'] Note: If user defined 'march_feature', it also needs to define a valid 'march_base' because 'march_feature' depends on 'march_base' when checking validity. 3. Select the most suitable march+feature combination based on 'march_base' and 'march_feature' tuples. 4. Use the selected march+feature combination as the default machine_args. Fixes: 7cf32a22b240 ("config/arm: add Hisilicon kunpeng") Signed-off-by: Chengwen Feng --- config/arm/meson.build | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 3f34ec9..044812f 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -158,7 +158,9 @@ implementer_hisilicon = { ] }, '0xd02': { - 'machine_args': ['-march=armv8.2-a+crypto+sve'], + 'march_base': ['-march=armv8.2-a'], + 'march_feature': ['crypto', 'sve'], + 'machine_args': [], 'flags': [ ['RTE_MACHINE', '"Kunpeng 930"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -449,8 +451,33 @@ else # add/overwrite flags in the proper order dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', []) + soc_flags + # select the most suitable march+feature combination + machine_march = [] + if part_number_config.has_key('march_base') + tmp_machine_march = '' + march_valid = false + foreach march: part_number_config['march_base'] + if cc.has_argument(march) + tmp_machine_march = march # Set the higher supported march as possible + march_valid = true + endif + endforeach + # select feature only when march valid + if march_valid and part_number_config.has_key('march_feature') + foreach feature: part_number_config['march_feature'] + tmp_feature = tmp_machine_march + '+' + feature + if cc.has_argument(tmp_feature) + tmp_machine_march = tmp_feature # Set the more supported feature as possible + endif + endforeach + endif + if march_valid + machine_march = [tmp_machine_march] + endif + endif + # apply supported machine args - machine_args = [] # Clear previous machine args + machine_args = machine_march # Init with machine march which set above foreach flag: part_number_config['machine_args'] if cc.has_argument(flag) machine_args += flag From patchwork Mon May 24 13:23:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: fengchengwen X-Patchwork-Id: 93422 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0241CA0547; Mon, 24 May 2021 15:26:38 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 767C3410FF; Mon, 24 May 2021 15:26:33 +0200 (CEST) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id ED17B4003E for ; Mon, 24 May 2021 15:26:30 +0200 (CEST) Received: from dggems702-chm.china.huawei.com (unknown [172.30.72.60]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4FpdFj4NhVzBvb0; Mon, 24 May 2021 21:23:37 +0800 (CST) Received: from dggpeml500024.china.huawei.com (7.185.36.10) by dggems702-chm.china.huawei.com (10.3.19.179) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 24 May 2021 21:26:28 +0800 Received: from localhost.localdomain (10.67.165.24) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 24 May 2021 21:26:27 +0800 From: Chengwen Feng To: , CC: , , , , , , , , Date: Mon, 24 May 2021 21:23:22 +0800 Message-ID: <1621862602-51782-3-git-send-email-fengchengwen@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1621862602-51782-1-git-send-email-fengchengwen@huawei.com> References: <1620808126-18876-1-git-send-email-fengchengwen@huawei.com> <1621862602-51782-1-git-send-email-fengchengwen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v8 2/2] net/hns3: refactor SVE code compile method X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently, the SVE code is compiled only when -march supports SVE (e.g. '-march=armv8.2a+sve'), there maybe some problem[1] with this approach. The solution: a. If the minimum instruction set support SVE then compiles it. b. Else if the compiler support SVE then compiles it. c. Otherwise don't compile it. Note: this patch also fixes compile error with gcc8.3 + '-march=armv8.a+sve', the error is arm_sve.h no such file or directory. [1] https://mails.dpdk.org/archives/dev/2021-April/208189.html Fixes: 8c25b02b082a ("net/hns3: fix enabling SVE Rx/Tx") Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") Cc: stable@dpdk.org Signed-off-by: Chengwen Feng Reviewed-by: Ruifeng Wang Reviewed-by: Ruifeng Wang < ruifeng.wang@arm.com> --- drivers/net/hns3/hns3_rxtx.c | 2 +- drivers/net/hns3/meson.build | 20 +++++++++++++++++++- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 1d7a769..9b2f082 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2808,7 +2808,7 @@ hns3_get_default_vec_support(void) static bool hns3_get_sve_support(void) { -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) +#if defined(CC_SVE_ACLE_SUPPORT) if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) return false; if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build index 53c7df7..aabcf23 100644 --- a/drivers/net/hns3/meson.build +++ b/drivers/net/hns3/meson.build @@ -35,7 +35,25 @@ deps += ['hash'] if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64') sources += files('hns3_rxtx_vec.c') - if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' + + # compile SVE when: + # a. support SVE in minimum instruction set baseline + # b. it's not minimum instruction set, but compiler support + if dpdk_conf.has('CC_SVE_ACLE_SUPPORT') sources += files('hns3_rxtx_vec_sve.c') + elif cc.has_argument('-march=armv8.2-a+sve') and cc.check_header('arm_sve.h') + cflags += ['-DCC_SVE_ACLE_SUPPORT=1'] + sve_cflags = [] + foreach flag: cflags + if not (flag.startswith('-march=') or flag.startswith('-mcpu=') or flag.startswith('-mtune=')) + sve_cflags += flag + endif + endforeach + hns3_sve_lib = static_library('hns3_sve_lib', + 'hns3_rxtx_vec_sve.c', + dependencies: [static_rte_ethdev], + include_directories: includes, + c_args: [sve_cflags, '-march=armv8.2-a+sve']) + objs += hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c') endif endif