From patchwork Tue Jul 6 06:54:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 95333 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0E9A0A0C47; Tue, 6 Jul 2021 08:55:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B6E324121D; Tue, 6 Jul 2021 08:55:09 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 601724067E; Tue, 6 Jul 2021 08:55:08 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CB95C31B; Mon, 5 Jul 2021 23:55:07 -0700 (PDT) Received: from net-arm-n1sdp.shanghai.arm.com (net-arm-n1sdp.shanghai.arm.com [10.169.208.222]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F20603F5A1; Mon, 5 Jul 2021 23:55:04 -0700 (PDT) From: Joyce Kong To: beilei.xing@intel.com, qi.z.zhang@intel.com, ruifeng.wang@arm.com, honnappa.nagarahalli@arm.com, bruce.richardson@intel.com, helin.zhang@intel.com Cc: dev@dpdk.org, stable@dpdk.org, nd@arm.com Date: Tue, 6 Jul 2021 01:54:03 -0500 Message-Id: <20210706065404.25137-2-joyce.kong@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210706065404.25137-1-joyce.kong@arm.com> References: <20210604073405.14880-1-joyce.kong@arm.com> <20210706065404.25137-1-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v3 1/2] net/i40e: add logic of processing continuous DD bits for Arm X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" For Arm platforms, reading descs can get re-ordered, then the status of DD bits will be discontinuous, so add the logic to only process continuous descs by checking DD bits. Fixes: 4861cde46116 ("i40e: new poll mode driver") Cc: stable@dpdk.org Signed-off-by: Joyce Kong Reviewed-by: Ruifeng Wang --- drivers/net/i40e/i40e_rxtx.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index 6c58decec..9aaabfd92 100644 --- a/drivers/net/i40e/i40e_rxtx.c +++ b/drivers/net/i40e/i40e_rxtx.c @@ -452,7 +452,7 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq) uint16_t pkt_len; uint64_t qword1; uint32_t rx_status; - int32_t s[I40E_LOOK_AHEAD], nb_dd; + int32_t s[I40E_LOOK_AHEAD], var, nb_dd; int32_t i, j, nb_rx = 0; uint64_t pkt_flags; uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl; @@ -485,8 +485,18 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq) rte_smp_rmb(); /* Compute how many status bits were set */ - for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) - nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT); + for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) { + var = s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT); +#ifdef RTE_ARCH_ARM + /* For Arm platforms, only compute continuous status bits */ + if (var) + nb_dd += 1; + else + break; +#else + nb_dd += var; +#endif + } nb_rx += nb_dd; From patchwork Tue Jul 6 06:54:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 95334 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 79D10A0C47; Tue, 6 Jul 2021 08:55:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3646A41228; Tue, 6 Jul 2021 08:55:13 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id B1A7E41226; Tue, 6 Jul 2021 08:55:11 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3724E31B; Mon, 5 Jul 2021 23:55:11 -0700 (PDT) Received: from net-arm-n1sdp.shanghai.arm.com (net-arm-n1sdp.shanghai.arm.com [10.169.208.222]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 50CC93F5A1; Mon, 5 Jul 2021 23:55:08 -0700 (PDT) From: Joyce Kong To: beilei.xing@intel.com, qi.z.zhang@intel.com, ruifeng.wang@arm.com, honnappa.nagarahalli@arm.com, bruce.richardson@intel.com, helin.zhang@intel.com Cc: dev@dpdk.org, stable@dpdk.org, nd@arm.com Date: Tue, 6 Jul 2021 01:54:04 -0500 Message-Id: <20210706065404.25137-3-joyce.kong@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210706065404.25137-1-joyce.kong@arm.com> References: <20210604073405.14880-1-joyce.kong@arm.com> <20210706065404.25137-1-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v3 2/2] net/i40e: replace SMP barrier with thread fence X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Simply replace the SMP barrier with atomic thread fence for i40e hw ring sacn, if there is no synchronization point. Signed-off-by: Joyce Kong Reviewed-by: Ruifeng Wang Acked-by: Qi Zhang --- drivers/net/i40e/i40e_rxtx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index 9aaabfd92..86e2f083e 100644 --- a/drivers/net/i40e/i40e_rxtx.c +++ b/drivers/net/i40e/i40e_rxtx.c @@ -482,7 +482,8 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq) I40E_RXD_QW1_STATUS_SHIFT; } - rte_smp_rmb(); + /* This barrier is to order loads of different words in the descriptor */ + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); /* Compute how many status bits were set */ for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) {