From patchwork Fri Sep 17 13:54:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 99159 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6D931A0C46; Fri, 17 Sep 2021 15:54:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 02786410F1; Fri, 17 Sep 2021 15:54:40 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id EA3EA40689 for ; Fri, 17 Sep 2021 15:54:37 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10109"; a="286485137" X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="286485137" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2021 06:54:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="530730333" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by fmsmga004.fm.intel.com with ESMTP; 17 Sep 2021 06:54:35 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Fri, 17 Sep 2021 14:54:21 +0100 Message-Id: <20210917135429.90562-2-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210917135429.90562-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210917135429.90562-1-bruce.richardson@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v5 1/9] dmadev: add channel status check for testing use X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add in a function to check if a device or vchan has completed all jobs assigned to it, without gathering in the results. This is primarily for use in testing, to allow the hardware to be in a known-state prior to gathering completions. Signed-off-by: Bruce Richardson Reviewed-by: Conor Walsh Reviewed-by: Kevin Laatz --- lib/dmadev/rte_dmadev.c | 15 +++++++++++++++ lib/dmadev/rte_dmadev.h | 33 +++++++++++++++++++++++++++++++++ lib/dmadev/rte_dmadev_core.h | 6 ++++++ lib/dmadev/version.map | 1 + 4 files changed, 55 insertions(+) -- 2.30.2 diff --git a/lib/dmadev/rte_dmadev.c b/lib/dmadev/rte_dmadev.c index 544937acf8..859958fff8 100644 --- a/lib/dmadev/rte_dmadev.c +++ b/lib/dmadev/rte_dmadev.c @@ -716,3 +716,18 @@ rte_dma_dump(int16_t dev_id, FILE *f) return 0; } + +int +rte_dma_vchan_status(uint16_t dev_id, uint16_t vchan, enum rte_dma_vchan_status *status) +{ + struct rte_dma_dev *dev = &rte_dma_devices[dev_id]; + + RTE_DMA_VALID_DEV_ID_OR_ERR_RET(dev_id, -EINVAL); + if (vchan >= dev->data->dev_conf.nb_vchans) { + RTE_DMA_LOG(ERR, "Device %u vchan %u out of range\n", dev_id, vchan); + return -EINVAL; + } + + RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vchan_status, -ENOTSUP); + return (*dev->dev_ops->vchan_status)(dev, vchan, status); +} diff --git a/lib/dmadev/rte_dmadev.h b/lib/dmadev/rte_dmadev.h index be54f2cb9d..86c4a38f83 100644 --- a/lib/dmadev/rte_dmadev.h +++ b/lib/dmadev/rte_dmadev.h @@ -660,6 +660,39 @@ int rte_dma_stats_get(int16_t dev_id, uint16_t vchan, __rte_experimental int rte_dma_stats_reset(int16_t dev_id, uint16_t vchan); +/** + * device vchannel status + * + * Enum with the options for the channel status, either idle, active or halted due to error + */ +enum rte_dma_vchan_status { + RTE_DMA_VCHAN_IDLE, /**< not processing, awaiting ops */ + RTE_DMA_VCHAN_ACTIVE, /**< currently processing jobs */ + RTE_DMA_VCHAN_HALTED_ERROR, /**< not processing due to error, cannot accept new ops */ +}; + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Determine if all jobs have completed on a device channel. + * This function is primarily designed for testing use, as it allows a process to check if + * all jobs are completed, without actually gathering completions from those jobs. + * + * @param dev_id + * The identifier of the device. + * @param vchan + * The identifier of virtual DMA channel. + * @param[out] status + * The vchan status + * @return + * 0 - call completed successfully + * < 0 - error code indicating there was a problem calling the API + */ +__rte_experimental +int +rte_dma_vchan_status(uint16_t dev_id, uint16_t vchan, enum rte_dma_vchan_status *status); + /** * @warning * @b EXPERIMENTAL: this API may change without prior notice. diff --git a/lib/dmadev/rte_dmadev_core.h b/lib/dmadev/rte_dmadev_core.h index edb3286cbb..0eec1aa43b 100644 --- a/lib/dmadev/rte_dmadev_core.h +++ b/lib/dmadev/rte_dmadev_core.h @@ -46,6 +46,10 @@ typedef int (*rte_dma_vchan_setup_t)(struct rte_dma_dev *dev, uint16_t vchan, const struct rte_dma_vchan_conf *conf, uint32_t conf_sz); +/** @internal Used to check if a virtual channel has finished all jobs. */ +typedef int (*rte_dma_vchan_status_t)(const struct rte_dma_dev *dev, uint16_t vchan, + enum rte_dma_vchan_status *status); + /** @internal Used to retrieve basic statistics. */ typedef int (*rte_dma_stats_get_t)(const struct rte_dma_dev *dev, uint16_t vchan, struct rte_dma_stats *stats, @@ -119,6 +123,8 @@ struct rte_dma_dev_ops { rte_dma_stats_reset_t stats_reset; rte_dma_dump_t dev_dump; + rte_dma_vchan_status_t vchan_status; + }; /** diff --git a/lib/dmadev/version.map b/lib/dmadev/version.map index c780463bb2..40ea517016 100644 --- a/lib/dmadev/version.map +++ b/lib/dmadev/version.map @@ -20,6 +20,7 @@ EXPERIMENTAL { rte_dma_stop; rte_dma_submit; rte_dma_vchan_setup; + rte_dma_vchan_status; local: *; }; From patchwork Fri Sep 17 13:54:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 99160 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6BEE3A0C46; Fri, 17 Sep 2021 15:54:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 173BF410FF; Fri, 17 Sep 2021 15:54:42 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 59D61410F8 for ; Fri, 17 Sep 2021 15:54:40 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10109"; a="286485152" X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="286485152" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2021 06:54:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="530730342" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by fmsmga004.fm.intel.com with ESMTP; 17 Sep 2021 06:54:38 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com Date: Fri, 17 Sep 2021 14:54:22 +0100 Message-Id: <20210917135429.90562-3-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210917135429.90562-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210917135429.90562-1-bruce.richardson@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v5 2/9] dmadev: add burst capacity API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kevin Laatz Add a burst capacity check API to the dmadev library. This API is useful to applications which need to how many descriptors can be enqueued in the current batch. For example, it could be used to determine whether all segments of a multi-segment packet can be enqueued in the same batch or not (to avoid half-offload of the packet). Signed-off-by: Kevin Laatz Reviewed-by: Conor Walsh --- lib/dmadev/rte_dmadev.c | 11 +++++++++++ lib/dmadev/rte_dmadev.h | 19 +++++++++++++++++++ lib/dmadev/rte_dmadev_core.h | 5 ++++- lib/dmadev/version.map | 1 + 4 files changed, 35 insertions(+), 1 deletion(-) -- 2.30.2 diff --git a/lib/dmadev/rte_dmadev.c b/lib/dmadev/rte_dmadev.c index 859958fff8..ed342e0d32 100644 --- a/lib/dmadev/rte_dmadev.c +++ b/lib/dmadev/rte_dmadev.c @@ -684,6 +684,17 @@ dma_dump_capability(FILE *f, uint64_t dev_capa) fprintf(f, "\n"); } +int +rte_dma_burst_capacity(uint16_t dev_id, uint16_t vchan) +{ + const struct rte_dma_dev *dev = &rte_dma_devices[dev_id]; + + RTE_DMA_VALID_DEV_ID_OR_ERR_RET(dev_id, -EINVAL); + + RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->burst_capacity, -ENOTSUP); + return (*dev->dev_ops->burst_capacity)(dev, vchan); +} + int rte_dma_dump(int16_t dev_id, FILE *f) { diff --git a/lib/dmadev/rte_dmadev.h b/lib/dmadev/rte_dmadev.h index 86c4a38f83..be4bb18ee6 100644 --- a/lib/dmadev/rte_dmadev.h +++ b/lib/dmadev/rte_dmadev.h @@ -693,6 +693,25 @@ __rte_experimental int rte_dma_vchan_status(uint16_t dev_id, uint16_t vchan, enum rte_dma_vchan_status *status); +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Check remaining capacity in descriptor ring for the current burst. + * + * @param dev_id + * The identifier of the device. + * @param vchan + * The identifier of virtual DMA channel. + * + * @return + * - Remaining space in the descriptor ring for the current burst on success. + * - -ENOTSUP: if not supported by the device. + */ +__rte_experimental +int +rte_dma_burst_capacity(uint16_t dev_id, uint16_t vchan); + /** * @warning * @b EXPERIMENTAL: this API may change without prior notice. diff --git a/lib/dmadev/rte_dmadev_core.h b/lib/dmadev/rte_dmadev_core.h index 0eec1aa43b..21290ef471 100644 --- a/lib/dmadev/rte_dmadev_core.h +++ b/lib/dmadev/rte_dmadev_core.h @@ -58,6 +58,9 @@ typedef int (*rte_dma_stats_get_t)(const struct rte_dma_dev *dev, /** @internal Used to reset basic statistics. */ typedef int (*rte_dma_stats_reset_t)(struct rte_dma_dev *dev, uint16_t vchan); +/** @internal Used to check the remaining space in descriptor ring. */ +typedef uint16_t (*rte_dma_burst_capacity_t)(const struct rte_dma_dev *dev, uint16_t vchan); + /** @internal Used to dump internal information. */ typedef int (*rte_dma_dump_t)(const struct rte_dma_dev *dev, FILE *f); @@ -124,7 +127,7 @@ struct rte_dma_dev_ops { rte_dma_dump_t dev_dump; rte_dma_vchan_status_t vchan_status; - + rte_dma_burst_capacity_t burst_capacity; }; /** diff --git a/lib/dmadev/version.map b/lib/dmadev/version.map index 40ea517016..66420c4ede 100644 --- a/lib/dmadev/version.map +++ b/lib/dmadev/version.map @@ -1,6 +1,7 @@ EXPERIMENTAL { global: + rte_dma_burst_capacity; rte_dma_close; rte_dma_completed; rte_dma_completed_status; From patchwork Fri Sep 17 13:54:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 99161 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 96528A0C46; Fri, 17 Sep 2021 15:54:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3C2614111C; Fri, 17 Sep 2021 15:54:44 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 869F141104 for ; Fri, 17 Sep 2021 15:54:42 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10109"; a="286485161" X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="286485161" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2021 06:54:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="530730356" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by fmsmga004.fm.intel.com with ESMTP; 17 Sep 2021 06:54:40 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Fri, 17 Sep 2021 14:54:23 +0100 Message-Id: <20210917135429.90562-4-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210917135429.90562-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210917135429.90562-1-bruce.richardson@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v5 3/9] dmadev: add device iterator X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add a function and wrapper macro to iterate over all dma devices. Signed-off-by: Bruce Richardson --- lib/dmadev/rte_dmadev.c | 13 +++++++++++++ lib/dmadev/rte_dmadev.h | 18 ++++++++++++++++++ lib/dmadev/version.map | 1 + 3 files changed, 32 insertions(+) -- 2.30.2 diff --git a/lib/dmadev/rte_dmadev.c b/lib/dmadev/rte_dmadev.c index ed342e0d32..ba189f3539 100644 --- a/lib/dmadev/rte_dmadev.c +++ b/lib/dmadev/rte_dmadev.c @@ -55,6 +55,19 @@ rte_dma_dev_max(size_t dev_max) return 0; } +uint16_t +rte_dma_next_dev(uint16_t start_dev_id) +{ + uint16_t dev_id = start_dev_id; + while (dev_id < dma_devices_max && rte_dma_devices[dev_id].state == RTE_DMA_DEV_UNUSED) + dev_id++; + + if (dev_id < dma_devices_max) + return dev_id; + + return UINT16_MAX; +} + static int dma_check_name(const char *name) { diff --git a/lib/dmadev/rte_dmadev.h b/lib/dmadev/rte_dmadev.h index be4bb18ee6..d262b8ed8d 100644 --- a/lib/dmadev/rte_dmadev.h +++ b/lib/dmadev/rte_dmadev.h @@ -219,6 +219,24 @@ bool rte_dma_is_valid(int16_t dev_id); __rte_experimental uint16_t rte_dma_count_avail(void); +/** + * Iterates over valid dmadev instances. + * + * @param start_dev_id + * The id of the next possible dmadev. + * @return + * Next valid dmadev, UINT16_MAX if there is none. + */ +__rte_experimental +uint16_t rte_dma_next_dev(uint16_t start_dev_id); + +/** Utility macro to iterate over all available dmadevs */ +#define RTE_DMA_FOREACH_DEV(p) \ + for (p = rte_dma_next_dev(0); \ + (uint16_t)p < UINT16_MAX; \ + p = rte_dma_next_dev(p + 1)) + + /** DMA device support memory-to-memory transfer. * * @see struct rte_dma_info::dev_capa diff --git a/lib/dmadev/version.map b/lib/dmadev/version.map index 66420c4ede..0ab570a1be 100644 --- a/lib/dmadev/version.map +++ b/lib/dmadev/version.map @@ -15,6 +15,7 @@ EXPERIMENTAL { rte_dma_get_dev_id; rte_dma_info_get; rte_dma_is_valid; + rte_dma_next_dev; rte_dma_start; rte_dma_stats_get; rte_dma_stats_reset; From patchwork Fri Sep 17 13:54:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 99162 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E3EE2A0C46; Fri, 17 Sep 2021 15:55:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A1D98410E9; Fri, 17 Sep 2021 15:54:46 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id DD0F54111F for ; Fri, 17 Sep 2021 15:54:44 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10109"; a="286485167" X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="286485167" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2021 06:54:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="530730365" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by fmsmga004.fm.intel.com with ESMTP; 17 Sep 2021 06:54:42 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Fri, 17 Sep 2021 14:54:24 +0100 Message-Id: <20210917135429.90562-5-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210917135429.90562-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210917135429.90562-1-bruce.richardson@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v5 4/9] app/test: add basic dmadev instance tests X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Run basic sanity tests for configuring, starting and stopping a dmadev instance to help validate drivers. This also provides the framework for future tests for data-path operation. Signed-off-by: Bruce Richardson Reviewed-by: Conor Walsh Reviewed-by: Kevin Laatz --- app/test/test_dmadev.c | 72 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) -- 2.30.2 diff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c index e765ec5f2c..28fbdc0b1f 100644 --- a/app/test/test_dmadev.c +++ b/app/test/test_dmadev.c @@ -3,6 +3,8 @@ * Copyright(c) 2021 Intel Corporation */ +#include + #include #include @@ -11,6 +13,65 @@ /* from test_dmadev_api.c */ extern int test_dma_api(uint16_t dev_id); +#define ERR_RETURN(...) do { print_err(__func__, __LINE__, __VA_ARGS__); return -1; } while (0) + +static void +__rte_format_printf(3, 4) +print_err(const char *func, int lineno, const char *format, ...) +{ + va_list ap; + + fprintf(stderr, "In %s:%d - ", func, lineno); + va_start(ap, format); + vfprintf(stderr, format, ap); + va_end(ap); +} + +static int +test_dmadev_instance(uint16_t dev_id) +{ +#define TEST_RINGSIZE 512 + struct rte_dma_stats stats; + struct rte_dma_info info; + const struct rte_dma_conf conf = { .nb_vchans = 1}; + const struct rte_dma_vchan_conf qconf = { + .direction = RTE_DMA_DIR_MEM_TO_MEM, + .nb_desc = TEST_RINGSIZE, + }; + const int vchan = 0; + + printf("\n### Test dmadev instance %u\n", dev_id); + + rte_dma_info_get(dev_id, &info); + if (info.max_vchans < 1) + ERR_RETURN("Error, no channels available on device id %u\n", dev_id); + + if (rte_dma_configure(dev_id, &conf) != 0) + ERR_RETURN("Error with rte_dma_configure()\n"); + + if (rte_dma_vchan_setup(dev_id, vchan, &qconf) < 0) + ERR_RETURN("Error with queue configuration\n"); + + rte_dma_info_get(dev_id, &info); + if (info.nb_vchans != 1) + ERR_RETURN("Error, no configured queues reported on device id %u\n", dev_id); + + if (rte_dma_start(dev_id) != 0) + ERR_RETURN("Error with rte_dma_start()\n"); + + if (rte_dma_stats_get(dev_id, vchan, &stats) != 0) + ERR_RETURN("Error with rte_dma_stats_get()\n"); + + if (stats.completed != 0 || stats.submitted != 0 || stats.errors != 0) + ERR_RETURN("Error device stats are not all zero: completed = %"PRIu64", " + "submitted = %"PRIu64", errors = %"PRIu64"\n", + stats.completed, stats.submitted, stats.errors); + + rte_dma_stop(dev_id); + rte_dma_stats_reset(dev_id, vchan); + return 0; +} + static int test_apis(void) { @@ -33,9 +94,18 @@ test_apis(void) static int test_dma(void) { + int i; + /* basic sanity on dmadev infrastructure */ if (test_apis() < 0) - return -1; + ERR_RETURN("Error performing API tests\n"); + + if (rte_dma_count_avail() == 0) + return TEST_SKIPPED; + + RTE_DMA_FOREACH_DEV(i) + if (test_dmadev_instance(i) < 0) + ERR_RETURN("Error, test failure for device %d\n", i); return 0; } From patchwork Fri Sep 17 13:54:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 99163 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3799AA0C46; Fri, 17 Sep 2021 15:55:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C215841122; Fri, 17 Sep 2021 15:54:48 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 457E741136 for ; Fri, 17 Sep 2021 15:54:47 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10109"; a="286485171" X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="286485171" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2021 06:54:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="530730370" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by fmsmga004.fm.intel.com with ESMTP; 17 Sep 2021 06:54:45 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Fri, 17 Sep 2021 14:54:25 +0100 Message-Id: <20210917135429.90562-6-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210917135429.90562-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210917135429.90562-1-bruce.richardson@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v5 5/9] app/test: add basic dmadev copy tests X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" For each dmadev instance, perform some basic copy tests to validate that functionality. Signed-off-by: Bruce Richardson Reviewed-by: Kevin Laatz Reviewed-by: Conor Walsh --- app/test/test_dmadev.c | 175 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) -- 2.30.2 diff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c index 28fbdc0b1f..2f22b6e382 100644 --- a/app/test/test_dmadev.c +++ b/app/test/test_dmadev.c @@ -6,6 +6,10 @@ #include #include +#include +#include +#include +#include #include #include "test.h" @@ -15,6 +19,11 @@ extern int test_dma_api(uint16_t dev_id); #define ERR_RETURN(...) do { print_err(__func__, __LINE__, __VA_ARGS__); return -1; } while (0) +#define COPY_LEN 1024 + +static struct rte_mempool *pool; +static uint16_t id_count; + static void __rte_format_printf(3, 4) print_err(const char *func, int lineno, const char *format, ...) @@ -27,10 +36,155 @@ print_err(const char *func, int lineno, const char *format, ...) va_end(ap); } +static int +runtest(const char *printable, int (*test_fn)(int dev_id, uint16_t vchan), int iterations, + int dev_id, uint16_t vchan, bool check_err_stats) +{ + struct rte_dma_stats stats; + int i; + + rte_dma_stats_reset(dev_id, vchan); + printf("DMA Dev %d: Running %s Tests %s\n", dev_id, printable, + check_err_stats ? " " : "(errors expected)"); + for (i = 0; i < iterations; i++) { + if (test_fn(dev_id, vchan) < 0) + return -1; + + rte_dma_stats_get(dev_id, 0, &stats); + printf("Ops submitted: %"PRIu64"\t", stats.submitted); + printf("Ops completed: %"PRIu64"\t", stats.completed); + printf("Errors: %"PRIu64"\r", stats.errors); + + if (stats.completed != stats.submitted) + ERR_RETURN("\nError, not all submitted jobs are reported as completed\n"); + if (check_err_stats && stats.errors != 0) + ERR_RETURN("\nErrors reported during op processing, aborting tests\n"); + } + printf("\n"); + return 0; +} + +static void +await_hw(int dev_id, uint16_t vchan) +{ + enum rte_dma_vchan_status st; + + if (rte_dma_vchan_status(dev_id, vchan, &st) < 0) { + /* for drivers that don't support this op, just sleep for 1 millisecond */ + rte_delay_us_sleep(1000); + return; + } + + /* for those that do, *max* end time is one second from now, but all should be faster */ + const uint64_t end_cycles = rte_get_timer_cycles() + rte_get_timer_hz(); + while (st == RTE_DMA_VCHAN_ACTIVE && rte_get_timer_cycles() < end_cycles) { + rte_pause(); + rte_dma_vchan_status(dev_id, vchan, &st); + } +} + +static int +test_enqueue_copies(int dev_id, uint16_t vchan) +{ + unsigned int i; + uint16_t id; + + /* test doing a single copy */ + do { + struct rte_mbuf *src, *dst; + char *src_data, *dst_data; + + src = rte_pktmbuf_alloc(pool); + dst = rte_pktmbuf_alloc(pool); + src_data = rte_pktmbuf_mtod(src, char *); + dst_data = rte_pktmbuf_mtod(dst, char *); + + for (i = 0; i < COPY_LEN; i++) + src_data[i] = rte_rand() & 0xFF; + + id = rte_dma_copy(dev_id, vchan, rte_pktmbuf_iova(src), rte_pktmbuf_iova(dst), + COPY_LEN, RTE_DMA_OP_FLAG_SUBMIT); + if (id != id_count) + ERR_RETURN("Error with rte_dma_copy, got %u, expected %u\n", + id, id_count); + + /* give time for copy to finish, then check it was done */ + await_hw(dev_id, vchan); + + for (i = 0; i < COPY_LEN; i++) + if (dst_data[i] != src_data[i]) + ERR_RETURN("Data mismatch at char %u [Got %02x not %02x]\n", i, + dst_data[i], src_data[i]); + + /* now check completion works */ + if (rte_dma_completed(dev_id, vchan, 1, &id, NULL) != 1) + ERR_RETURN("Error with rte_dma_completed\n"); + + if (id != id_count) + ERR_RETURN("Error:incorrect job id received, %u [expected %u]\n", + id, id_count); + + rte_pktmbuf_free(src); + rte_pktmbuf_free(dst); + + /* now check completion returns nothing more */ + if (rte_dma_completed(dev_id, 0, 1, NULL, NULL) != 0) + ERR_RETURN("Error with rte_dma_completed in empty check\n"); + + id_count++; + + } while (0); + + /* test doing a multiple single copies */ + do { + const uint16_t max_ops = 4; + struct rte_mbuf *src, *dst; + char *src_data, *dst_data; + uint16_t count; + + src = rte_pktmbuf_alloc(pool); + dst = rte_pktmbuf_alloc(pool); + src_data = rte_pktmbuf_mtod(src, char *); + dst_data = rte_pktmbuf_mtod(dst, char *); + + for (i = 0; i < COPY_LEN; i++) + src_data[i] = rte_rand() & 0xFF; + + /* perform the same copy times */ + for (i = 0; i < max_ops; i++) + if (rte_dma_copy(dev_id, vchan, + rte_pktmbuf_iova(src), + rte_pktmbuf_iova(dst), + COPY_LEN, RTE_DMA_OP_FLAG_SUBMIT) != id_count++) + ERR_RETURN("Error with rte_dma_copy\n"); + + await_hw(dev_id, vchan); + + count = rte_dma_completed(dev_id, vchan, max_ops * 2, &id, NULL); + if (count != max_ops) + ERR_RETURN("Error with rte_dma_completed, got %u not %u\n", + count, max_ops); + + if (id != id_count - 1) + ERR_RETURN("Error, incorrect job id returned: got %u not %u\n", + id, id_count - 1); + + for (i = 0; i < COPY_LEN; i++) + if (dst_data[i] != src_data[i]) + ERR_RETURN("Data mismatch at char %u\n", i); + + rte_pktmbuf_free(src); + rte_pktmbuf_free(dst); + } while (0); + + return 0; +} + static int test_dmadev_instance(uint16_t dev_id) { #define TEST_RINGSIZE 512 +#define CHECK_ERRS true struct rte_dma_stats stats; struct rte_dma_info info; const struct rte_dma_conf conf = { .nb_vchans = 1}; @@ -66,10 +220,31 @@ test_dmadev_instance(uint16_t dev_id) ERR_RETURN("Error device stats are not all zero: completed = %"PRIu64", " "submitted = %"PRIu64", errors = %"PRIu64"\n", stats.completed, stats.submitted, stats.errors); + id_count = 0; + + /* create a mempool for running tests */ + pool = rte_pktmbuf_pool_create("TEST_DMADEV_POOL", + TEST_RINGSIZE * 2, /* n == num elements */ + 32, /* cache size */ + 0, /* priv size */ + 2048, /* data room size */ + info.numa_node); + if (pool == NULL) + ERR_RETURN("Error with mempool creation\n"); + /* run the test cases, use many iterations to ensure UINT16_MAX id wraparound */ + if (runtest("copy", test_enqueue_copies, 640, dev_id, vchan, CHECK_ERRS) < 0) + goto err; + + rte_mempool_free(pool); rte_dma_stop(dev_id); rte_dma_stats_reset(dev_id, vchan); return 0; + +err: + rte_mempool_free(pool); + rte_dma_stop(dev_id); + return -1; } static int From patchwork Fri Sep 17 13:54:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 99164 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D0871A0C46; Fri, 17 Sep 2021 15:55:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E13304113B; Fri, 17 Sep 2021 15:54:50 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id BE48B4113A for ; Fri, 17 Sep 2021 15:54:49 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10109"; a="286485178" X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="286485178" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2021 06:54:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="530730382" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by fmsmga004.fm.intel.com with ESMTP; 17 Sep 2021 06:54:47 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Fri, 17 Sep 2021 14:54:26 +0100 Message-Id: <20210917135429.90562-7-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210917135429.90562-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210917135429.90562-1-bruce.richardson@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v5 6/9] app/test: add more comprehensive dmadev copy tests X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add unit tests for various combinations of use for dmadev, copying bursts of packets in various formats, e.g. 1. enqueuing two smaller bursts and completing them as one burst 2. enqueuing one burst and gathering completions in smaller bursts 3. using completed_status() function to gather completions rather than just completed() Signed-off-by: Bruce Richardson Reviewed-by: Kevin Laatz Reviewed-by: Conor Walsh --- app/test/test_dmadev.c | 101 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 100 insertions(+), 1 deletion(-) -- 2.30.2 diff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c index 2f22b6e382..3a1373b1ef 100644 --- a/app/test/test_dmadev.c +++ b/app/test/test_dmadev.c @@ -83,6 +83,98 @@ await_hw(int dev_id, uint16_t vchan) } } +/* run a series of copy tests just using some different options for enqueues and completions */ +static int +do_multi_copies(int dev_id, uint16_t vchan, + int split_batches, /* submit 2 x 16 or 1 x 32 burst */ + int split_completions, /* gather 2 x 16 or 1 x 32 completions */ + int use_completed_status) /* use completed or completed_status function */ +{ + struct rte_mbuf *srcs[32], *dsts[32]; + enum rte_dma_status_code sc[32]; + unsigned int i, j; + bool dma_err = false; + + /* Enqueue burst of copies and hit doorbell */ + for (i = 0; i < RTE_DIM(srcs); i++) { + uint64_t *src_data; + + if (split_batches && i == RTE_DIM(srcs) / 2) + rte_dma_submit(dev_id, vchan); + + srcs[i] = rte_pktmbuf_alloc(pool); + dsts[i] = rte_pktmbuf_alloc(pool); + if (srcs[i] == NULL || dsts[i] == NULL) + ERR_RETURN("Error allocating buffers\n"); + + src_data = rte_pktmbuf_mtod(srcs[i], uint64_t *); + for (j = 0; j < COPY_LEN/sizeof(uint64_t); j++) + src_data[j] = rte_rand(); + + if (rte_dma_copy(dev_id, vchan, srcs[i]->buf_iova + srcs[i]->data_off, + dsts[i]->buf_iova + dsts[i]->data_off, COPY_LEN, 0) != id_count++) + ERR_RETURN("Error with rte_dma_copy for buffer %u\n", i); + } + rte_dma_submit(dev_id, vchan); + + await_hw(dev_id, vchan); + + if (split_completions) { + /* gather completions in two halves */ + uint16_t half_len = RTE_DIM(srcs) / 2; + int ret = rte_dma_completed(dev_id, vchan, half_len, NULL, &dma_err); + if (ret != half_len || dma_err) + ERR_RETURN("Error with rte_dma_completed - first half. ret = %d, expected ret = %u, dma_err = %d\n", + ret, half_len, dma_err); + + ret = rte_dma_completed(dev_id, vchan, half_len, NULL, &dma_err); + if (ret != half_len || dma_err) + ERR_RETURN("Error with rte_dma_completed - second half. ret = %d, expected ret = %u, dma_err = %d\n", + ret, half_len, dma_err); + } else { + /* gather all completions in one go, using either + * completed or completed_status fns + */ + if (!use_completed_status) { + int n = rte_dma_completed(dev_id, vchan, RTE_DIM(srcs), NULL, &dma_err); + if (n != RTE_DIM(srcs) || dma_err) + ERR_RETURN("Error with rte_dma_completed, %u [expected: %zu], dma_err = %d\n", + n, RTE_DIM(srcs), dma_err); + } else { + int n = rte_dma_completed_status(dev_id, vchan, RTE_DIM(srcs), NULL, sc); + if (n != RTE_DIM(srcs)) + ERR_RETURN("Error with rte_dma_completed_status, %u [expected: %zu]\n", + n, RTE_DIM(srcs)); + + for (j = 0; j < (uint16_t)n; j++) + if (sc[j] != RTE_DMA_STATUS_SUCCESSFUL) + ERR_RETURN("Error with rte_dma_completed_status, job %u reports failure [code %u]\n", + j, sc[j]); + } + } + + /* check for empty */ + int ret = use_completed_status ? + rte_dma_completed_status(dev_id, vchan, RTE_DIM(srcs), NULL, sc) : + rte_dma_completed(dev_id, vchan, RTE_DIM(srcs), NULL, &dma_err); + if (ret != 0) + ERR_RETURN("Error with completion check - ops unexpectedly returned\n"); + + for (i = 0; i < RTE_DIM(srcs); i++) { + char *src_data, *dst_data; + + src_data = rte_pktmbuf_mtod(srcs[i], char *); + dst_data = rte_pktmbuf_mtod(dsts[i], char *); + for (j = 0; j < COPY_LEN; j++) + if (src_data[j] != dst_data[j]) + ERR_RETURN("Error with copy of packet %u, byte %u\n", i, j); + + rte_pktmbuf_free(srcs[i]); + rte_pktmbuf_free(dsts[i]); + } + return 0; +} + static int test_enqueue_copies(int dev_id, uint16_t vchan) { @@ -177,7 +269,14 @@ test_enqueue_copies(int dev_id, uint16_t vchan) rte_pktmbuf_free(dst); } while (0); - return 0; + /* test doing multiple copies */ + return do_multi_copies(dev_id, vchan, 0, 0, 0) /* enqueue and complete 1 batch at a time */ + /* enqueue 2 batches and then complete both */ + || do_multi_copies(dev_id, vchan, 1, 0, 0) + /* enqueue 1 batch, then complete in two halves */ + || do_multi_copies(dev_id, vchan, 0, 1, 0) + /* test using completed_status in place of regular completed API */ + || do_multi_copies(dev_id, vchan, 0, 0, 1); } static int From patchwork Fri Sep 17 13:54:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 99165 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 51490A0C46; Fri, 17 Sep 2021 15:55:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1E26941144; Fri, 17 Sep 2021 15:54:55 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 92F8041145 for ; Fri, 17 Sep 2021 15:54:52 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10109"; a="286485186" X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="286485186" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2021 06:54:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="530730388" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by fmsmga004.fm.intel.com with ESMTP; 17 Sep 2021 06:54:50 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Fri, 17 Sep 2021 14:54:27 +0100 Message-Id: <20210917135429.90562-8-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210917135429.90562-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210917135429.90562-1-bruce.richardson@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v5 7/9] app/test: test dmadev instance failure handling X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add a series of tests to inject bad copy operations into a dmadev to test the error handling and reporting capabilities. Various combinations of errors in various positions in a burst are tested, as are errors in bursts with fence flag set, and multiple errors in a single burst. Signed-off-by: Bruce Richardson Reviewed-by: Kevin Laatz Reviewed-by: Conor Walsh --- app/test/test_dmadev.c | 357 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 357 insertions(+) -- 2.30.2 diff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c index 3a1373b1ef..656012239d 100644 --- a/app/test/test_dmadev.c +++ b/app/test/test_dmadev.c @@ -279,6 +279,354 @@ test_enqueue_copies(int dev_id, uint16_t vchan) || do_multi_copies(dev_id, vchan, 0, 0, 1); } +/* Failure handling test cases - global macros and variables for those tests*/ +#define COMP_BURST_SZ 16 +#define OPT_FENCE(idx) ((fence && idx == 8) ? RTE_DMA_OP_FLAG_FENCE : 0) + +static int +test_failure_in_full_burst(int dev_id, uint16_t vchan, bool fence, + struct rte_mbuf **srcs, struct rte_mbuf **dsts, unsigned int fail_idx) +{ + /* Test single full batch statuses with failures */ + enum rte_dma_status_code status[COMP_BURST_SZ]; + struct rte_dma_stats baseline, stats; + uint16_t invalid_addr_id = 0; + uint16_t idx; + uint16_t count, status_count; + unsigned int i; + bool error = false; + int err_count = 0; + + rte_dma_stats_get(dev_id, vchan, &baseline); /* get a baseline set of stats */ + for (i = 0; i < COMP_BURST_SZ; i++) { + int id = rte_dma_copy(dev_id, vchan, + (i == fail_idx ? 0 : (srcs[i]->buf_iova + srcs[i]->data_off)), + dsts[i]->buf_iova + dsts[i]->data_off, + COPY_LEN, OPT_FENCE(i)); + if (id < 0) + ERR_RETURN("Error with rte_dma_copy for buffer %u\n", i); + if (i == fail_idx) + invalid_addr_id = id; + } + rte_dma_submit(dev_id, vchan); + rte_dma_stats_get(dev_id, vchan, &stats); + if (stats.submitted != baseline.submitted + COMP_BURST_SZ) + ERR_RETURN("Submitted stats value not as expected, %"PRIu64" not %"PRIu64"\n", + stats.submitted, baseline.submitted + COMP_BURST_SZ); + + await_hw(dev_id, vchan); + + count = rte_dma_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error); + if (count != fail_idx) + ERR_RETURN("Error with rte_dma_completed for failure test. Got returned %u not %u.\n", + count, fail_idx); + if (!error) + ERR_RETURN("Error, missing expected failed copy, %u. has_error is not set\n", + fail_idx); + if (idx != invalid_addr_id - 1) + ERR_RETURN("Error, missing expected failed copy, %u. Got last idx %u, not %u\n", + fail_idx, idx, invalid_addr_id - 1); + + /* all checks ok, now verify calling completed() again always returns 0 */ + for (i = 0; i < 10; i++) + if (rte_dma_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error) != 0 + || error == false || idx != (invalid_addr_id - 1)) + ERR_RETURN("Error with follow-up completed calls for fail idx %u\n", + fail_idx); + + status_count = rte_dma_completed_status(dev_id, vchan, COMP_BURST_SZ, + &idx, status); + /* some HW may stop on error and be restarted after getting error status for single value + * To handle this case, if we get just one error back, wait for more completions and get + * status for rest of the burst + */ + if (status_count == 1) { + await_hw(dev_id, vchan); + status_count += rte_dma_completed_status(dev_id, vchan, COMP_BURST_SZ - 1, + &idx, &status[1]); + } + /* check that at this point we have all status values */ + if (status_count != COMP_BURST_SZ - count) + ERR_RETURN("Error with completed_status calls for fail idx %u. Got %u not %u\n", + fail_idx, status_count, COMP_BURST_SZ - count); + /* now verify just one failure followed by multiple successful or skipped entries */ + if (status[0] == RTE_DMA_STATUS_SUCCESSFUL) + ERR_RETURN("Error with status returned for fail idx %u. First status was not failure\n", + fail_idx); + for (i = 1; i < status_count; i++) + /* after a failure in a burst, depending on ordering/fencing, + * operations may be successful or skipped because of previous error. + */ + if (status[i] != RTE_DMA_STATUS_SUCCESSFUL + && status[i] != RTE_DMA_STATUS_NOT_ATTEMPTED) + ERR_RETURN("Error with status calls for fail idx %u. Status for job %u (of %u) is not successful\n", + fail_idx, count + i, COMP_BURST_SZ); + + /* check the completed + errors stats are as expected */ + rte_dma_stats_get(dev_id, vchan, &stats); + if (stats.completed != baseline.completed + COMP_BURST_SZ) + ERR_RETURN("Completed stats value not as expected, %"PRIu64" not %"PRIu64"\n", + stats.completed, baseline.completed + COMP_BURST_SZ); + for (i = 0; i < status_count; i++) + err_count += (status[i] != RTE_DMA_STATUS_SUCCESSFUL); + if (stats.errors != baseline.errors + err_count) + ERR_RETURN("'Errors' stats value not as expected, %"PRIu64" not %"PRIu64"\n", + stats.errors, baseline.errors + err_count); + + return 0; +} + +static int +test_individual_status_query_with_failure(int dev_id, uint16_t vchan, bool fence, + struct rte_mbuf **srcs, struct rte_mbuf **dsts, unsigned int fail_idx) +{ + /* Test gathering batch statuses one at a time */ + enum rte_dma_status_code status[COMP_BURST_SZ]; + uint16_t invalid_addr_id = 0; + uint16_t idx; + uint16_t count = 0, status_count = 0; + unsigned int j; + bool error = false; + + for (j = 0; j < COMP_BURST_SZ; j++) { + int id = rte_dma_copy(dev_id, vchan, + (j == fail_idx ? 0 : (srcs[j]->buf_iova + srcs[j]->data_off)), + dsts[j]->buf_iova + dsts[j]->data_off, + COPY_LEN, OPT_FENCE(j)); + if (id < 0) + ERR_RETURN("Error with rte_dma_copy for buffer %u\n", j); + if (j == fail_idx) + invalid_addr_id = id; + } + rte_dma_submit(dev_id, vchan); + await_hw(dev_id, vchan); + + /* use regular "completed" until we hit error */ + while (!error) { + uint16_t n = rte_dma_completed(dev_id, vchan, 1, &idx, &error); + count += n; + if (n > 1 || count >= COMP_BURST_SZ) + ERR_RETURN("Error - too many completions got\n"); + if (n == 0 && !error) + ERR_RETURN("Error, unexpectedly got zero completions after %u completed\n", + count); + } + if (idx != invalid_addr_id - 1) + ERR_RETURN("Error, last successful index not as expected, got %u, expected %u\n", + idx, invalid_addr_id - 1); + + /* use completed_status until we hit end of burst */ + while (count + status_count < COMP_BURST_SZ) { + uint16_t n = rte_dma_completed_status(dev_id, vchan, 1, &idx, + &status[status_count]); + await_hw(dev_id, vchan); /* allow delay to ensure jobs are completed */ + status_count += n; + if (n != 1) + ERR_RETURN("Error: unexpected number of completions received, %u, not 1\n", + n); + } + + /* check for single failure */ + if (status[0] == RTE_DMA_STATUS_SUCCESSFUL) + ERR_RETURN("Error, unexpected successful DMA transaction\n"); + for (j = 1; j < status_count; j++) + if (status[j] != RTE_DMA_STATUS_SUCCESSFUL + && status[j] != RTE_DMA_STATUS_NOT_ATTEMPTED) + ERR_RETURN("Error, unexpected DMA error reported\n"); + + return 0; +} + +static int +test_single_item_status_query_with_failure(int dev_id, uint16_t vchan, + struct rte_mbuf **srcs, struct rte_mbuf **dsts, unsigned int fail_idx) +{ + /* When error occurs just collect a single error using "completed_status()" + * before going to back to completed() calls + */ + enum rte_dma_status_code status; + uint16_t invalid_addr_id = 0; + uint16_t idx; + uint16_t count, status_count, count2; + unsigned int j; + bool error = false; + + for (j = 0; j < COMP_BURST_SZ; j++) { + int id = rte_dma_copy(dev_id, vchan, + (j == fail_idx ? 0 : (srcs[j]->buf_iova + srcs[j]->data_off)), + dsts[j]->buf_iova + dsts[j]->data_off, + COPY_LEN, 0); + if (id < 0) + ERR_RETURN("Error with rte_dma_copy for buffer %u\n", j); + if (j == fail_idx) + invalid_addr_id = id; + } + rte_dma_submit(dev_id, vchan); + await_hw(dev_id, vchan); + + /* get up to the error point */ + count = rte_dma_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error); + if (count != fail_idx) + ERR_RETURN("Error with rte_dma_completed for failure test. Got returned %u not %u.\n", + count, fail_idx); + if (!error) + ERR_RETURN("Error, missing expected failed copy, %u. has_error is not set\n", + fail_idx); + if (idx != invalid_addr_id - 1) + ERR_RETURN("Error, missing expected failed copy, %u. Got last idx %u, not %u\n", + fail_idx, idx, invalid_addr_id - 1); + + /* get the error code */ + status_count = rte_dma_completed_status(dev_id, vchan, 1, &idx, &status); + if (status_count != 1) + ERR_RETURN("Error with completed_status calls for fail idx %u. Got %u not %u\n", + fail_idx, status_count, COMP_BURST_SZ - count); + if (status == RTE_DMA_STATUS_SUCCESSFUL) + ERR_RETURN("Error with status returned for fail idx %u. First status was not failure\n", + fail_idx); + + /* delay in case time needed after err handled to complete other jobs */ + await_hw(dev_id, vchan); + + /* get the rest of the completions without status */ + count2 = rte_dma_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error); + if (error == true) + ERR_RETURN("Error, got further errors post completed_status() call, for failure case %u.\n", + fail_idx); + if (count + status_count + count2 != COMP_BURST_SZ) + ERR_RETURN("Error, incorrect number of completions received, got %u not %u\n", + count + status_count + count2, COMP_BURST_SZ); + + return 0; +} + +static int +test_multi_failure(int dev_id, uint16_t vchan, struct rte_mbuf **srcs, struct rte_mbuf **dsts, + const unsigned int *fail, size_t num_fail) +{ + /* test having multiple errors in one go */ + enum rte_dma_status_code status[COMP_BURST_SZ]; + unsigned int i, j; + uint16_t count, err_count = 0; + bool error = false; + + /* enqueue and gather completions in one go */ + for (j = 0; j < COMP_BURST_SZ; j++) { + uintptr_t src = srcs[j]->buf_iova + srcs[j]->data_off; + /* set up for failure if the current index is anywhere is the fails array */ + for (i = 0; i < num_fail; i++) + if (j == fail[i]) + src = 0; + + int id = rte_dma_copy(dev_id, vchan, + src, dsts[j]->buf_iova + dsts[j]->data_off, + COPY_LEN, 0); + if (id < 0) + ERR_RETURN("Error with rte_dma_copy for buffer %u\n", j); + } + rte_dma_submit(dev_id, vchan); + await_hw(dev_id, vchan); + + count = rte_dma_completed_status(dev_id, vchan, COMP_BURST_SZ, NULL, status); + while (count < COMP_BURST_SZ) { + await_hw(dev_id, vchan); + + uint16_t ret = rte_dma_completed_status(dev_id, vchan, COMP_BURST_SZ - count, + NULL, &status[count]); + if (ret == 0) + ERR_RETURN("Error getting all completions for jobs. Got %u of %u\n", + count, COMP_BURST_SZ); + count += ret; + } + for (i = 0; i < count; i++) + if (status[i] != RTE_DMA_STATUS_SUCCESSFUL) + err_count++; + + if (err_count != num_fail) + ERR_RETURN("Error: Invalid number of failed completions returned, %u; expected %zu\n", + err_count, num_fail); + + /* enqueue and gather completions in bursts, but getting errors one at a time */ + for (j = 0; j < COMP_BURST_SZ; j++) { + uintptr_t src = srcs[j]->buf_iova + srcs[j]->data_off; + /* set up for failure if the current index is anywhere is the fails array */ + for (i = 0; i < num_fail; i++) + if (j == fail[i]) + src = 0; + + int id = rte_dma_copy(dev_id, vchan, + src, dsts[j]->buf_iova + dsts[j]->data_off, + COPY_LEN, 0); + if (id < 0) + ERR_RETURN("Error with rte_dma_copy for buffer %u\n", j); + } + rte_dma_submit(dev_id, vchan); + await_hw(dev_id, vchan); + + count = 0; + err_count = 0; + while (count + err_count < COMP_BURST_SZ) { + count += rte_dma_completed(dev_id, vchan, COMP_BURST_SZ, NULL, &error); + if (error) { + uint16_t ret = rte_dma_completed_status(dev_id, vchan, 1, + NULL, status); + if (ret != 1) + ERR_RETURN("Error getting error-status for completions\n"); + err_count += ret; + await_hw(dev_id, vchan); + } + } + if (err_count != num_fail) + ERR_RETURN("Error: Incorrect number of failed completions received, got %u not %zu\n", + err_count, num_fail); + + return 0; +} + +static int +test_completion_status(int dev_id, uint16_t vchan, bool fence) +{ + const unsigned int fail[] = {0, 7, 14, 15}; + struct rte_mbuf *srcs[COMP_BURST_SZ], *dsts[COMP_BURST_SZ]; + unsigned int i; + + for (i = 0; i < COMP_BURST_SZ; i++) { + srcs[i] = rte_pktmbuf_alloc(pool); + dsts[i] = rte_pktmbuf_alloc(pool); + } + + for (i = 0; i < RTE_DIM(fail); i++) { + if (test_failure_in_full_burst(dev_id, vchan, fence, srcs, dsts, fail[i]) < 0) + return -1; + + if (test_individual_status_query_with_failure(dev_id, vchan, fence, + srcs, dsts, fail[i]) < 0) + return -1; + + /* test is run the same fenced, or unfenced, but no harm in running it twice */ + if (test_single_item_status_query_with_failure(dev_id, vchan, + srcs, dsts, fail[i]) < 0) + return -1; + } + + if (test_multi_failure(dev_id, vchan, srcs, dsts, fail, RTE_DIM(fail)) < 0) + return -1; + + for (i = 0; i < COMP_BURST_SZ; i++) { + rte_pktmbuf_free(srcs[i]); + rte_pktmbuf_free(dsts[i]); + } + return 0; +} + +static int +test_completion_handling(int dev_id, uint16_t vchan) +{ + return test_completion_status(dev_id, vchan, false) /* without fences */ + || test_completion_status(dev_id, vchan, true); /* with fences */ + +} + static int test_dmadev_instance(uint16_t dev_id) { @@ -335,6 +683,15 @@ test_dmadev_instance(uint16_t dev_id) if (runtest("copy", test_enqueue_copies, 640, dev_id, vchan, CHECK_ERRS) < 0) goto err; + /* to test error handling we can provide null pointers for source or dest in copies. This + * requires VA mode in DPDK, since NULL(0) is a valid physical address. + */ + if (rte_eal_iova_mode() != RTE_IOVA_VA) + printf("DMA Dev %u: DPDK not in VA mode, skipping error handling tests\n", dev_id); + else if (runtest("error handling", test_completion_handling, 1, + dev_id, vchan, !CHECK_ERRS) < 0) + goto err; + rte_mempool_free(pool); rte_dma_stop(dev_id); rte_dma_stats_reset(dev_id, vchan); From patchwork Fri Sep 17 13:54:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 99166 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7535AA0C46; Fri, 17 Sep 2021 15:55:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A374341153; Fri, 17 Sep 2021 15:54:58 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id C478A41148 for ; Fri, 17 Sep 2021 15:54:55 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10109"; a="286485192" X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="286485192" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2021 06:54:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="530730397" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by fmsmga004.fm.intel.com with ESMTP; 17 Sep 2021 06:54:53 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Fri, 17 Sep 2021 14:54:28 +0100 Message-Id: <20210917135429.90562-9-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210917135429.90562-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210917135429.90562-1-bruce.richardson@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v5 8/9] app/test: add dmadev fill tests X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kevin Laatz For dma devices which support the fill operation, run unit tests to verify fill behaviour is correct. Signed-off-by: Kevin Laatz Signed-off-by: Bruce Richardson Reviewed-by: Conor Walsh --- app/test/test_dmadev.c | 49 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) -- 2.30.2 diff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c index 656012239d..f763cf273c 100644 --- a/app/test/test_dmadev.c +++ b/app/test/test_dmadev.c @@ -624,7 +624,51 @@ test_completion_handling(int dev_id, uint16_t vchan) { return test_completion_status(dev_id, vchan, false) /* without fences */ || test_completion_status(dev_id, vchan, true); /* with fences */ +} + +static int +test_enqueue_fill(int dev_id, uint16_t vchan) +{ + const unsigned int lengths[] = {8, 64, 1024, 50, 100, 89}; + struct rte_mbuf *dst; + char *dst_data; + uint64_t pattern = 0xfedcba9876543210; + unsigned int i, j; + + dst = rte_pktmbuf_alloc(pool); + if (dst == NULL) + ERR_RETURN("Failed to allocate mbuf\n"); + dst_data = rte_pktmbuf_mtod(dst, char *); + + for (i = 0; i < RTE_DIM(lengths); i++) { + /* reset dst_data */ + memset(dst_data, 0, rte_pktmbuf_data_len(dst)); + + /* perform the fill operation */ + int id = rte_dma_fill(dev_id, vchan, pattern, + rte_pktmbuf_iova(dst), lengths[i], RTE_DMA_OP_FLAG_SUBMIT); + if (id < 0) + ERR_RETURN("Error with rte_dma_fill\n"); + await_hw(dev_id, vchan); + + if (rte_dma_completed(dev_id, vchan, 1, NULL, NULL) != 1) + ERR_RETURN("Error: fill operation failed (length: %u)\n", lengths[i]); + /* check the data from the fill operation is correct */ + for (j = 0; j < lengths[i]; j++) { + char pat_byte = ((char *)&pattern)[j % 8]; + if (dst_data[j] != pat_byte) + ERR_RETURN("Error with fill operation (lengths = %u): got (%x), not (%x)\n", + lengths[i], dst_data[j], pat_byte); + } + /* check that the data after the fill operation was not written to */ + for (; j < rte_pktmbuf_data_len(dst); j++) + if (dst_data[j] != 0) + ERR_RETURN("Error, fill operation wrote too far (lengths = %u): got (%x), not (%x)\n", + lengths[i], dst_data[j], 0); + } + rte_pktmbuf_free(dst); + return 0; } static int @@ -692,6 +736,11 @@ test_dmadev_instance(uint16_t dev_id) dev_id, vchan, !CHECK_ERRS) < 0) goto err; + if ((info.dev_capa & RTE_DMA_CAPA_OPS_FILL) == 0) + printf("DMA Dev %u: No device fill support, skipping fill tests\n", dev_id); + else if (runtest("fill", test_enqueue_fill, 1, dev_id, vchan, CHECK_ERRS) < 0) + goto err; + rte_mempool_free(pool); rte_dma_stop(dev_id); rte_dma_stats_reset(dev_id, vchan); From patchwork Fri Sep 17 13:54:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 99167 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BA9AEA0C46; Fri, 17 Sep 2021 15:55:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CDF1B4115C; Fri, 17 Sep 2021 15:55:01 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 109E84114B for ; Fri, 17 Sep 2021 15:54:58 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10109"; a="286485196" X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="286485196" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2021 06:54:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="530730404" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by fmsmga004.fm.intel.com with ESMTP; 17 Sep 2021 06:54:56 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Fri, 17 Sep 2021 14:54:29 +0100 Message-Id: <20210917135429.90562-10-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210917135429.90562-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210917135429.90562-1-bruce.richardson@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v5 9/9] app/test: add dmadev burst capacity API test X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kevin Laatz Add a test case to validate the functionality of drivers' burst capacity API implementations. Signed-off-by: Kevin Laatz Signed-off-by: Bruce Richardson Reviewed-by: Conor Walsh --- app/test/test_dmadev.c | 68 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) -- 2.30.2 diff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c index f763cf273c..98fcab67f3 100644 --- a/app/test/test_dmadev.c +++ b/app/test/test_dmadev.c @@ -671,6 +671,69 @@ test_enqueue_fill(int dev_id, uint16_t vchan) return 0; } +static int +test_burst_capacity(int dev_id, uint16_t vchan) +{ +#define CAP_TEST_BURST_SIZE 64 + const int ring_space = rte_dma_burst_capacity(dev_id, vchan); + struct rte_mbuf *src, *dst; + int i, j, iter; + int cap, ret; + bool dma_err; + + src = rte_pktmbuf_alloc(pool); + dst = rte_pktmbuf_alloc(pool); + + /* to test capacity, we enqueue elements and check capacity is reduced + * by one each time - rebaselining the expected value after each burst + * as the capacity is only for a burst. We enqueue multiple bursts to + * fill up half the ring, before emptying it again. We do this twice to + * ensure that we get to test scenarios where we get ring wrap-around + */ + for (iter = 0; iter < 2; iter++) { + for (i = 0; i < (ring_space / (2 * CAP_TEST_BURST_SIZE)) + 1; i++) { + cap = rte_dma_burst_capacity(dev_id, vchan); + + for (j = 0; j < CAP_TEST_BURST_SIZE; j++) { + ret = rte_dma_copy(dev_id, vchan, rte_pktmbuf_iova(src), + rte_pktmbuf_iova(dst), COPY_LEN, 0); + if (ret < 0) + ERR_RETURN("Error with rte_dmadev_copy\n"); + + if (rte_dma_burst_capacity(dev_id, vchan) != cap - (j + 1)) + ERR_RETURN("Error, ring capacity did not change as expected\n"); + } + if (rte_dma_submit(dev_id, vchan) < 0) + ERR_RETURN("Error, failed to submit burst\n"); + + if (cap < rte_dma_burst_capacity(dev_id, vchan)) + ERR_RETURN("Error, avail ring capacity has gone up, not down\n"); + } + await_hw(dev_id, vchan); + + for (i = 0; i < (ring_space / (2 * CAP_TEST_BURST_SIZE)) + 1; i++) { + ret = rte_dma_completed(dev_id, vchan, + CAP_TEST_BURST_SIZE, NULL, &dma_err); + if (ret != CAP_TEST_BURST_SIZE || dma_err) { + enum rte_dma_status_code status; + + rte_dma_completed_status(dev_id, vchan, 1, NULL, &status); + ERR_RETURN("Error with rte_dmadev_completed, %u [expected: %u], dma_err = %d, i = %u, iter = %u, status = %u\n", + ret, CAP_TEST_BURST_SIZE, dma_err, i, iter, status); + } + } + cap = rte_dma_burst_capacity(dev_id, vchan); + if (cap != ring_space) + ERR_RETURN("Error, ring capacity has not reset to original value, got %u, expected %u\n", + cap, ring_space); + } + + rte_pktmbuf_free(src); + rte_pktmbuf_free(dst); + + return 0; +} + static int test_dmadev_instance(uint16_t dev_id) { @@ -741,6 +804,11 @@ test_dmadev_instance(uint16_t dev_id) else if (runtest("fill", test_enqueue_fill, 1, dev_id, vchan, CHECK_ERRS) < 0) goto err; + if (rte_dma_burst_capacity(dev_id, vchan) == -ENOTSUP) + printf("DMA Dev %u: Burst capacity API not supported, skipping tests\n", dev_id); + else if (runtest("burst capacity", test_burst_capacity, 1, dev_id, vchan, CHECK_ERRS) < 0) + goto err; + rte_mempool_free(pool); rte_dma_stop(dev_id); rte_dma_stats_reset(dev_id, vchan);