From patchwork Thu Sep 30 09:08:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100062 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2DD0DA0C41; Thu, 30 Sep 2021 11:08:55 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 083D4410EC; Thu, 30 Sep 2021 11:08:55 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B091540DDA for ; Thu, 30 Sep 2021 11:08:53 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18U1KPst001361 for ; Thu, 30 Sep 2021 02:08:52 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=93rIvAo8P94LjZmQFNtA+F9oXZl5OcDoUOQ9lE/lIoM=; b=PmWylsmp3FxHwskJbvXB6R/8irwAiVkHJgzcDjhsIjheSG27HQGEOhLcy8mscUDyV6cQ ipnmdVkg4JSPIyFe72HnCKBjETNDMR7SBzSUWEyMxlLpjIKR9choaXE/FN7g/rnCtPw0 b2/2fD09mK9enuEw7yz7BFuUh/te8vdsqC4tU6ojo/1XkQHnnYhU08Zc1HnEMhhe8XPd 4u5t7Kj4XSApjIZDpoA2NoG93CurckyMVYs2LVFyBObJejAQodLiZiXWSvAwd/67Ec2I ksTmDA62K/UhuBZkDQwW/A6Eu69tVcK4Ps3+YfzYZRp3EU2iG9DCUfAO67wZnWL4A6rX FA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3bd3g39kbe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 30 Sep 2021 02:08:52 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:08:49 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:08:50 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 753563F7068; Thu, 30 Sep 2021 02:08:48 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Date: Thu, 30 Sep 2021 14:38:18 +0530 Message-ID: <20210930090844.1059326-1-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210927082223.757436-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: -i0YpBCpcVNgvZPAXqhgun8RZL-8rR_5 X-Proofpoint-ORIG-GUID: -i0YpBCpcVNgvZPAXqhgun8RZL-8rR_5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 01/27] common/cnxk: update policer MBOX APIs and HW definitions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori To support ingress policer on CN10K, MBOX interfaces and HW definitions are synced. Signed-off-by: Sunil Kumar Kori Acked-by: Ray Kinsella --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/common/cnxk/hw/nix.h | 13 ++++++++++--- drivers/common/cnxk/roc_mbox.h | 34 +++++++++++++++++++++++++++++++++- 2 files changed, 43 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index 6b86002ead..53cdfbb142 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -692,9 +692,16 @@ #define NIX_RX_BAND_PROF_ACTIONRESULT_DROP (0x1ull) /* [CN10K, .) */ #define NIX_RX_BAND_PROF_ACTIONRESULT_RED (0x2ull) /* [CN10K, .) */ -#define NIX_RX_BAND_PROF_LAYER_LEAF (0x0ull) /* [CN10K, .) */ -#define NIX_RX_BAND_PROF_LAYER_MIDDLE (0x1ull) /* [CN10K, .) */ -#define NIX_RX_BAND_PROF_LAYER_TOP (0x2ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_LAYER_LEAF (0x0ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_LAYER_INVALID (0x1ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_LAYER_MIDDLE (0x2ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_LAYER_TOP (0x3ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_LAYER_MAX (0x4ull) /* [CN10K, .) */ + +#define NIX_RX_BAND_PROF_PC_MODE_VLAN (0x0ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_PC_MODE_DSCP (0x1ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_PC_MODE_GEN (0x2ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_PC_MODE_RSVD (0x3ull) /* [CN10K, .) */ #define NIX_RX_COLORRESULT_GREEN (0x0ull) /* [CN10K, .) */ #define NIX_RX_COLORRESULT_YELLOW (0x1ull) /* [CN10K, .) */ diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index b5da931b81..c8b97e9aee 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -234,7 +234,11 @@ struct mbox_msghdr { nix_inline_ipsec_lf_cfg, msg_rsp) \ M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ nix_cn10k_aq_enq_rsp) \ - M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) + M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ + M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, \ + nix_bandprof_alloc_req, nix_bandprof_alloc_rsp) \ + M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ + msg_rsp) /* Messages initiated by AF (range 0xC00 - 0xDFF) */ #define MBOX_UP_CGX_MESSAGES \ @@ -771,6 +775,10 @@ struct nix_cn10k_aq_enq_req { __io struct nix_rsse_s rss; /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */ __io struct nix_rx_mce_s mce; + /* Valid when op == WRITE/INIT and + * ctype == NIX_AQ_CTYPE_BAND_PROF + */ + __io struct nix_band_prof_s prof; }; /* Mask data when op == WRITE (1=write, 0=don't write) */ union { @@ -784,6 +792,8 @@ struct nix_cn10k_aq_enq_req { __io struct nix_rsse_s rss_mask; /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */ __io struct nix_rx_mce_s mce_mask; + /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_BAND_PROF */ + __io struct nix_band_prof_s prof_mask; }; }; @@ -795,6 +805,7 @@ struct nix_cn10k_aq_enq_rsp { struct nix_cq_ctx_s cq; struct nix_rsse_s rss; struct nix_rx_mce_s mce; + struct nix_band_prof_s prof; }; }; @@ -1129,6 +1140,27 @@ struct nix_hw_info { uint16_t __io rsvd[15]; }; +struct nix_bandprof_alloc_req { + struct mbox_msghdr hdr; + /* Count of profiles needed per layer */ + uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX]; +}; + +struct nix_bandprof_alloc_rsp { + struct mbox_msghdr hdr; + uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX]; + +#define BANDPROF_PER_PFFUNC 64 + uint16_t __io prof_idx[NIX_RX_BAND_PROF_LAYER_MAX][BANDPROF_PER_PFFUNC]; +}; + +struct nix_bandprof_free_req { + struct mbox_msghdr hdr; + uint8_t __io free_all; + uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX]; + uint16_t __io prof_idx[NIX_RX_BAND_PROF_LAYER_MAX][BANDPROF_PER_PFFUNC]; +}; + /* SSO mailbox error codes * Range 501 - 600. */ From patchwork Thu Sep 30 09:08:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100063 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8F8CAA0C41; Thu, 30 Sep 2021 11:08:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 24266410F1; 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Thu, 30 Sep 2021 02:08:54 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:08:52 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:08:52 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id A216B3F7067; Thu, 30 Sep 2021 02:08:50 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Thu, 30 Sep 2021 14:38:19 +0530 Message-ID: <20210930090844.1059326-2-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: O3JfQhSbLo-e-R-kSBRyuNjI-IH8NCGU X-Proofpoint-ORIG-GUID: O3JfQhSbLo-e-R-kSBRyuNjI-IH8NCGU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 02/27] common/cnxk: support RoC API to get level to index X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori CN10K platform supports policer up to 3 level of hierarchy. Implement RoC API to get corresponding index for given level. Signed-off-by: Sunil Kumar Kori --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_nix.h | 11 +++++++++++ drivers/common/cnxk/roc_nix_bpf.c | 22 ++++++++++++++++++++++ drivers/common/cnxk/roc_nix_priv.h | 1 + drivers/common/cnxk/roc_utils.c | 3 +++ drivers/common/cnxk/version.map | 1 + 6 files changed, 39 insertions(+) create mode 100644 drivers/common/cnxk/roc_nix_bpf.c diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 8a551d15d6..62901e66e7 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -25,6 +25,7 @@ sources = files( 'roc_mbox.c', 'roc_model.c', 'roc_nix.c', + 'roc_nix_bpf.c', 'roc_nix_debug.c', 'roc_nix_fc.c', 'roc_nix_irq.c', diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index b0e6fabe31..1488c24f59 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -6,6 +6,8 @@ #define _ROC_NIX_H_ /* Constants */ +#define ROC_NIX_BPF_LEVEL_IDX_INVALID 0xFF + enum roc_nix_rss_reta_sz { ROC_NIX_RSS_RETA_SZ_64 = 64, ROC_NIX_RSS_RETA_SZ_128 = 128, @@ -29,6 +31,12 @@ enum roc_nix_vlan_type { ROC_NIX_VLAN_TYPE_OUTER = 0x02, }; +enum roc_nix_bpf_level_flag { + ROC_NIX_BPF_LEVEL_F_LEAF = BIT(0), + ROC_NIX_BPF_LEVEL_F_MID = BIT(1), + ROC_NIX_BPF_LEVEL_F_TOP = BIT(2), +}; + struct roc_nix_vlan_config { uint32_t type; union { @@ -468,6 +476,9 @@ int __roc_api roc_nix_tm_rsrc_count(struct roc_nix *roc_nix, int __roc_api roc_nix_tm_node_name_get(struct roc_nix *roc_nix, uint32_t node_id, char *buf, size_t buflen); +/* Ingress Policer API */ +uint8_t __roc_api +roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag lvl_flag); /* MAC */ int __roc_api roc_nix_mac_rxtx_start_stop(struct roc_nix *roc_nix, bool start); diff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c new file mode 100644 index 0000000000..b588cc16e4 --- /dev/null +++ b/drivers/common/cnxk/roc_nix_bpf.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "roc_api.h" +#include "roc_priv.h" + +uint8_t +roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag level_f) +{ + uint8_t idx; + + if (level_f & ROC_NIX_BPF_LEVEL_F_LEAF) + idx = 0; + else if (level_f & ROC_NIX_BPF_LEVEL_F_MID) + idx = 1; + else if (level_f & ROC_NIX_BPF_LEVEL_F_TOP) + idx = 2; + else + idx = ROC_NIX_BPF_LEVEL_IDX_INVALID; + return idx; +} diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 9dc0c88a6f..94040fc744 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -170,6 +170,7 @@ enum nix_err_status { NIX_ERR_INVALID_RANGE, NIX_ERR_INTERNAL, NIX_ERR_OP_NOTSUP, + NIX_ERR_HW_NOTSUP, NIX_ERR_QUEUE_INVALID_RANGE, NIX_ERR_AQ_READ_FAILED, NIX_ERR_AQ_WRITE_FAILED, diff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c index 9cb8708a74..77dc279bcb 100644 --- a/drivers/common/cnxk/roc_utils.c +++ b/drivers/common/cnxk/roc_utils.c @@ -34,6 +34,9 @@ roc_error_msg_get(int errorcode) case NIX_ERR_OP_NOTSUP: err_msg = "Operation not supported"; break; + case NIX_ERR_HW_NOTSUP: + err_msg = "Hardware does not support"; + break; case NIX_ERR_QUEUE_INVALID_RANGE: err_msg = "Invalid Queue range"; break; diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 5df2e56ce6..c19f74fe91 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -77,6 +77,7 @@ INTERNAL { roc_model; roc_se_auth_key_set; roc_se_ciph_key_set; + roc_nix_bpf_level_to_idx; roc_nix_cq_dump; roc_nix_cq_fini; roc_nix_cq_init; From patchwork Thu Sep 30 09:08:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100064 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CBD30A0C41; Thu, 30 Sep 2021 11:09:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 326AB410ED; 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Thu, 30 Sep 2021 02:08:56 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:08:54 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:08:54 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 0F8D53F7068; Thu, 30 Sep 2021 02:08:52 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Thu, 30 Sep 2021 14:38:20 +0530 Message-ID: <20210930090844.1059326-3-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: alUdm-x5V3A84Eph-X4z1rMEEhJUrYdS X-Proofpoint-ORIG-GUID: alUdm-x5V3A84Eph-X4z1rMEEhJUrYdS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 03/27] common/cnxk: support RoC API to get profile count X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement interface to get available profile count for given nixlf. Signed-off-by: Sunil Kumar Kori --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/common/cnxk/roc_nix.h | 5 ++++ drivers/common/cnxk/roc_nix_bpf.c | 46 +++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 52 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 1488c24f59..3d3e169977 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -7,6 +7,7 @@ /* Constants */ #define ROC_NIX_BPF_LEVEL_IDX_INVALID 0xFF +#define ROC_NIX_BPF_LEVEL_MAX 3 enum roc_nix_rss_reta_sz { ROC_NIX_RSS_RETA_SZ_64 = 64, @@ -477,6 +478,10 @@ int __roc_api roc_nix_tm_node_name_get(struct roc_nix *roc_nix, uint32_t node_id, char *buf, size_t buflen); /* Ingress Policer API */ +int __roc_api +roc_nix_bpf_count_get(struct roc_nix *roc_nix, uint8_t lvl_mask, + uint16_t count[ROC_NIX_BPF_LEVEL_MAX] /* Out */); + uint8_t __roc_api roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag lvl_flag); diff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c index b588cc16e4..af9dffa90c 100644 --- a/drivers/common/cnxk/roc_nix_bpf.c +++ b/drivers/common/cnxk/roc_nix_bpf.c @@ -5,6 +5,14 @@ #include "roc_api.h" #include "roc_priv.h" +#define NIX_MAX_BPF_COUNT_LEAF_LAYER 64 +#define NIX_MAX_BPF_COUNT_MID_LAYER 8 +#define NIX_MAX_BPF_COUNT_TOP_LAYER 1 + +#define NIX_BPF_LEVEL_F_MASK \ + (ROC_NIX_BPF_LEVEL_F_LEAF | ROC_NIX_BPF_LEVEL_F_MID | \ + ROC_NIX_BPF_LEVEL_F_TOP) + uint8_t roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag level_f) { @@ -20,3 +28,41 @@ roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag level_f) idx = ROC_NIX_BPF_LEVEL_IDX_INVALID; return idx; } + +int +roc_nix_bpf_count_get(struct roc_nix *roc_nix, uint8_t lvl_mask, + uint16_t count[ROC_NIX_BPF_LEVEL_MAX]) +{ + uint8_t mask = lvl_mask & NIX_BPF_LEVEL_F_MASK; + uint8_t leaf_idx, mid_idx, top_idx; + + PLT_SET_USED(roc_nix); + + if (roc_model_is_cn9k()) + return NIX_ERR_HW_NOTSUP; + + if (!mask) + return NIX_ERR_PARAM; + + /* Currently No MBOX interface is available to get number + * of bandwidth profiles. So numbers per level are hard coded, + * considering 3 RPM blocks and each block has 4 LMAC's. + * So total 12 physical interfaces are in system. Each interface + * supports following bandwidth profiles. + */ + + leaf_idx = roc_nix_bpf_level_to_idx(mask & ROC_NIX_BPF_LEVEL_F_LEAF); + mid_idx = roc_nix_bpf_level_to_idx(mask & ROC_NIX_BPF_LEVEL_F_MID); + top_idx = roc_nix_bpf_level_to_idx(mask & ROC_NIX_BPF_LEVEL_F_TOP); + + if (leaf_idx != ROC_NIX_BPF_LEVEL_IDX_INVALID) + count[leaf_idx] = NIX_MAX_BPF_COUNT_LEAF_LAYER; + + if (mid_idx != ROC_NIX_BPF_LEVEL_IDX_INVALID) + count[mid_idx] = NIX_MAX_BPF_COUNT_MID_LAYER; + + if (top_idx != ROC_NIX_BPF_LEVEL_IDX_INVALID) + count[top_idx] = NIX_MAX_BPF_COUNT_TOP_LAYER; + + return 0; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index c19f74fe91..790a32e2e0 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -77,6 +77,7 @@ INTERNAL { roc_model; roc_se_auth_key_set; roc_se_ciph_key_set; + roc_nix_bpf_count_get; roc_nix_bpf_level_to_idx; roc_nix_cq_dump; roc_nix_cq_fini; From patchwork Thu Sep 30 09:08:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100065 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 54544A0C41; Thu, 30 Sep 2021 11:09:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4154E41109; Thu, 30 Sep 2021 11:09:03 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id AD07A41102 for ; Thu, 30 Sep 2021 11:09:01 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18U1KYVO001409; Thu, 30 Sep 2021 02:08:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=hwQt3fJozBHs9Fhovo/nhl63LcwnjHCL+9ex8qQYgnU=; b=ISZ7Yo4SWhsvpJEfbhoJqfPezSDJhpsfDefSc2nLdMSeBc/CugUcum1HvgkpKTZ/0Veu BKRkeaUZqlc/rTxzvqFg28++oVh4fD8WHGVeujY217eSMpbuWOqZxhPelW79NLFe/coK yqJo5bISCWswnzGiOrJZTBC2XVgQE5h3cLOQ56NNo/uOTh/9XY++rAMX7WoAD3zaPwYX oA9pf7Jsy+qnzCGxzDr0Q0PWJAWRNzDWFD+E4UYlXPnxaPPGvyEp6E0efP8Nb2MONyFH N7AGfLEcyRSv3HE58iktr+PzJ9UDLuvPcXwMvv4kT6GkJROT6F15WYCPEKrNSGYmfxNj Wg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3bd3g39kc6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 30 Sep 2021 02:08:59 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:08:57 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:08:57 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 741683F7067; Thu, 30 Sep 2021 02:08:55 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Thu, 30 Sep 2021 14:38:21 +0530 Message-ID: <20210930090844.1059326-4-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: gisqoQf5Q6HhNRbV4nyhcjD2hqvGed5x X-Proofpoint-ORIG-GUID: gisqoQf5Q6HhNRbV4nyhcjD2hqvGed5x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 04/27] common/cnxk: support RoC API to alloc bandwidth profiles X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement RoC API to allocate HW resources i.e. bandwidth profiles for policer processing on CN10K platform. Signed-off-by: Sunil Kumar Kori --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/common/cnxk/roc_nix.h | 11 ++++ drivers/common/cnxk/roc_nix_bpf.c | 104 ++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 116 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 3d3e169977..b55333a01c 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -6,6 +6,7 @@ #define _ROC_NIX_H_ /* Constants */ +#define ROC_NIX_BPF_PER_PFFUNC 64 #define ROC_NIX_BPF_LEVEL_IDX_INVALID 0xFF #define ROC_NIX_BPF_LEVEL_MAX 3 @@ -38,6 +39,12 @@ enum roc_nix_bpf_level_flag { ROC_NIX_BPF_LEVEL_F_TOP = BIT(2), }; +struct roc_nix_bpf_objs { + uint16_t level; + uint16_t count; + uint16_t ids[ROC_NIX_BPF_PER_PFFUNC]; +}; + struct roc_nix_vlan_config { uint32_t type; union { @@ -482,6 +489,10 @@ int __roc_api roc_nix_bpf_count_get(struct roc_nix *roc_nix, uint8_t lvl_mask, uint16_t count[ROC_NIX_BPF_LEVEL_MAX] /* Out */); +int __roc_api roc_nix_bpf_alloc(struct roc_nix *roc_nix, uint8_t lvl_mask, + uint16_t per_lvl_cnt[ROC_NIX_BPF_LEVEL_MAX], + struct roc_nix_bpf_objs *profs /* Out */); + uint8_t __roc_api roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag lvl_flag); diff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c index af9dffa90c..06394bda07 100644 --- a/drivers/common/cnxk/roc_nix_bpf.c +++ b/drivers/common/cnxk/roc_nix_bpf.c @@ -13,6 +13,19 @@ (ROC_NIX_BPF_LEVEL_F_LEAF | ROC_NIX_BPF_LEVEL_F_MID | \ ROC_NIX_BPF_LEVEL_F_TOP) +static uint8_t sw_to_hw_lvl_map[] = {NIX_RX_BAND_PROF_LAYER_LEAF, + NIX_RX_BAND_PROF_LAYER_MIDDLE, + NIX_RX_BAND_PROF_LAYER_TOP}; + +static inline struct mbox * +get_mbox(struct roc_nix *roc_nix) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct dev *dev = &nix->dev; + + return dev->mbox; +} + uint8_t roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag level_f) { @@ -66,3 +79,94 @@ roc_nix_bpf_count_get(struct roc_nix *roc_nix, uint8_t lvl_mask, return 0; } + +int +roc_nix_bpf_alloc(struct roc_nix *roc_nix, uint8_t lvl_mask, + uint16_t per_lvl_cnt[ROC_NIX_BPF_LEVEL_MAX], + struct roc_nix_bpf_objs *profs) +{ + uint8_t mask = lvl_mask & NIX_BPF_LEVEL_F_MASK; + struct mbox *mbox = get_mbox(roc_nix); + struct nix_bandprof_alloc_req *req; + struct nix_bandprof_alloc_rsp *rsp; + uint8_t leaf_idx, mid_idx, top_idx; + int rc = -ENOSPC, i; + + if (roc_model_is_cn9k()) + return NIX_ERR_HW_NOTSUP; + + if (!mask) + return NIX_ERR_PARAM; + + leaf_idx = roc_nix_bpf_level_to_idx(mask & ROC_NIX_BPF_LEVEL_F_LEAF); + mid_idx = roc_nix_bpf_level_to_idx(mask & ROC_NIX_BPF_LEVEL_F_MID); + top_idx = roc_nix_bpf_level_to_idx(mask & ROC_NIX_BPF_LEVEL_F_TOP); + + if ((leaf_idx != ROC_NIX_BPF_LEVEL_IDX_INVALID) && + (per_lvl_cnt[leaf_idx] > NIX_MAX_BPF_COUNT_LEAF_LAYER)) + return NIX_ERR_INVALID_RANGE; + + if ((mid_idx != ROC_NIX_BPF_LEVEL_IDX_INVALID) && + (per_lvl_cnt[mid_idx] > NIX_MAX_BPF_COUNT_MID_LAYER)) + return NIX_ERR_INVALID_RANGE; + + if ((top_idx != ROC_NIX_BPF_LEVEL_IDX_INVALID) && + (per_lvl_cnt[top_idx] > NIX_MAX_BPF_COUNT_TOP_LAYER)) + return NIX_ERR_INVALID_RANGE; + + req = mbox_alloc_msg_nix_bandprof_alloc(mbox); + if (req == NULL) + goto exit; + + if (leaf_idx != ROC_NIX_BPF_LEVEL_IDX_INVALID) { + req->prof_count[sw_to_hw_lvl_map[leaf_idx]] = + per_lvl_cnt[leaf_idx]; + } + + if (mid_idx != ROC_NIX_BPF_LEVEL_IDX_INVALID) { + req->prof_count[sw_to_hw_lvl_map[mid_idx]] = + per_lvl_cnt[mid_idx]; + } + + if (top_idx != ROC_NIX_BPF_LEVEL_IDX_INVALID) { + req->prof_count[sw_to_hw_lvl_map[top_idx]] = + per_lvl_cnt[top_idx]; + } + + rc = mbox_process_msg(mbox, (void *)&rsp); + if (rc) + goto exit; + + if (leaf_idx != ROC_NIX_BPF_LEVEL_IDX_INVALID) { + profs[leaf_idx].level = leaf_idx; + profs[leaf_idx].count = + rsp->prof_count[sw_to_hw_lvl_map[leaf_idx]]; + for (i = 0; i < profs[leaf_idx].count; i++) { + profs[leaf_idx].ids[i] = + rsp->prof_idx[sw_to_hw_lvl_map[leaf_idx]][i]; + } + } + + if (mid_idx != ROC_NIX_BPF_LEVEL_IDX_INVALID) { + profs[mid_idx].level = mid_idx; + profs[mid_idx].count = + rsp->prof_count[sw_to_hw_lvl_map[mid_idx]]; + for (i = 0; i < profs[mid_idx].count; i++) { + profs[mid_idx].ids[i] = + rsp->prof_idx[sw_to_hw_lvl_map[mid_idx]][i]; + } + } + + if (top_idx != ROC_NIX_BPF_LEVEL_IDX_INVALID) { + profs[top_idx].level = top_idx; + profs[top_idx].count = + rsp->prof_count[sw_to_hw_lvl_map[top_idx]]; + for (i = 0; i < profs[top_idx].count; i++) { + profs[top_idx].ids[i] = + rsp->prof_idx[sw_to_hw_lvl_map[top_idx]][i]; + } + } + +exit: + return rc; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 790a32e2e0..81e76919b5 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -77,6 +77,7 @@ INTERNAL { roc_model; roc_se_auth_key_set; roc_se_ciph_key_set; + roc_nix_bpf_alloc; roc_nix_bpf_count_get; roc_nix_bpf_level_to_idx; roc_nix_cq_dump; From patchwork Thu Sep 30 09:08:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100066 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EC949A0C41; Thu, 30 Sep 2021 11:09:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B0F4641123; Thu, 30 Sep 2021 11:09:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A763B4111D for ; Thu, 30 Sep 2021 11:09:04 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18U1KaVb001428; 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Thu, 30 Sep 2021 02:08:59 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:08:59 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id D77DF3F7068; Thu, 30 Sep 2021 02:08:57 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Thu, 30 Sep 2021 14:38:22 +0530 Message-ID: <20210930090844.1059326-5-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ZCht5n3xeWa92wOrxJmOg6LHLTBfF2MY X-Proofpoint-ORIG-GUID: ZCht5n3xeWa92wOrxJmOg6LHLTBfF2MY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 05/27] common/cnxk: support RoC API to free bandwidth profiles X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement RoC interface to free HW bandwidth profiles on CN10K platform. Signed-off-by: Sunil Kumar Kori --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/common/cnxk/roc_nix.h | 6 +++++ drivers/common/cnxk/roc_nix_bpf.c | 40 +++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 2 ++ 3 files changed, 48 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index b55333a01c..bf451ecdbc 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -493,6 +493,12 @@ int __roc_api roc_nix_bpf_alloc(struct roc_nix *roc_nix, uint8_t lvl_mask, uint16_t per_lvl_cnt[ROC_NIX_BPF_LEVEL_MAX], struct roc_nix_bpf_objs *profs /* Out */); +int __roc_api roc_nix_bpf_free(struct roc_nix *roc_nix, + struct roc_nix_bpf_objs *profs, + uint8_t num_prof); + +int __roc_api roc_nix_bpf_free_all(struct roc_nix *roc_nix); + uint8_t __roc_api roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag lvl_flag); diff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c index 06394bda07..41d31bc6cd 100644 --- a/drivers/common/cnxk/roc_nix_bpf.c +++ b/drivers/common/cnxk/roc_nix_bpf.c @@ -170,3 +170,43 @@ roc_nix_bpf_alloc(struct roc_nix *roc_nix, uint8_t lvl_mask, exit: return rc; } + +int +roc_nix_bpf_free(struct roc_nix *roc_nix, struct roc_nix_bpf_objs *profs, + uint8_t num_prof) +{ + struct mbox *mbox = get_mbox(roc_nix); + struct nix_bandprof_free_req *req; + uint8_t level; + int i, j; + + if (num_prof >= NIX_RX_BAND_PROF_LAYER_MAX) + return NIX_ERR_INVALID_RANGE; + + req = mbox_alloc_msg_nix_bandprof_free(mbox); + if (req == NULL) + return -ENOSPC; + + for (i = 0; i < num_prof; i++) { + level = sw_to_hw_lvl_map[profs[i].level]; + req->prof_count[level] = profs[i].count; + for (j = 0; j < profs[i].count; j++) + req->prof_idx[level][j] = profs[i].ids[j]; + } + + return mbox_process(mbox); +} + +int +roc_nix_bpf_free_all(struct roc_nix *roc_nix) +{ + struct mbox *mbox = get_mbox(roc_nix); + struct nix_bandprof_free_req *req; + + req = mbox_alloc_msg_nix_bandprof_free(mbox); + if (req == NULL) + return -ENOSPC; + + req->free_all = true; + return mbox_process(mbox); +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 81e76919b5..c45d524d65 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -79,6 +79,8 @@ INTERNAL { roc_se_ciph_key_set; roc_nix_bpf_alloc; roc_nix_bpf_count_get; + roc_nix_bpf_free; + roc_nix_bpf_free_all; roc_nix_bpf_level_to_idx; roc_nix_cq_dump; roc_nix_cq_fini; From patchwork Thu Sep 30 09:08:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100067 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0494BA0C41; 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Thu, 30 Sep 2021 02:09:06 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:09:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:02 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 4BDB43F7067; Thu, 30 Sep 2021 02:09:00 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Thu, 30 Sep 2021 14:38:23 +0530 Message-ID: <20210930090844.1059326-6-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: hxx6bjaynqsm5SkfjNV9LiW1nqX1I5K9 X-Proofpoint-ORIG-GUID: hxx6bjaynqsm5SkfjNV9LiW1nqX1I5K9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 06/27] common/cnxk: support RoC API to configure bandwidth profile X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement RoC API to configure HW bandwidth profile for CN10K platform. Signed-off-by: Sunil Kumar Kori --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/common/cnxk/hw/nix.h | 49 +++++++ drivers/common/cnxk/roc_nix.h | 60 ++++++++ drivers/common/cnxk/roc_nix_bpf.c | 233 ++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 4 files changed, 343 insertions(+) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index 53cdfbb142..2c1487a105 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -2112,6 +2112,55 @@ struct nix_lso_format { #define NIX_RPM_MAX_HW_FRS 16380UL #define NIX_MIN_HW_FRS 60UL +/** NIX policer rate limits */ +#define NIX_BPF_MAX_RATE_DIV_EXP 12 +#define NIX_BPF_MAX_RATE_EXPONENT 0xf +#define NIX_BPF_MAX_RATE_MANTISSA 0xff + +#define NIX_BPF_RATE_CONST 2000000ULL + +/* NIX rate calculation in Bits/Sec + * PIR_ADD = ((256 + NIX_*_PIR[RATE_MANTISSA]) + * << NIX_*_PIR[RATE_EXPONENT]) / 256 + * PIR = (2E6 * PIR_ADD / (1 << NIX_*_PIR[RATE_DIVIDER_EXPONENT])) + * + * CIR_ADD = ((256 + NIX_*_CIR[RATE_MANTISSA]) + * << NIX_*_CIR[RATE_EXPONENT]) / 256 + * CIR = (2E6 * CIR_ADD / (CCLK_TICKS << NIX_*_CIR[RATE_DIVIDER_EXPONENT])) + */ +#define NIX_BPF_RATE(exponent, mantissa, div_exp) \ + ((NIX_BPF_RATE_CONST * ((256 + (mantissa)) << (exponent))) / \ + (((1ull << (div_exp)) * 256))) + +/* Meter rate limits in Bits/Sec */ +#define NIX_BPF_RATE_MIN NIX_BPF_RATE(0, 0, NIX_BPF_MAX_RATE_DIV_EXP) +#define NIX_BPF_RATE_MAX \ + NIX_BPF_RATE(NIX_BPF_MAX_RATE_EXPONENT, NIX_BPF_MAX_RATE_MANTISSA, 0) + +#define NIX_BPF_DEFAULT_ADJUST_MANTISSA 511 +#define NIX_BPF_DEFAULT_ADJUST_EXPONENT 0 + +/** NIX burst limits */ +#define NIX_BPF_MAX_BURST_EXPONENT 0xf +#define NIX_BPF_MAX_BURST_MANTISSA 0xff + +/* NIX burst calculation + * PIR_BURST = ((256 + NIX_*_PIR[BURST_MANTISSA]) + * << (NIX_*_PIR[BURST_EXPONENT] + 1)) + * / 256 + * + * CIR_BURST = ((256 + NIX_*_CIR[BURST_MANTISSA]) + * << (NIX_*_CIR[BURST_EXPONENT] + 1)) + * / 256 + */ +#define NIX_BPF_BURST(exponent, mantissa) \ + (((256 + (mantissa)) << ((exponent) + 1)) / 256) + +/** Meter burst limits */ +#define NIX_BPF_BURST_MIN NIX_BPF_BURST(0, 0) +#define NIX_BPF_BURST_MAX \ + NIX_BPF_BURST(NIX_BPF_MAX_BURST_EXPONENT, NIX_BPF_MAX_BURST_MANTISSA) + /* NIX rate limits */ #define NIX_TM_MAX_RATE_DIV_EXP 12 #define NIX_TM_MAX_RATE_EXPONENT 0xf diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index bf451ecdbc..42af66ccde 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -39,6 +39,62 @@ enum roc_nix_bpf_level_flag { ROC_NIX_BPF_LEVEL_F_TOP = BIT(2), }; +enum roc_nix_bpf_color { + ROC_NIX_BPF_COLOR_GREEN, + ROC_NIX_BPF_COLOR_YELLOW, + ROC_NIX_BPF_COLOR_RED, + ROC_NIX_BPF_COLOR_MAX +}; + +enum roc_nix_bpf_algo { + ROC_NIX_BPF_ALGO_NONE, + ROC_NIX_BPF_ALGO_2698, + ROC_NIX_BPF_ALGO_4115, + ROC_NIX_BPF_ALGO_2697 +}; + +enum roc_nix_bpf_lmode { ROC_NIX_BPF_LMODE_BYTE, ROC_NIX_BPF_LMODE_PACKET }; + +enum roc_nix_bpf_action { + ROC_NIX_BPF_ACTION_PASS, + ROC_NIX_BPF_ACTION_DROP, + ROC_NIX_BPF_ACTION_RED +}; + +struct roc_nix_bpf_cfg { + enum roc_nix_bpf_algo alg; + enum roc_nix_bpf_lmode lmode; + union { + /* Valid when *alg* is set to ROC_NIX_BPF_ALGO_2697. */ + struct { + uint64_t cir; + uint64_t cbs; + uint64_t ebs; + } algo2697; + + /* Valid when *alg* is set to ROC_NIX_BPF_ALGO_2698. */ + struct { + uint64_t cir; + uint64_t pir; + uint64_t cbs; + uint64_t pbs; + } algo2698; + + /* Valid when *alg* is set to ROC_NIX_BPF_ALGO_4115. */ + struct { + uint64_t cir; + uint64_t eir; + uint64_t cbs; + uint64_t ebs; + } algo4115; + }; + + enum roc_nix_bpf_action action[ROC_NIX_BPF_COLOR_MAX]; + + /* Reserved for future config*/ + uint32_t rsvd[3]; +}; + struct roc_nix_bpf_objs { uint16_t level; uint16_t count; @@ -499,6 +555,10 @@ int __roc_api roc_nix_bpf_free(struct roc_nix *roc_nix, int __roc_api roc_nix_bpf_free_all(struct roc_nix *roc_nix); +int __roc_api roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id, + enum roc_nix_bpf_level_flag lvl_flag, + struct roc_nix_bpf_cfg *cfg); + uint8_t __roc_api roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag lvl_flag); diff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c index 41d31bc6cd..37631c134c 100644 --- a/drivers/common/cnxk/roc_nix_bpf.c +++ b/drivers/common/cnxk/roc_nix_bpf.c @@ -26,6 +26,105 @@ get_mbox(struct roc_nix *roc_nix) return dev->mbox; } +static inline uint64_t +meter_rate_to_nix(uint64_t value, uint64_t *exponent_p, uint64_t *mantissa_p, + uint64_t *div_exp_p) +{ + uint64_t div_exp, exponent, mantissa; + + /* Boundary checks */ + if (value < NIX_BPF_RATE_MIN || value > NIX_BPF_RATE_MAX) + return 0; + + if (value <= NIX_BPF_RATE(0, 0, 0)) { + /* Calculate rate div_exp and mantissa using + * the following formula: + * + * value = (2E6 * (256 + mantissa) + * / ((1 << div_exp) * 256)) + */ + div_exp = 0; + exponent = 0; + mantissa = NIX_BPF_MAX_RATE_MANTISSA; + + while (value < (NIX_BPF_RATE_CONST / (1 << div_exp))) + div_exp += 1; + + while (value < ((NIX_BPF_RATE_CONST * (256 + mantissa)) / + ((1 << div_exp) * 256))) + mantissa -= 1; + } else { + /* Calculate rate exponent and mantissa using + * the following formula: + * + * value = (2E6 * ((256 + mantissa) << exponent)) / 256 + * + */ + div_exp = 0; + exponent = NIX_BPF_MAX_RATE_EXPONENT; + mantissa = NIX_BPF_MAX_RATE_MANTISSA; + + while (value < (NIX_BPF_RATE_CONST * (1 << exponent))) + exponent -= 1; + + while (value < + ((NIX_BPF_RATE_CONST * ((256 + mantissa) << exponent)) / + 256)) + mantissa -= 1; + } + + if (div_exp > NIX_BPF_MAX_RATE_DIV_EXP || + exponent > NIX_BPF_MAX_RATE_EXPONENT || + mantissa > NIX_BPF_MAX_RATE_MANTISSA) + return 0; + + if (div_exp_p) + *div_exp_p = div_exp; + if (exponent_p) + *exponent_p = exponent; + if (mantissa_p) + *mantissa_p = mantissa; + + /* Calculate real rate value */ + return NIX_BPF_RATE(exponent, mantissa, div_exp); +} + +static inline uint64_t +meter_burst_to_nix(uint64_t value, uint64_t *exponent_p, uint64_t *mantissa_p) +{ + uint64_t exponent, mantissa; + + if (value < NIX_BPF_BURST_MIN || value > NIX_BPF_BURST_MAX) + return 0; + + /* Calculate burst exponent and mantissa using + * the following formula: + * + * value = (((256 + mantissa) << (exponent + 1) + / 256) + * + */ + exponent = NIX_BPF_MAX_BURST_EXPONENT; + mantissa = NIX_BPF_MAX_BURST_MANTISSA; + + while (value < (1ull << (exponent + 1))) + exponent -= 1; + + while (value < ((256 + mantissa) << (exponent + 1)) / 256) + mantissa -= 1; + + if (exponent > NIX_BPF_MAX_BURST_EXPONENT || + mantissa > NIX_BPF_MAX_BURST_MANTISSA) + return 0; + + if (exponent_p) + *exponent_p = exponent; + if (mantissa_p) + *mantissa_p = mantissa; + + return NIX_BPF_BURST(exponent, mantissa); +} + uint8_t roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag level_f) { @@ -210,3 +309,137 @@ roc_nix_bpf_free_all(struct roc_nix *roc_nix) req->free_all = true; return mbox_process(mbox); } + +int +roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id, + enum roc_nix_bpf_level_flag lvl_flag, + struct roc_nix_bpf_cfg *cfg) +{ + uint64_t exponent_p = 0, mantissa_p = 0, div_exp_p = 0; + struct mbox *mbox = get_mbox(roc_nix); + struct nix_cn10k_aq_enq_req *aq; + uint8_t level_idx; + + if (roc_model_is_cn9k()) + return NIX_ERR_HW_NOTSUP; + + if (!cfg) + return NIX_ERR_PARAM; + + level_idx = roc_nix_bpf_level_to_idx(lvl_flag); + if (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID) + return NIX_ERR_PARAM; + + aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox); + if (aq == NULL) + return -ENOSPC; + aq->qidx = (sw_to_hw_lvl_map[level_idx] << 14) | id; + aq->ctype = NIX_AQ_CTYPE_BAND_PROF; + aq->op = NIX_AQ_INSTOP_WRITE; + + aq->prof.adjust_exponent = NIX_BPF_DEFAULT_ADJUST_EXPONENT; + aq->prof.adjust_mantissa = NIX_BPF_DEFAULT_ADJUST_MANTISSA; + if (cfg->lmode == ROC_NIX_BPF_LMODE_BYTE) + aq->prof.adjust_mantissa = NIX_BPF_DEFAULT_ADJUST_MANTISSA / 2; + + aq->prof_mask.adjust_exponent = ~(aq->prof_mask.adjust_exponent); + aq->prof_mask.adjust_mantissa = ~(aq->prof_mask.adjust_mantissa); + + switch (cfg->alg) { + case ROC_NIX_BPF_ALGO_2697: + meter_rate_to_nix(cfg->algo2697.cir, &exponent_p, &mantissa_p, + &div_exp_p); + aq->prof.cir_mantissa = mantissa_p; + aq->prof.cir_exponent = exponent_p; + + meter_burst_to_nix(cfg->algo2697.cbs, &exponent_p, &mantissa_p); + aq->prof.cbs_mantissa = mantissa_p; + aq->prof.cbs_exponent = exponent_p; + + meter_burst_to_nix(cfg->algo2697.ebs, &exponent_p, &mantissa_p); + aq->prof.pebs_mantissa = mantissa_p; + aq->prof.pebs_exponent = exponent_p; + + aq->prof_mask.cir_mantissa = ~(aq->prof_mask.cir_mantissa); + aq->prof_mask.cbs_mantissa = ~(aq->prof_mask.cbs_mantissa); + aq->prof_mask.pebs_mantissa = ~(aq->prof_mask.pebs_mantissa); + aq->prof_mask.cir_exponent = ~(aq->prof_mask.cir_exponent); + aq->prof_mask.cbs_exponent = ~(aq->prof_mask.cbs_exponent); + aq->prof_mask.pebs_exponent = ~(aq->prof_mask.pebs_exponent); + break; + + case ROC_NIX_BPF_ALGO_2698: + meter_rate_to_nix(cfg->algo2698.cir, &exponent_p, &mantissa_p, + &div_exp_p); + aq->prof.cir_mantissa = mantissa_p; + aq->prof.cir_exponent = exponent_p; + + meter_rate_to_nix(cfg->algo2698.pir, &exponent_p, &mantissa_p, + &div_exp_p); + aq->prof.peir_mantissa = mantissa_p; + aq->prof.peir_exponent = exponent_p; + + meter_burst_to_nix(cfg->algo2698.cbs, &exponent_p, &mantissa_p); + aq->prof.cbs_mantissa = mantissa_p; + aq->prof.cbs_exponent = exponent_p; + + meter_burst_to_nix(cfg->algo2698.pbs, &exponent_p, &mantissa_p); + aq->prof.pebs_mantissa = mantissa_p; + aq->prof.pebs_exponent = exponent_p; + + aq->prof_mask.cir_mantissa = ~(aq->prof_mask.cir_mantissa); + aq->prof_mask.peir_mantissa = ~(aq->prof_mask.peir_mantissa); + aq->prof_mask.cbs_mantissa = ~(aq->prof_mask.cbs_mantissa); + aq->prof_mask.pebs_mantissa = ~(aq->prof_mask.pebs_mantissa); + aq->prof_mask.cir_exponent = ~(aq->prof_mask.cir_exponent); + aq->prof_mask.peir_exponent = ~(aq->prof_mask.peir_exponent); + aq->prof_mask.cbs_exponent = ~(aq->prof_mask.cbs_exponent); + aq->prof_mask.pebs_exponent = ~(aq->prof_mask.pebs_exponent); + break; + + case ROC_NIX_BPF_ALGO_4115: + meter_rate_to_nix(cfg->algo4115.cir, &exponent_p, &mantissa_p, + &div_exp_p); + aq->prof.cir_mantissa = mantissa_p; + aq->prof.cir_exponent = exponent_p; + + meter_rate_to_nix(cfg->algo4115.eir, &exponent_p, &mantissa_p, + &div_exp_p); + aq->prof.peir_mantissa = mantissa_p; + aq->prof.peir_exponent = exponent_p; + + meter_burst_to_nix(cfg->algo4115.cbs, &exponent_p, &mantissa_p); + aq->prof.cbs_mantissa = mantissa_p; + aq->prof.cbs_exponent = exponent_p; + + meter_burst_to_nix(cfg->algo4115.ebs, &exponent_p, &mantissa_p); + aq->prof.pebs_mantissa = mantissa_p; + aq->prof.pebs_exponent = exponent_p; + + aq->prof_mask.cir_mantissa = ~(aq->prof_mask.cir_mantissa); + aq->prof_mask.peir_mantissa = ~(aq->prof_mask.peir_mantissa); + aq->prof_mask.cbs_mantissa = ~(aq->prof_mask.cbs_mantissa); + aq->prof_mask.pebs_mantissa = ~(aq->prof_mask.pebs_mantissa); + + aq->prof_mask.cir_exponent = ~(aq->prof_mask.cir_exponent); + aq->prof_mask.peir_exponent = ~(aq->prof_mask.peir_exponent); + aq->prof_mask.cbs_exponent = ~(aq->prof_mask.cbs_exponent); + aq->prof_mask.pebs_exponent = ~(aq->prof_mask.pebs_exponent); + break; + + default: + return NIX_ERR_PARAM; + } + + aq->prof.lmode = cfg->lmode; + aq->prof.gc_action = cfg->action[ROC_NIX_BPF_COLOR_GREEN]; + aq->prof.yc_action = cfg->action[ROC_NIX_BPF_COLOR_YELLOW]; + aq->prof.rc_action = cfg->action[ROC_NIX_BPF_COLOR_RED]; + + aq->prof_mask.lmode = ~(aq->prof_mask.lmode); + aq->prof_mask.gc_action = ~(aq->prof_mask.gc_action); + aq->prof_mask.yc_action = ~(aq->prof_mask.yc_action); + aq->prof_mask.rc_action = ~(aq->prof_mask.rc_action); + + return mbox_process(mbox); +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index c45d524d65..6a009eaf35 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -78,6 +78,7 @@ INTERNAL { roc_se_auth_key_set; roc_se_ciph_key_set; roc_nix_bpf_alloc; + roc_nix_bpf_config; roc_nix_bpf_count_get; roc_nix_bpf_free; roc_nix_bpf_free_all; From patchwork Thu Sep 30 09:08:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100068 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4EDC9A0C41; Thu, 30 Sep 2021 11:09:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D115F4112E; Thu, 30 Sep 2021 11:09:13 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 8D55A410E5 for ; Thu, 30 Sep 2021 11:09:10 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18U1KYKR001412; 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Thu, 30 Sep 2021 02:09:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:04 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id AD60B3F7068; Thu, 30 Sep 2021 02:09:02 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Thu, 30 Sep 2021 14:38:24 +0530 Message-ID: <20210930090844.1059326-7-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 3rruxf-wU1XuI7r9cgoRC1k11t6BapAD X-Proofpoint-ORIG-GUID: 3rruxf-wU1XuI7r9cgoRC1k11t6BapAD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 07/27] common/cnxk: support RoC API to toggle profile state X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement RoC API to enable or disable HW bandwidth profiles on CN10K platform. Signed-off-by: Sunil Kumar Kori --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/common/cnxk/roc_nix.h | 4 ++++ drivers/common/cnxk/roc_nix_bpf.c | 39 +++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 44 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 42af66ccde..2576e938be 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -214,6 +214,7 @@ struct roc_nix_stats_queue { struct roc_nix_rq { /* Input parameters */ uint16_t qid; + uint16_t bpf_id; uint64_t aura_handle; bool ipsech_ena; uint16_t first_skip; @@ -559,6 +560,9 @@ int __roc_api roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id, enum roc_nix_bpf_level_flag lvl_flag, struct roc_nix_bpf_cfg *cfg); +int __roc_api roc_nix_bpf_ena_dis(struct roc_nix *roc_nix, uint16_t id, + struct roc_nix_rq *rq, bool enable); + uint8_t __roc_api roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag lvl_flag); diff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c index 37631c134c..557b6279e6 100644 --- a/drivers/common/cnxk/roc_nix_bpf.c +++ b/drivers/common/cnxk/roc_nix_bpf.c @@ -443,3 +443,42 @@ roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id, return mbox_process(mbox); } + +int +roc_nix_bpf_ena_dis(struct roc_nix *roc_nix, uint16_t id, struct roc_nix_rq *rq, + bool enable) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct mbox *mbox = get_mbox(roc_nix); + struct nix_cn10k_aq_enq_req *aq; + int rc; + + if (roc_model_is_cn9k()) + return NIX_ERR_HW_NOTSUP; + + if (rq->qid >= nix->nb_rx_queues) + return NIX_ERR_QUEUE_INVALID_RANGE; + + aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox); + if (aq == NULL) + return -ENOSPC; + aq->qidx = rq->qid; + aq->ctype = NIX_AQ_CTYPE_RQ; + aq->op = NIX_AQ_INSTOP_WRITE; + + aq->rq.policer_ena = enable; + aq->rq_mask.policer_ena = ~(aq->rq_mask.policer_ena); + if (enable) { + aq->rq.band_prof_id = id; + aq->rq_mask.band_prof_id = ~(aq->rq_mask.band_prof_id); + } + + rc = mbox_process(mbox); + if (rc) + goto exit; + + rq->bpf_id = id; + +exit: + return rc; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 6a009eaf35..4c5adb8212 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -80,6 +80,7 @@ INTERNAL { roc_nix_bpf_alloc; roc_nix_bpf_config; roc_nix_bpf_count_get; + roc_nix_bpf_ena_dis; roc_nix_bpf_free; roc_nix_bpf_free_all; roc_nix_bpf_level_to_idx; From patchwork Thu Sep 30 09:08:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100069 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E6461A0C41; Thu, 30 Sep 2021 11:09:42 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D42F641137; Thu, 30 Sep 2021 11:09:14 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id F0201410FF for ; Thu, 30 Sep 2021 11:09:10 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18U1KYVS001409; Thu, 30 Sep 2021 02:09:08 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ZisCDuJgoLEYWAiKKNbXLhni+OLmJLctRfYo6z4sw5M=; b=WoI1RxhGX16p8QyxYErGEZ1SikWI7iIbxQusSFSgsusf34Qg/hXmNcnSO6PR1BIB/OU9 81kBJQIvqQJRGpGaJUhp79l79S4V/6+iSV94qtmIDeqyZfMLITaqjKaIU9vRPKizgYL/ knDpgoY9u6ftcErK/9FPehAmytv1/5uXQC9mjI16Wd+iqCmjrHjtq6T1AhDp1e9eBFDQ 72Bx5hiCFRQyIWDJvVECFy0L6AXkxbohykubcuHmGs8zNp8pmO65zd7hbilp3b13g1j9 umjpD6jlzR1B18QJ2r1sbu5BSmCSpwqfHSb+4WfRDo8HCsokfOhoWY4Mi354CzJNV/zN 5g== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3bd3g39kcw-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 30 Sep 2021 02:09:08 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:09:06 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:06 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 1F22A3F7067; Thu, 30 Sep 2021 02:09:04 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Thu, 30 Sep 2021 14:38:25 +0530 Message-ID: <20210930090844.1059326-8-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 8AnZtYvW8jzsglcgTFvwe2x1Hrj2wSyl X-Proofpoint-ORIG-GUID: 8AnZtYvW8jzsglcgTFvwe2x1Hrj2wSyl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 08/27] common/cnxk: support RoC API to dump bandwidth profile X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement RoC API to dump bandwidth profile on CN10K platform. Signed-off-by: Sunil Kumar Kori --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/common/cnxk/roc_nix.h | 3 ++ drivers/common/cnxk/roc_nix_bpf.c | 86 ++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_platform.h | 1 + drivers/common/cnxk/version.map | 1 + 4 files changed, 91 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 2576e938be..15df1e593f 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -563,6 +563,9 @@ int __roc_api roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id, int __roc_api roc_nix_bpf_ena_dis(struct roc_nix *roc_nix, uint16_t id, struct roc_nix_rq *rq, bool enable); +int __roc_api roc_nix_bpf_dump(struct roc_nix *roc_nix, uint16_t id, + enum roc_nix_bpf_level_flag lvl_flag); + uint8_t __roc_api roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag lvl_flag); diff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c index 557b6279e6..970c960186 100644 --- a/drivers/common/cnxk/roc_nix_bpf.c +++ b/drivers/common/cnxk/roc_nix_bpf.c @@ -125,6 +125,60 @@ meter_burst_to_nix(uint64_t value, uint64_t *exponent_p, uint64_t *mantissa_p) return NIX_BPF_BURST(exponent, mantissa); } +static inline void +nix_lf_bpf_dump(__io struct nix_band_prof_s *bpf) +{ + plt_dump("W0: cir_mantissa \t\t\t%d\nW0: pebs_mantissa \t\t\t0x%03x", + bpf->cir_mantissa, bpf->pebs_mantissa); + plt_dump("W0: peir_matissa \t\t\t\t%d\nW0: cbs_exponent \t\t\t%d", + bpf->peir_mantissa, bpf->cbs_exponent); + plt_dump("W0: cir_exponent \t\t\t%d\nW0: pebs_exponent \t\t\t%d", + bpf->cir_exponent, bpf->pebs_exponent); + plt_dump("W0: peir_exponent \t\t\t%d\n", bpf->peir_exponent); + plt_dump("W0: tnl_ena \t\t\t%d\n", bpf->tnl_ena); + plt_dump("W0: icolor \t\t\t%d\n", bpf->icolor); + plt_dump("W0: pc_mode \t\t\t%d\n", bpf->pc_mode); + plt_dump("W1: hl_en \t\t%d\nW1: band_prof_id \t\t%d", bpf->hl_en, + bpf->band_prof_id); + plt_dump("W1: meter_algo \t\t%d\nW1: rc_action \t\t%d", bpf->meter_algo, + bpf->rc_action); + plt_dump("W1: yc_action \t\t\t%d\nW1: gc_action \t\t\t%d", + bpf->yc_action, bpf->gc_action); + plt_dump("W1: adjust_mantissa\t\t\t%d\nW1: adjust_exponent \t\t\t%d", + bpf->adjust_mantissa, bpf->adjust_exponent); + plt_dump("W1: rdiv \t\t\t%d\n", bpf->rdiv); + plt_dump("W1: l_select \t\t%d\nW2: lmode \t\t%d", bpf->l_sellect, + bpf->lmode); + plt_dump("W1: cbs_mantissa \t\t\t%d\n", bpf->cbs_mantissa); + plt_dump("W2: tsa \t\t\t0x%" PRIx64 "\n", (uint64_t)bpf->ts); + plt_dump("W3: c_accum \t\t%d\nW3: pe_accum \t\t%d", bpf->c_accum, + bpf->pe_accum); + plt_dump("W4: green_pkt_pass \t\t\t0x%" PRIx64 "", + (uint64_t)bpf->green_pkt_pass); + plt_dump("W5: yellow_pkt_pass \t\t\t0x%" PRIx64 "", + (uint64_t)bpf->yellow_pkt_pass); + plt_dump("W6: red_pkt_pass \t\t\t0x%" PRIx64 "", + (uint64_t)bpf->red_pkt_pass); + plt_dump("W7: green_octs_pass \t\t\t0x%" PRIx64 "", + (uint64_t)bpf->green_octs_pass); + plt_dump("W8: yellow_octs_pass \t\t\t0x%" PRIx64 "", + (uint64_t)bpf->yellow_octs_pass); + plt_dump("W9: red_octs_pass \t\t\t0x%" PRIx64 "", + (uint64_t)bpf->red_octs_pass); + plt_dump("W10: green_pkt_drop \t\t\t0x%" PRIx64 "", + (uint64_t)bpf->green_pkt_drop); + plt_dump("W11: yellow_pkt_drop \t\t\t0x%" PRIx64 "", + (uint64_t)bpf->yellow_pkt_drop); + plt_dump("W12: red_pkt_drop \t\t\t0x%" PRIx64 "", + (uint64_t)bpf->red_pkt_drop); + plt_dump("W13: green_octs_drop \t\t\t0x%" PRIx64 "", + (uint64_t)bpf->green_octs_drop); + plt_dump("W14: yellow_octs_drop \t\t\t0x%" PRIx64 "", + (uint64_t)bpf->yellow_octs_drop); + plt_dump("W15: red_octs_drop \t\t\t0x%" PRIx64 "", + (uint64_t)bpf->red_octs_drop); +} + uint8_t roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag level_f) { @@ -482,3 +536,35 @@ roc_nix_bpf_ena_dis(struct roc_nix *roc_nix, uint16_t id, struct roc_nix_rq *rq, exit: return rc; } + +int +roc_nix_bpf_dump(struct roc_nix *roc_nix, uint16_t id, + enum roc_nix_bpf_level_flag lvl_flag) +{ + struct mbox *mbox = get_mbox(roc_nix); + struct nix_cn10k_aq_enq_rsp *rsp; + struct nix_cn10k_aq_enq_req *aq; + uint8_t level_idx; + int rc; + + if (roc_model_is_cn9k()) + return NIX_ERR_HW_NOTSUP; + + level_idx = roc_nix_bpf_level_to_idx(lvl_flag); + if (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID) + return NIX_ERR_PARAM; + + aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox); + if (aq == NULL) + return -ENOSPC; + aq->qidx = (sw_to_hw_lvl_map[level_idx] << 14 | id); + aq->ctype = NIX_AQ_CTYPE_BAND_PROF; + aq->op = NIX_AQ_INSTOP_READ; + rc = mbox_process_msg(mbox, (void *)&rsp); + if (!rc) { + plt_dump("============= band prof id =%d ===============", id); + nix_lf_bpf_dump(&rsp->prof); + } + + return rc; +} diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index 285b24b82d..69b7c49d8b 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -155,6 +155,7 @@ extern int cnxk_logtype_tm; #define plt_info(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) #define plt_warn(fmt, args...) RTE_LOG(WARNING, PMD, fmt "\n", ##args) #define plt_print(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args) +#define plt_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__) /** * Log debug message if given subsystem logging is enabled. diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 4c5adb8212..97386ef273 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -80,6 +80,7 @@ INTERNAL { roc_nix_bpf_alloc; roc_nix_bpf_config; roc_nix_bpf_count_get; + roc_nix_bpf_dump; roc_nix_bpf_ena_dis; roc_nix_bpf_free; roc_nix_bpf_free_all; From patchwork Thu Sep 30 09:08:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100070 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A085AA0C41; Thu, 30 Sep 2021 11:09:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5424C41141; Thu, 30 Sep 2021 11:09:18 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A90864111F for ; Thu, 30 Sep 2021 11:09:13 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18U1KGNl000861; Thu, 30 Sep 2021 02:09:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=9sBqDUDAvK+iBAhdUdi4iThxrwkLSnsNqJiaXfuGf7A=; b=D2gZSfcQ9KhTRkf8gCh0hsKtCy8Q2fvqyqamGclO7Pd8eDpMHh3MwWUX1IeaxHRmHr4m 4H78J8XAY8uhzSaNh3rqIPfT13ISQRLFpE/wGbS8QWOwp9oU1EZJeSnUSNw2K1NnFF/X tjccnIZwFEQrm8LTXnJOrpXhMVWAxhbRRXjXlgUHp0oisvXpVEzD6fxX5IEcDHQ0DgyH k2sp60H/QASD6PPpV+JzT8/ZEtjbGP1cwl95+QU9xdIjASjBP+/3eYR3yMVRmNYO2hJQ rTvjjesM7akIloEAWeZVO/ic2+9F0F7XsfgSI1Sp3Wd6gNLQqkZ3C1xPCjw6L2aOA84r RQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3bd3g39kd3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 30 Sep 2021 02:09:11 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:09:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:09 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 8093B3F7068; Thu, 30 Sep 2021 02:09:07 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Thu, 30 Sep 2021 14:38:26 +0530 Message-ID: <20210930090844.1059326-9-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: NzB0TDGRlCV1LQ8BIHRtUbp7JBGs2TZL X-Proofpoint-ORIG-GUID: NzB0TDGRlCV1LQ8BIHRtUbp7JBGs2TZL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 09/27] common/cnxk: support RoC API to setup precolor table X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori For initial coloring of input packet, CN10K platform maintains precolor table for VLAN, DSCP and Generic. Implement RoC interface to setup pre color table. Signed-off-by: Sunil Kumar Kori --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/common/cnxk/roc_nix.h | 20 ++++ drivers/common/cnxk/roc_nix_bpf.c | 193 ++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 214 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 15df1e593f..6d17d46388 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -39,6 +39,15 @@ enum roc_nix_bpf_level_flag { ROC_NIX_BPF_LEVEL_F_TOP = BIT(2), }; +enum roc_nix_bpf_pc_mode { + ROC_NIX_BPF_PC_MODE_VLAN_INNER, + ROC_NIX_BPF_PC_MODE_VLAN_OUTER, + ROC_NIX_BPF_PC_MODE_DSCP_INNER, + ROC_NIX_BPF_PC_MODE_DSCP_OUTER, + ROC_NIX_BPF_PC_MODE_GEN_INNER, + ROC_NIX_BPF_PC_MODE_GEN_OUTER +}; + enum roc_nix_bpf_color { ROC_NIX_BPF_COLOR_GREEN, ROC_NIX_BPF_COLOR_YELLOW, @@ -101,6 +110,13 @@ struct roc_nix_bpf_objs { uint16_t ids[ROC_NIX_BPF_PER_PFFUNC]; }; +struct roc_nix_bpf_precolor { +#define ROC_NIX_BPF_PRE_COLOR_MAX 64 + uint8_t count; + enum roc_nix_bpf_pc_mode mode; + enum roc_nix_bpf_color color[ROC_NIX_BPF_PRE_COLOR_MAX]; +}; + struct roc_nix_vlan_config { uint32_t type; union { @@ -566,6 +582,10 @@ int __roc_api roc_nix_bpf_ena_dis(struct roc_nix *roc_nix, uint16_t id, int __roc_api roc_nix_bpf_dump(struct roc_nix *roc_nix, uint16_t id, enum roc_nix_bpf_level_flag lvl_flag); +int __roc_api roc_nix_bpf_pre_color_tbl_setup( + struct roc_nix *roc_nix, uint16_t id, + enum roc_nix_bpf_level_flag lvl_flag, struct roc_nix_bpf_precolor *tbl); + uint8_t __roc_api roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag lvl_flag); diff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c index 970c960186..b5a1c484a9 100644 --- a/drivers/common/cnxk/roc_nix_bpf.c +++ b/drivers/common/cnxk/roc_nix_bpf.c @@ -9,6 +9,10 @@ #define NIX_MAX_BPF_COUNT_MID_LAYER 8 #define NIX_MAX_BPF_COUNT_TOP_LAYER 1 +#define NIX_BPF_PRECOLOR_GEN_TABLE_SIZE 16 +#define NIX_BPF_PRECOLOR_VLAN_TABLE_SIZE 16 +#define NIX_BPF_PRECOLOR_DSCP_TABLE_SIZE 64 + #define NIX_BPF_LEVEL_F_MASK \ (ROC_NIX_BPF_LEVEL_F_LEAF | ROC_NIX_BPF_LEVEL_F_MID | \ ROC_NIX_BPF_LEVEL_F_TOP) @@ -179,6 +183,107 @@ nix_lf_bpf_dump(__io struct nix_band_prof_s *bpf) (uint64_t)bpf->red_octs_drop); } +static inline void +nix_precolor_conv_table_write(struct roc_nix *roc_nix, uint64_t val, + uint32_t off) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + int64_t *addr; + + addr = PLT_PTR_ADD(nix->base, off); + /* FIXME: Currently writing to this register throwing kernel dump. + * plt_write64(val, addr); + */ + PLT_SET_USED(val); + PLT_SET_USED(addr); +} + +static uint8_t +nix_precolor_vlan_table_update(struct roc_nix *roc_nix, + struct roc_nix_bpf_precolor *tbl) +{ + uint64_t val = 0, i; + uint8_t tn_ena; + uint32_t off; + + for (i = 0; i < tbl->count; i++) + val |= (((uint64_t)tbl->color[i]) << (2 * i)); + + if (tbl->mode == ROC_NIX_BPF_PC_MODE_VLAN_INNER) { + off = NIX_LF_RX_VLAN1_COLOR_CONV; + tn_ena = true; + } else { + off = NIX_LF_RX_VLAN0_COLOR_CONV; + tn_ena = false; + } + + nix_precolor_conv_table_write(roc_nix, val, off); + return tn_ena; +} + +static uint8_t +nix_precolor_inner_dscp_table_update(struct roc_nix *roc_nix, + struct roc_nix_bpf_precolor *tbl) +{ + uint64_t val_lo = 0, val_hi = 0, i, j; + + for (i = 0, j = 0; i < (tbl->count / 2); i++, j++) + val_lo |= (((uint64_t)tbl->color[i]) << (2 * j)); + + for (j = 0; i < tbl->count; i++, j++) + val_hi |= (((uint64_t)tbl->color[i]) << (2 * j)); + + nix_precolor_conv_table_write(roc_nix, val_lo, + NIX_LF_RX_IIP_COLOR_CONV_LO); + nix_precolor_conv_table_write(roc_nix, val_hi, + NIX_LF_RX_IIP_COLOR_CONV_HI); + + return true; +} + +static uint8_t +nix_precolor_outer_dscp_table_update(struct roc_nix *roc_nix, + struct roc_nix_bpf_precolor *tbl) +{ + uint64_t val_lo = 0, val_hi = 0, i, j; + + for (i = 0, j = 0; i < (tbl->count / 2); i++, j++) + val_lo |= (((uint64_t)tbl->color[i]) << (2 * j)); + + for (j = 0; i < tbl->count; i++, j++) + val_hi |= (((uint64_t)tbl->color[i]) << (2 * j)); + + nix_precolor_conv_table_write(roc_nix, val_lo, + NIX_LF_RX_OIP_COLOR_CONV_LO); + nix_precolor_conv_table_write(roc_nix, val_hi, + NIX_LF_RX_OIP_COLOR_CONV_HI); + + return false; +} + +static uint8_t +nix_precolor_gen_table_update(struct roc_nix *roc_nix, + struct roc_nix_bpf_precolor *tbl) +{ + uint64_t val = 0, i; + uint8_t tn_ena; + uint32_t off; + + for (i = 0; i < tbl->count; i++) + val |= (((uint64_t)tbl->color[i]) << (2 * i)); + + if (tbl->mode == ROC_NIX_BPF_PC_MODE_GEN_INNER) { + off = NIX_LF_RX_GEN_COLOR_CONVX(1); + tn_ena = true; + } else { + off = NIX_LF_RX_GEN_COLOR_CONVX(0); + tn_ena = false; + } + + nix_precolor_conv_table_write(roc_nix, val, off); + return tn_ena; +} + uint8_t roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag level_f) { @@ -568,3 +673,91 @@ roc_nix_bpf_dump(struct roc_nix *roc_nix, uint16_t id, return rc; } + +int +roc_nix_bpf_pre_color_tbl_setup(struct roc_nix *roc_nix, uint16_t id, + enum roc_nix_bpf_level_flag lvl_flag, + struct roc_nix_bpf_precolor *tbl) +{ + struct mbox *mbox = get_mbox(roc_nix); + struct nix_cn10k_aq_enq_req *aq; + uint8_t pc_mode, tn_ena; + uint8_t level_idx; + int rc; + + if (!tbl || !tbl->count) + return NIX_ERR_PARAM; + + if (roc_model_is_cn9k()) + return NIX_ERR_HW_NOTSUP; + + level_idx = roc_nix_bpf_level_to_idx(lvl_flag); + if (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID) + return NIX_ERR_PARAM; + + switch (tbl->mode) { + case ROC_NIX_BPF_PC_MODE_VLAN_INNER: + case ROC_NIX_BPF_PC_MODE_VLAN_OUTER: + if (tbl->count != NIX_BPF_PRECOLOR_VLAN_TABLE_SIZE) { + plt_err("Table size must be %d", + NIX_BPF_PRECOLOR_VLAN_TABLE_SIZE); + rc = NIX_ERR_PARAM; + goto exit; + } + tn_ena = nix_precolor_vlan_table_update(roc_nix, tbl); + pc_mode = NIX_RX_BAND_PROF_PC_MODE_VLAN; + break; + case ROC_NIX_BPF_PC_MODE_DSCP_INNER: + if (tbl->count != NIX_BPF_PRECOLOR_DSCP_TABLE_SIZE) { + plt_err("Table size must be %d", + NIX_BPF_PRECOLOR_DSCP_TABLE_SIZE); + rc = NIX_ERR_PARAM; + goto exit; + } + tn_ena = nix_precolor_inner_dscp_table_update(roc_nix, tbl); + pc_mode = NIX_RX_BAND_PROF_PC_MODE_DSCP; + break; + case ROC_NIX_BPF_PC_MODE_DSCP_OUTER: + if (tbl->count != NIX_BPF_PRECOLOR_DSCP_TABLE_SIZE) { + plt_err("Table size must be %d", + NIX_BPF_PRECOLOR_DSCP_TABLE_SIZE); + rc = NIX_ERR_PARAM; + goto exit; + } + tn_ena = nix_precolor_outer_dscp_table_update(roc_nix, tbl); + pc_mode = NIX_RX_BAND_PROF_PC_MODE_DSCP; + break; + case ROC_NIX_BPF_PC_MODE_GEN_INNER: + case ROC_NIX_BPF_PC_MODE_GEN_OUTER: + if (tbl->count != NIX_BPF_PRECOLOR_GEN_TABLE_SIZE) { + plt_err("Table size must be %d", + NIX_BPF_PRECOLOR_GEN_TABLE_SIZE); + rc = NIX_ERR_PARAM; + goto exit; + } + + tn_ena = nix_precolor_gen_table_update(roc_nix, tbl); + pc_mode = NIX_RX_BAND_PROF_PC_MODE_GEN; + break; + default: + rc = NIX_ERR_PARAM; + goto exit; + } + + /* Update corresponding bandwidth profile too */ + aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox); + if (aq == NULL) + return -ENOSPC; + aq->qidx = (sw_to_hw_lvl_map[level_idx] << 14) | id; + aq->ctype = NIX_AQ_CTYPE_BAND_PROF; + aq->op = NIX_AQ_INSTOP_WRITE; + aq->prof.pc_mode = pc_mode; + aq->prof.tnl_ena = tn_ena; + aq->prof_mask.pc_mode = ~(aq->prof_mask.pc_mode); + aq->prof_mask.tnl_ena = ~(aq->prof_mask.tnl_ena); + + return mbox_process(mbox); + +exit: + return rc; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 97386ef273..a08fbe6013 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -85,6 +85,7 @@ INTERNAL { roc_nix_bpf_free; roc_nix_bpf_free_all; roc_nix_bpf_level_to_idx; + roc_nix_bpf_pre_color_tbl_setup; roc_nix_cq_dump; roc_nix_cq_fini; roc_nix_cq_init; From patchwork Thu Sep 30 09:08:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100071 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1F9B9A0C41; Thu, 30 Sep 2021 11:09:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5D318410EB; Thu, 30 Sep 2021 11:09:19 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id D83764113D for ; Thu, 30 Sep 2021 11:09:15 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18U1KS9P001373; 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Thu, 30 Sep 2021 02:09:11 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:11 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id E58ED3F7067; Thu, 30 Sep 2021 02:09:09 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Thu, 30 Sep 2021 14:38:27 +0530 Message-ID: <20210930090844.1059326-10-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 8mYEF2CbyCg_HuPmI73bhtbMIqEWOKqx X-Proofpoint-ORIG-GUID: 8mYEF2CbyCg_HuPmI73bhtbMIqEWOKqx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 10/27] common/cnxk: support RoC API to connect bandwidth profiles X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori To maintain chain of bandwidth profiles, they needs to be connected. Implement RoC API to connect two bandwidth profiles at different levels. Signed-off-by: Sunil Kumar Kori --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/common/cnxk/roc_nix.h | 6 ++++++ drivers/common/cnxk/roc_nix_bpf.c | 36 +++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 43 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 6d17d46388..af76068030 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -7,6 +7,7 @@ /* Constants */ #define ROC_NIX_BPF_PER_PFFUNC 64 +#define ROC_NIX_BPF_ID_INVALID 0xFFFF #define ROC_NIX_BPF_LEVEL_IDX_INVALID 0xFF #define ROC_NIX_BPF_LEVEL_MAX 3 @@ -586,6 +587,11 @@ int __roc_api roc_nix_bpf_pre_color_tbl_setup( struct roc_nix *roc_nix, uint16_t id, enum roc_nix_bpf_level_flag lvl_flag, struct roc_nix_bpf_precolor *tbl); +/* Use ROC_NIX_BPF_ID_INVALID as dst_id to disconnect */ +int __roc_api roc_nix_bpf_connect(struct roc_nix *roc_nix, + enum roc_nix_bpf_level_flag lvl_flag, + uint16_t src_id, uint16_t dst_id); + uint8_t __roc_api roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag lvl_flag); diff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c index b5a1c484a9..f5822136d1 100644 --- a/drivers/common/cnxk/roc_nix_bpf.c +++ b/drivers/common/cnxk/roc_nix_bpf.c @@ -761,3 +761,39 @@ roc_nix_bpf_pre_color_tbl_setup(struct roc_nix *roc_nix, uint16_t id, exit: return rc; } + +int +roc_nix_bpf_connect(struct roc_nix *roc_nix, + enum roc_nix_bpf_level_flag lvl_flag, uint16_t src_id, + uint16_t dst_id) +{ + struct mbox *mbox = get_mbox(roc_nix); + struct nix_cn10k_aq_enq_req *aq; + uint8_t level_idx; + + if (roc_model_is_cn9k()) + return NIX_ERR_HW_NOTSUP; + + level_idx = roc_nix_bpf_level_to_idx(lvl_flag); + if (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID) + return NIX_ERR_PARAM; + + aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox); + if (aq == NULL) + return -ENOSPC; + aq->qidx = (sw_to_hw_lvl_map[level_idx] << 14) | src_id; + aq->ctype = NIX_AQ_CTYPE_BAND_PROF; + aq->op = NIX_AQ_INSTOP_WRITE; + + if (dst_id == ROC_NIX_BPF_ID_INVALID) { + aq->prof.hl_en = false; + aq->prof_mask.hl_en = ~(aq->prof_mask.hl_en); + } else { + aq->prof.hl_en = true; + aq->prof.band_prof_id = dst_id; + aq->prof_mask.hl_en = ~(aq->prof_mask.hl_en); + aq->prof_mask.band_prof_id = ~(aq->prof_mask.band_prof_id); + } + + return mbox_process(mbox); +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index a08fbe6013..c04a8ca9da 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -79,6 +79,7 @@ INTERNAL { roc_se_ciph_key_set; roc_nix_bpf_alloc; roc_nix_bpf_config; + roc_nix_bpf_connect; roc_nix_bpf_count_get; roc_nix_bpf_dump; roc_nix_bpf_ena_dis; From patchwork Thu Sep 30 09:08:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100072 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 21F54A0C41; Thu, 30 Sep 2021 11:10:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 798F34114B; Thu, 30 Sep 2021 11:09:22 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 8216F41144 for ; Thu, 30 Sep 2021 11:09:18 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18U1KcVj001444; Thu, 30 Sep 2021 02:09:16 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=FaP9AahL43Iy1t2SWA29TeRw9OLMq+743kP4KUW0A7s=; b=MotEprqep8hY9pyyRlTEWS2ifcFB1Xh33ZH3NPh+7ij/4pasgSKFm+R/25ixSFB3gCN0 HAQ+VYRIbklVzLcRjc4Bf+QWPjpR2xk4NDOcRwl8FYtTdUGfgKfNbRWIWZcfG3IL+opD 6CNkr/z5lU3n+koHz+KDxxgKBdpOGaRZ0gmHhAfqlPJ55ZwTCQ+eVfg0Xahl1gfsP2Eh /vzzURkaSUh0vA7SbRTAmMTh5SqcN3htFO8EAqb0b2c03YWzbnRgdoFKNZ4Mx6n6nmLi KXdTE0GLk9lEFLo0bKn9QrO8rGSAgTi+5EUuiit40fjT3a7w3KzWBKJQMoE3kVF/XH/W YA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3bd3g39kd9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 30 Sep 2021 02:09:16 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:09:14 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:14 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 546E83F7068; Thu, 30 Sep 2021 02:09:12 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Thu, 30 Sep 2021 14:38:28 +0530 Message-ID: <20210930090844.1059326-11-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: RxzUU8TqLXuoQ_x41Sp73ukS-WJ1ayx8 X-Proofpoint-ORIG-GUID: RxzUU8TqLXuoQ_x41Sp73ukS-WJ1ayx8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 11/27] common/cnxk: support RoC API to get stats to index X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori CN10K platform supports different stats for HW bandwidth profiles. Implement RoC API to get index for given stats type. Signed-off-by: Sunil Kumar Kori --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/common/cnxk/roc_nix.h | 18 ++++++++++++++++ drivers/common/cnxk/roc_nix_bpf.c | 34 +++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 53 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index af76068030..7bff69d39f 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -10,6 +10,7 @@ #define ROC_NIX_BPF_ID_INVALID 0xFFFF #define ROC_NIX_BPF_LEVEL_IDX_INVALID 0xFF #define ROC_NIX_BPF_LEVEL_MAX 3 +#define ROC_NIX_BPF_STATS_MAX 12 enum roc_nix_rss_reta_sz { ROC_NIX_RSS_RETA_SZ_64 = 64, @@ -71,6 +72,21 @@ enum roc_nix_bpf_action { ROC_NIX_BPF_ACTION_RED }; +enum roc_nix_bpf_stats { + ROC_NIX_BPF_GREEN_PKT_F_PASS = BIT_ULL(0), + ROC_NIX_BPF_GREEN_OCTS_F_PASS = BIT_ULL(1), + ROC_NIX_BPF_GREEN_PKT_F_DROP = BIT_ULL(2), + ROC_NIX_BPF_GREEN_OCTS_F_DROP = BIT_ULL(3), + ROC_NIX_BPF_YELLOW_PKT_F_PASS = BIT_ULL(4), + ROC_NIX_BPF_YELLOW_OCTS_F_PASS = BIT_ULL(5), + ROC_NIX_BPF_YELLOW_PKT_F_DROP = BIT_ULL(6), + ROC_NIX_BPF_YELLOW_OCTS_F_DROP = BIT_ULL(7), + ROC_NIX_BPF_RED_PKT_F_PASS = BIT_ULL(8), + ROC_NIX_BPF_RED_OCTS_F_PASS = BIT_ULL(9), + ROC_NIX_BPF_RED_PKT_F_DROP = BIT_ULL(10), + ROC_NIX_BPF_RED_OCTS_F_DROP = BIT_ULL(11), +}; + struct roc_nix_bpf_cfg { enum roc_nix_bpf_algo alg; enum roc_nix_bpf_lmode lmode; @@ -595,6 +611,8 @@ int __roc_api roc_nix_bpf_connect(struct roc_nix *roc_nix, uint8_t __roc_api roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag lvl_flag); +uint8_t __roc_api roc_nix_bpf_stats_to_idx(enum roc_nix_bpf_stats lvl_flag); + /* MAC */ int __roc_api roc_nix_mac_rxtx_start_stop(struct roc_nix *roc_nix, bool start); int __roc_api roc_nix_mac_link_event_start_stop(struct roc_nix *roc_nix, diff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c index f5822136d1..8f45650d18 100644 --- a/drivers/common/cnxk/roc_nix_bpf.c +++ b/drivers/common/cnxk/roc_nix_bpf.c @@ -300,6 +300,40 @@ roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag level_f) return idx; } +uint8_t +roc_nix_bpf_stats_to_idx(enum roc_nix_bpf_stats level_f) +{ + uint8_t idx; + + if (level_f & ROC_NIX_BPF_GREEN_PKT_F_PASS) + idx = 0; + else if (level_f & ROC_NIX_BPF_GREEN_OCTS_F_PASS) + idx = 1; + else if (level_f & ROC_NIX_BPF_GREEN_PKT_F_DROP) + idx = 2; + else if (level_f & ROC_NIX_BPF_GREEN_OCTS_F_DROP) + idx = 3; + else if (level_f & ROC_NIX_BPF_YELLOW_PKT_F_PASS) + idx = 4; + else if (level_f & ROC_NIX_BPF_YELLOW_OCTS_F_PASS) + idx = 5; + else if (level_f & ROC_NIX_BPF_YELLOW_PKT_F_DROP) + idx = 6; + else if (level_f & ROC_NIX_BPF_YELLOW_OCTS_F_DROP) + idx = 7; + else if (level_f & ROC_NIX_BPF_RED_PKT_F_PASS) + idx = 8; + else if (level_f & ROC_NIX_BPF_RED_OCTS_F_PASS) + idx = 9; + else if (level_f & ROC_NIX_BPF_RED_PKT_F_DROP) + idx = 10; + else if (level_f & ROC_NIX_BPF_RED_OCTS_F_DROP) + idx = 11; + else + idx = ROC_NIX_BPF_STATS_MAX; + return idx; +} + int roc_nix_bpf_count_get(struct roc_nix *roc_nix, uint8_t lvl_mask, uint16_t count[ROC_NIX_BPF_LEVEL_MAX]) diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index c04a8ca9da..5d4bdd57a9 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -87,6 +87,7 @@ INTERNAL { roc_nix_bpf_free_all; roc_nix_bpf_level_to_idx; roc_nix_bpf_pre_color_tbl_setup; + roc_nix_bpf_stats_to_idx; roc_nix_cq_dump; roc_nix_cq_fini; roc_nix_cq_init; From patchwork Thu Sep 30 09:08:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100073 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 42B1FA0C41; Thu, 30 Sep 2021 11:10:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8804241151; Thu, 30 Sep 2021 11:09:24 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A15EC4114B for ; Thu, 30 Sep 2021 11:09:21 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18U1KeYu001484; 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Thu, 30 Sep 2021 02:09:16 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:16 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id B5BBC3F7075; Thu, 30 Sep 2021 02:09:14 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Thu, 30 Sep 2021 14:38:29 +0530 Message-ID: <20210930090844.1059326-12-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: LBAGDqXI3D8jRUJxgW1cV0dYpjU2tGPr X-Proofpoint-ORIG-GUID: LBAGDqXI3D8jRUJxgW1cV0dYpjU2tGPr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 12/27] common/cnxk: support RoC API to read profile statistics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori CN10K platform provides statistics per bandwidth profile and per nixlf. Implement RoC API to read stats for given bandwidth profile. Signed-off-by: Sunil Kumar Kori --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/common/cnxk/roc_nix.h | 9 ++ drivers/common/cnxk/roc_nix_bpf.c | 197 ++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 2 + 3 files changed, 208 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 7bff69d39f..0081ccc9ee 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -608,6 +608,15 @@ int __roc_api roc_nix_bpf_connect(struct roc_nix *roc_nix, enum roc_nix_bpf_level_flag lvl_flag, uint16_t src_id, uint16_t dst_id); +int __roc_api +roc_nix_bpf_stats_read(struct roc_nix *roc_nix, uint16_t id, uint64_t mask, + enum roc_nix_bpf_level_flag lvl_flag, + uint64_t stats[ROC_NIX_BPF_STATS_MAX] /* Out */); + +int __roc_api +roc_nix_bpf_lf_stats_read(struct roc_nix *roc_nix, uint64_t mask, + uint64_t stats[ROC_NIX_BPF_STATS_MAX] /* Out */); + uint8_t __roc_api roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag lvl_flag); diff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c index 8f45650d18..2169164d9c 100644 --- a/drivers/common/cnxk/roc_nix_bpf.c +++ b/drivers/common/cnxk/roc_nix_bpf.c @@ -17,6 +17,9 @@ (ROC_NIX_BPF_LEVEL_F_LEAF | ROC_NIX_BPF_LEVEL_F_MID | \ ROC_NIX_BPF_LEVEL_F_TOP) +#define NIX_RD_STATS(val) plt_read64(nix->base + NIX_LF_RX_STATX(val)) +#define NIX_RST_STATS(val) plt_write64(0, nix->base + NIX_LF_RX_STATX(val)) + static uint8_t sw_to_hw_lvl_map[] = {NIX_RX_BAND_PROF_LAYER_LEAF, NIX_RX_BAND_PROF_LAYER_MIDDLE, NIX_RX_BAND_PROF_LAYER_TOP}; @@ -831,3 +834,197 @@ roc_nix_bpf_connect(struct roc_nix *roc_nix, return mbox_process(mbox); } + +int +roc_nix_bpf_stats_read(struct roc_nix *roc_nix, uint16_t id, uint64_t mask, + enum roc_nix_bpf_level_flag lvl_flag, + uint64_t stats[ROC_NIX_BPF_STATS_MAX]) +{ + uint8_t yellow_pkt_pass, yellow_octs_pass, yellow_pkt_drop; + uint8_t green_octs_drop, yellow_octs_drop, red_octs_drop; + uint8_t green_pkt_pass, green_octs_pass, green_pkt_drop; + uint8_t red_pkt_pass, red_octs_pass, red_pkt_drop; + struct mbox *mbox = get_mbox(roc_nix); + struct nix_cn10k_aq_enq_rsp *rsp; + struct nix_cn10k_aq_enq_req *aq; + uint8_t level_idx; + int rc; + + if (roc_model_is_cn9k()) + return NIX_ERR_HW_NOTSUP; + + level_idx = roc_nix_bpf_level_to_idx(lvl_flag); + if (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID) + return NIX_ERR_PARAM; + + aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox); + if (aq == NULL) + return -ENOSPC; + aq->qidx = (sw_to_hw_lvl_map[level_idx] << 14 | id); + aq->ctype = NIX_AQ_CTYPE_BAND_PROF; + aq->op = NIX_AQ_INSTOP_READ; + rc = mbox_process_msg(mbox, (void *)&rsp); + if (rc) + return rc; + + green_pkt_pass = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_GREEN_PKT_F_PASS); + green_octs_pass = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_GREEN_OCTS_F_PASS); + green_pkt_drop = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_GREEN_PKT_F_DROP); + green_octs_drop = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_GREEN_OCTS_F_DROP); + yellow_pkt_pass = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_YELLOW_PKT_F_PASS); + yellow_octs_pass = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_YELLOW_OCTS_F_PASS); + yellow_pkt_drop = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_YELLOW_PKT_F_DROP); + yellow_octs_drop = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_YELLOW_OCTS_F_DROP); + red_pkt_pass = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_RED_PKT_F_PASS); + red_octs_pass = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_RED_OCTS_F_PASS); + red_pkt_drop = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_RED_PKT_F_DROP); + red_octs_drop = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_RED_OCTS_F_DROP); + + if (green_pkt_pass != ROC_NIX_BPF_STATS_MAX) + stats[green_pkt_pass] = rsp->prof.green_pkt_pass; + + if (green_octs_pass != ROC_NIX_BPF_STATS_MAX) + stats[green_octs_pass] = rsp->prof.green_octs_pass; + + if (green_pkt_drop != ROC_NIX_BPF_STATS_MAX) + stats[green_pkt_drop] = rsp->prof.green_pkt_drop; + + if (green_octs_drop != ROC_NIX_BPF_STATS_MAX) + stats[green_octs_drop] = rsp->prof.green_octs_pass; + + if (yellow_pkt_pass != ROC_NIX_BPF_STATS_MAX) + stats[yellow_pkt_pass] = rsp->prof.yellow_pkt_pass; + + if (yellow_octs_pass != ROC_NIX_BPF_STATS_MAX) + stats[yellow_octs_pass] = rsp->prof.yellow_octs_pass; + + if (yellow_pkt_drop != ROC_NIX_BPF_STATS_MAX) + stats[yellow_pkt_drop] = rsp->prof.yellow_pkt_drop; + + if (yellow_octs_drop != ROC_NIX_BPF_STATS_MAX) + stats[yellow_octs_drop] = rsp->prof.yellow_octs_drop; + + if (red_pkt_pass != ROC_NIX_BPF_STATS_MAX) + stats[red_pkt_pass] = rsp->prof.red_pkt_pass; + + if (red_octs_pass != ROC_NIX_BPF_STATS_MAX) + stats[red_octs_pass] = rsp->prof.red_octs_pass; + + if (red_pkt_drop != ROC_NIX_BPF_STATS_MAX) + stats[red_pkt_drop] = rsp->prof.red_pkt_drop; + + if (red_octs_drop != ROC_NIX_BPF_STATS_MAX) + stats[red_octs_drop] = rsp->prof.red_octs_drop; + + return 0; +} + +int +roc_nix_bpf_lf_stats_read(struct roc_nix *roc_nix, uint64_t mask, + uint64_t stats[ROC_NIX_BPF_STATS_MAX]) +{ + uint8_t yellow_pkt_pass, yellow_octs_pass, yellow_pkt_drop; + uint8_t green_octs_drop, yellow_octs_drop, red_octs_drop; + uint8_t green_pkt_pass, green_octs_pass, green_pkt_drop; + uint8_t red_pkt_pass, red_octs_pass, red_pkt_drop; + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + + green_pkt_pass = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_GREEN_PKT_F_PASS); + green_octs_pass = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_GREEN_OCTS_F_PASS); + green_pkt_drop = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_GREEN_PKT_F_DROP); + green_octs_drop = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_GREEN_OCTS_F_DROP); + yellow_pkt_pass = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_YELLOW_PKT_F_PASS); + yellow_octs_pass = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_YELLOW_OCTS_F_PASS); + yellow_pkt_drop = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_YELLOW_PKT_F_DROP); + yellow_octs_drop = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_YELLOW_OCTS_F_DROP); + red_pkt_pass = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_RED_PKT_F_PASS); + red_octs_pass = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_RED_OCTS_F_PASS); + red_pkt_drop = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_RED_PKT_F_DROP); + red_octs_drop = + roc_nix_bpf_stats_to_idx(mask & ROC_NIX_BPF_RED_OCTS_F_DROP); + + if (green_pkt_pass != ROC_NIX_BPF_STATS_MAX) { + stats[green_pkt_pass] = + NIX_RD_STATS(NIX_STAT_LF_RX_RX_GC_OCTS_PASSED); + } + + if (green_octs_pass != ROC_NIX_BPF_STATS_MAX) { + stats[green_octs_pass] = + NIX_RD_STATS(NIX_STAT_LF_RX_RX_YC_PKTS_PASSED); + } + + if (green_pkt_drop != ROC_NIX_BPF_STATS_MAX) { + stats[green_pkt_drop] = + NIX_RD_STATS(NIX_STAT_LF_RX_RX_GC_OCTS_DROP); + } + + if (green_octs_drop != ROC_NIX_BPF_STATS_MAX) { + stats[green_octs_drop] = + NIX_RD_STATS(NIX_STAT_LF_RX_RX_YC_PKTS_DROP); + } + + if (yellow_pkt_pass != ROC_NIX_BPF_STATS_MAX) { + stats[yellow_pkt_pass] = + NIX_RD_STATS(NIX_STAT_LF_RX_RX_GC_PKTS_PASSED); + } + + if (yellow_octs_pass != ROC_NIX_BPF_STATS_MAX) { + stats[yellow_octs_pass] = + NIX_RD_STATS(NIX_STAT_LF_RX_RX_RC_OCTS_PASSED); + } + + if (yellow_pkt_drop != ROC_NIX_BPF_STATS_MAX) { + stats[yellow_pkt_drop] = + NIX_RD_STATS(NIX_STAT_LF_RX_RX_GC_PKTS_DROP); + } + + if (yellow_octs_drop != ROC_NIX_BPF_STATS_MAX) { + stats[yellow_octs_drop] = + NIX_RD_STATS(NIX_STAT_LF_RX_RX_RC_OCTS_DROP); + } + + if (red_pkt_pass != ROC_NIX_BPF_STATS_MAX) { + stats[red_pkt_pass] = + NIX_RD_STATS(NIX_STAT_LF_RX_RX_YC_OCTS_PASSED); + } + + if (red_octs_pass != ROC_NIX_BPF_STATS_MAX) { + stats[red_octs_pass] = + NIX_RD_STATS(NIX_STAT_LF_RX_RX_RC_PKTS_PASSED); + } + + if (red_pkt_drop != ROC_NIX_BPF_STATS_MAX) { + stats[red_pkt_drop] = + NIX_RD_STATS(NIX_STAT_LF_RX_RX_YC_OCTS_DROP); + } + + if (red_octs_drop != ROC_NIX_BPF_STATS_MAX) { + stats[red_octs_drop] = + NIX_RD_STATS(NIX_STAT_LF_RX_RX_RC_PKTS_DROP); + } + + return 0; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 5d4bdd57a9..52e7fa1e89 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -86,7 +86,9 @@ INTERNAL { roc_nix_bpf_free; roc_nix_bpf_free_all; roc_nix_bpf_level_to_idx; + roc_nix_bpf_lf_stats_read; roc_nix_bpf_pre_color_tbl_setup; + roc_nix_bpf_stats_read; roc_nix_bpf_stats_to_idx; roc_nix_cq_dump; roc_nix_cq_fini; From patchwork Thu Sep 30 09:08:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100074 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4F77EA0C41; Thu, 30 Sep 2021 11:10:23 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9591A41155; Thu, 30 Sep 2021 11:09:25 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 7A77641150 for ; Thu, 30 Sep 2021 11:09:23 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18U1KYKV001412; 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Thu, 30 Sep 2021 02:09:19 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:19 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 2326E3F7068; Thu, 30 Sep 2021 02:09:16 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Thu, 30 Sep 2021 14:38:30 +0530 Message-ID: <20210930090844.1059326-13-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: m4jx3yBLTLbLm5zJgeU7HwXWldVQSXCN X-Proofpoint-ORIG-GUID: m4jx3yBLTLbLm5zJgeU7HwXWldVQSXCN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 13/27] common/cnxk: support RoC API to reset profile stats X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement RoC API to reset stats per bandwidth profile or per nixlf. Signed-off-by: Sunil Kumar Kori --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/common/cnxk/roc_nix.h | 7 ++ drivers/common/cnxk/roc_nix_bpf.c | 113 ++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 2 + 3 files changed, 122 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 0081ccc9ee..b6715ef2ed 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -613,10 +613,17 @@ roc_nix_bpf_stats_read(struct roc_nix *roc_nix, uint16_t id, uint64_t mask, enum roc_nix_bpf_level_flag lvl_flag, uint64_t stats[ROC_NIX_BPF_STATS_MAX] /* Out */); +int __roc_api roc_nix_bpf_stats_reset(struct roc_nix *roc_nix, uint16_t id, + uint64_t mask, + enum roc_nix_bpf_level_flag lvl_flag); + int __roc_api roc_nix_bpf_lf_stats_read(struct roc_nix *roc_nix, uint64_t mask, uint64_t stats[ROC_NIX_BPF_STATS_MAX] /* Out */); +int __roc_api roc_nix_bpf_lf_stats_reset(struct roc_nix *roc_nix, + uint64_t mask); + uint8_t __roc_api roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag lvl_flag); diff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c index 2169164d9c..bba906a59b 100644 --- a/drivers/common/cnxk/roc_nix_bpf.c +++ b/drivers/common/cnxk/roc_nix_bpf.c @@ -931,6 +931,86 @@ roc_nix_bpf_stats_read(struct roc_nix *roc_nix, uint16_t id, uint64_t mask, return 0; } +int +roc_nix_bpf_stats_reset(struct roc_nix *roc_nix, uint16_t id, uint64_t mask, + enum roc_nix_bpf_level_flag lvl_flag) +{ + struct mbox *mbox = get_mbox(roc_nix); + struct nix_cn10k_aq_enq_req *aq; + uint8_t level_idx; + + if (roc_model_is_cn9k()) + return NIX_ERR_HW_NOTSUP; + + level_idx = roc_nix_bpf_level_to_idx(lvl_flag); + if (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID) + return NIX_ERR_PARAM; + + aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox); + if (aq == NULL) + return -ENOSPC; + aq->qidx = (sw_to_hw_lvl_map[level_idx] << 14 | id); + aq->ctype = NIX_AQ_CTYPE_BAND_PROF; + aq->op = NIX_AQ_INSTOP_WRITE; + + if (mask & ROC_NIX_BPF_GREEN_PKT_F_PASS) { + aq->prof.green_pkt_pass = 0; + aq->prof_mask.green_pkt_pass = ~(aq->prof_mask.green_pkt_pass); + } + if (mask & ROC_NIX_BPF_GREEN_OCTS_F_PASS) { + aq->prof.green_octs_pass = 0; + aq->prof_mask.green_octs_pass = + ~(aq->prof_mask.green_octs_pass); + } + if (mask & ROC_NIX_BPF_GREEN_PKT_F_DROP) { + aq->prof.green_pkt_drop = 0; + aq->prof_mask.green_pkt_drop = ~(aq->prof_mask.green_pkt_drop); + } + if (mask & ROC_NIX_BPF_GREEN_OCTS_F_DROP) { + aq->prof.green_octs_drop = 0; + aq->prof_mask.green_octs_drop = + ~(aq->prof_mask.green_octs_drop); + } + if (mask & ROC_NIX_BPF_YELLOW_PKT_F_PASS) { + aq->prof.yellow_pkt_pass = 0; + aq->prof_mask.yellow_pkt_pass = + ~(aq->prof_mask.yellow_pkt_pass); + } + if (mask & ROC_NIX_BPF_YELLOW_OCTS_F_PASS) { + aq->prof.yellow_octs_pass = 0; + aq->prof_mask.yellow_octs_pass = + ~(aq->prof_mask.yellow_octs_pass); + } + if (mask & ROC_NIX_BPF_YELLOW_PKT_F_DROP) { + aq->prof.yellow_pkt_drop = 0; + aq->prof_mask.yellow_pkt_drop = + ~(aq->prof_mask.yellow_pkt_drop); + } + if (mask & ROC_NIX_BPF_YELLOW_OCTS_F_DROP) { + aq->prof.yellow_octs_drop = 0; + aq->prof_mask.yellow_octs_drop = + ~(aq->prof_mask.yellow_octs_drop); + } + if (mask & ROC_NIX_BPF_RED_PKT_F_PASS) { + aq->prof.red_pkt_pass = 0; + aq->prof_mask.red_pkt_pass = ~(aq->prof_mask.red_pkt_pass); + } + if (mask & ROC_NIX_BPF_RED_OCTS_F_PASS) { + aq->prof.red_octs_pass = 0; + aq->prof_mask.red_octs_pass = ~(aq->prof_mask.red_octs_pass); + } + if (mask & ROC_NIX_BPF_RED_PKT_F_DROP) { + aq->prof.red_pkt_drop = 0; + aq->prof_mask.red_pkt_drop = ~(aq->prof_mask.red_pkt_drop); + } + if (mask & ROC_NIX_BPF_RED_OCTS_F_DROP) { + aq->prof.red_octs_drop = 0; + aq->prof_mask.red_octs_drop = ~(aq->prof_mask.red_octs_drop); + } + + return mbox_process(mbox); +} + int roc_nix_bpf_lf_stats_read(struct roc_nix *roc_nix, uint64_t mask, uint64_t stats[ROC_NIX_BPF_STATS_MAX]) @@ -1028,3 +1108,36 @@ roc_nix_bpf_lf_stats_read(struct roc_nix *roc_nix, uint64_t mask, return 0; } + +int +roc_nix_bpf_lf_stats_reset(struct roc_nix *roc_nix, uint64_t mask) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + + if (mask & ROC_NIX_BPF_GREEN_PKT_F_PASS) + NIX_RST_STATS(ROC_NIX_BPF_GREEN_PKT_F_PASS); + if (mask & ROC_NIX_BPF_GREEN_OCTS_F_PASS) + NIX_RST_STATS(ROC_NIX_BPF_GREEN_OCTS_F_PASS); + if (mask & ROC_NIX_BPF_GREEN_PKT_F_DROP) + NIX_RST_STATS(ROC_NIX_BPF_GREEN_PKT_F_DROP); + if (mask & ROC_NIX_BPF_GREEN_OCTS_F_DROP) + NIX_RST_STATS(ROC_NIX_BPF_GREEN_OCTS_F_DROP); + if (mask & ROC_NIX_BPF_YELLOW_PKT_F_PASS) + NIX_RST_STATS(ROC_NIX_BPF_YELLOW_PKT_F_PASS); + if (mask & ROC_NIX_BPF_YELLOW_OCTS_F_PASS) + NIX_RST_STATS(ROC_NIX_BPF_YELLOW_OCTS_F_PASS); + if (mask & ROC_NIX_BPF_YELLOW_PKT_F_DROP) + NIX_RST_STATS(ROC_NIX_BPF_YELLOW_PKT_F_DROP); + if (mask & ROC_NIX_BPF_YELLOW_OCTS_F_DROP) + NIX_RST_STATS(ROC_NIX_BPF_YELLOW_OCTS_F_DROP); + if (mask & ROC_NIX_BPF_RED_PKT_F_PASS) + NIX_RST_STATS(ROC_NIX_BPF_RED_PKT_F_PASS); + if (mask & ROC_NIX_BPF_RED_OCTS_F_PASS) + NIX_RST_STATS(ROC_NIX_BPF_RED_OCTS_F_PASS); + if (mask & ROC_NIX_BPF_RED_PKT_F_DROP) + NIX_RST_STATS(ROC_NIX_BPF_RED_PKT_F_DROP); + if (mask & ROC_NIX_BPF_RED_OCTS_F_DROP) + NIX_RST_STATS(ROC_NIX_BPF_RED_OCTS_F_DROP); + + return 0; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 52e7fa1e89..3b08fb0025 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -87,8 +87,10 @@ INTERNAL { roc_nix_bpf_free_all; roc_nix_bpf_level_to_idx; roc_nix_bpf_lf_stats_read; + roc_nix_bpf_lf_stats_reset; roc_nix_bpf_pre_color_tbl_setup; roc_nix_bpf_stats_read; + roc_nix_bpf_stats_reset; roc_nix_bpf_stats_to_idx; roc_nix_cq_dump; roc_nix_cq_fini; From patchwork Thu Sep 30 09:08:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100075 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1AF51A0C41; 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Thu, 30 Sep 2021 02:09:23 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:09:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:21 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 83C063F7067; Thu, 30 Sep 2021 02:09:19 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Date: Thu, 30 Sep 2021 14:38:31 +0530 Message-ID: <20210930090844.1059326-14-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 9WhS6gZ6zW7t11_j83h65as5JzEmh03y X-Proofpoint-ORIG-GUID: 9WhS6gZ6zW7t11_j83h65as5JzEmh03y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 14/27] common/cnxk: support meter in action list X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Meter action is added in supported action list. Signed-off-by: Sunil Kumar Kori --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/common/cnxk/roc_npc.c | 3 +++ drivers/common/cnxk/roc_npc.h | 7 ++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c index 52a54b3990..8f88e254b3 100644 --- a/drivers/common/cnxk/roc_npc.c +++ b/drivers/common/cnxk/roc_npc.c @@ -447,6 +447,9 @@ npc_parse_actions(struct npc *npc, const struct roc_npc_attr *attr, case ROC_NPC_ACTION_TYPE_VLAN_PCP_INSERT: req_act |= ROC_NPC_ACTION_TYPE_VLAN_PCP_INSERT; break; + case ROC_NPC_ACTION_TYPE_METER: + req_act |= ROC_NPC_ACTION_TYPE_METER; + break; default: errcode = NPC_ERR_ACTION_NOTSUP; goto err_exit; diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h index 4d6f8f8cd9..86365df754 100644 --- a/drivers/common/cnxk/roc_npc.h +++ b/drivers/common/cnxk/roc_npc.h @@ -58,7 +58,7 @@ struct roc_npc_flow_item_raw { const uint8_t *pattern; /**< Byte string to look for. */ }; -#define ROC_NPC_MAX_ACTION_COUNT 12 +#define ROC_NPC_MAX_ACTION_COUNT 17 enum roc_npc_action_type { ROC_NPC_ACTION_TYPE_END = (1 << 0), @@ -77,6 +77,7 @@ enum roc_npc_action_type { ROC_NPC_ACTION_TYPE_VLAN_INSERT = (1 << 13), ROC_NPC_ACTION_TYPE_VLAN_ETHTYPE_INSERT = (1 << 14), ROC_NPC_ACTION_TYPE_VLAN_PCP_INSERT = (1 << 15), + ROC_NPC_ACTION_TYPE_METER = (1 << 16), }; struct roc_npc_action { @@ -110,6 +111,10 @@ struct roc_npc_action_of_set_vlan_pcp { uint8_t vlan_pcp; /**< VLAN priority. */ }; +struct roc_npc_action_meter { + uint32_t mtr_id; /**< Meter id to be applied. > */ +}; + struct roc_npc_attr { uint32_t priority; /**< Rule priority level within group. */ uint32_t ingress : 1; /**< Rule applies to ingress traffic. */ From patchwork Thu Sep 30 09:08:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100076 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ECA55A0C41; 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Thu, 30 Sep 2021 02:09:25 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:09:23 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:23 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id AF9723F7068; Thu, 30 Sep 2021 02:09:21 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rakesh Kudurumalla Date: Thu, 30 Sep 2021 14:38:32 +0530 Message-ID: <20210930090844.1059326-15-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ELhM_limhB5Yo-de6ORFPXY3H_egjKRV X-Proofpoint-ORIG-GUID: ELhM_limhB5Yo-de6ORFPXY3H_egjKRV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 15/27] net/cnxk: support meter ops get API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori To enable support for ingress meter, supported operations are exposed for CN10K platform. Signed-off-by: Sunil Kumar Kori Signed-off-by: Rakesh Kudurumalla --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/net/cnxk/cn10k_ethdev.c | 1 + drivers/net/cnxk/cn10k_ethdev.h | 2 ++ drivers/net/cnxk/cn10k_ethdev_mtr.c | 18 ++++++++++++++++++ drivers/net/cnxk/meson.build | 1 + 4 files changed, 22 insertions(+) create mode 100644 drivers/net/cnxk/cn10k_ethdev_mtr.c diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c index 7caec6cf14..8c1f6a4408 100644 --- a/drivers/net/cnxk/cn10k_ethdev.c +++ b/drivers/net/cnxk/cn10k_ethdev.c @@ -457,6 +457,7 @@ nix_eth_dev_ops_override(void) cnxk_eth_dev_ops.dev_ptypes_set = cn10k_nix_ptypes_set; cnxk_eth_dev_ops.timesync_enable = cn10k_nix_timesync_enable; cnxk_eth_dev_ops.timesync_disable = cn10k_nix_timesync_disable; + cnxk_eth_dev_ops.mtr_ops_get = cn10k_nix_mtr_ops_get; } static void diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h index 8b6e0f2b3f..117aa2a62d 100644 --- a/drivers/net/cnxk/cn10k_ethdev.h +++ b/drivers/net/cnxk/cn10k_ethdev.h @@ -38,4 +38,6 @@ struct cn10k_eth_rxq { void cn10k_eth_set_rx_function(struct rte_eth_dev *eth_dev); void cn10k_eth_set_tx_function(struct rte_eth_dev *eth_dev); +/* MTR */ +int cn10k_nix_mtr_ops_get(struct rte_eth_dev *dev, void *ops); #endif /* __CN10K_ETHDEV_H__ */ diff --git a/drivers/net/cnxk/cn10k_ethdev_mtr.c b/drivers/net/cnxk/cn10k_ethdev_mtr.c new file mode 100644 index 0000000000..9b46032858 --- /dev/null +++ b/drivers/net/cnxk/cn10k_ethdev_mtr.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_ethdev.h" +#include + +const struct rte_mtr_ops nix_mtr_ops = { +}; + +int +cn10k_nix_mtr_ops_get(struct rte_eth_dev *dev, void *ops) +{ + RTE_SET_USED(dev); + + *(const void **)ops = &nix_mtr_ops; + return 0; +} diff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build index d4cdd1744a..91afc1de4c 100644 --- a/drivers/net/cnxk/meson.build +++ b/drivers/net/cnxk/meson.build @@ -35,6 +35,7 @@ sources += files( # CN10K sources += files( 'cn10k_ethdev.c', + 'cn10k_ethdev_mtr.c', 'cn10k_rte_flow.c', 'cn10k_rx.c', 'cn10k_rx_mseg.c', From patchwork Thu Sep 30 09:08:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100077 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7F8EA0C41; Thu, 30 Sep 2021 11:10:48 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2A62A41167; Thu, 30 Sep 2021 11:09:31 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 974C241103 for ; Thu, 30 Sep 2021 11:09:28 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18U1KYKW001412 for ; Thu, 30 Sep 2021 02:09:28 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; 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Thu, 30 Sep 2021 02:09:23 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rakesh Kudurumalla Date: Thu, 30 Sep 2021 14:38:33 +0530 Message-ID: <20210930090844.1059326-16-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: OP2kR76lRmbCJuilZpK-6rVz2Z1l-nyA X-Proofpoint-ORIG-GUID: OP2kR76lRmbCJuilZpK-6rVz2Z1l-nyA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 16/27] net/cnxk: support ops to get meter capabilities X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement ethdev operation to get meter capabilities for CN10K platform. Signed-off-by: Sunil Kumar Kori Signed-off-by: Rakesh Kudurumalla --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/net/cnxk/cn10k_ethdev_mtr.c | 48 +++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev_mtr.c b/drivers/net/cnxk/cn10k_ethdev_mtr.c index 9b46032858..a1b42831a5 100644 --- a/drivers/net/cnxk/cn10k_ethdev_mtr.c +++ b/drivers/net/cnxk/cn10k_ethdev_mtr.c @@ -5,7 +5,55 @@ #include "cn10k_ethdev.h" #include +#define NIX_MTR_COUNT_MAX 73 /* 64(leaf) + 8(mid) + 1(top) */ +#define NIX_MTR_COUNT_PER_FLOW 3 /* 1(leaf) + 1(mid) + 1(top) */ + +static struct rte_mtr_capabilities mtr_capa = { + .n_max = NIX_MTR_COUNT_MAX, + .n_shared_max = NIX_MTR_COUNT_PER_FLOW, + /* .identical = , */ + .shared_identical = true, + /* .shared_n_flows_per_mtr_max = ,*/ + .chaining_n_mtrs_per_flow_max = NIX_MTR_COUNT_PER_FLOW, + .chaining_use_prev_mtr_color_supported = true, + .chaining_use_prev_mtr_color_enforced = true, + .meter_srtcm_rfc2697_n_max = NIX_MTR_COUNT_MAX, + .meter_trtcm_rfc2698_n_max = NIX_MTR_COUNT_MAX, + .meter_trtcm_rfc4115_n_max = NIX_MTR_COUNT_MAX, + .meter_rate_max = NIX_BPF_RATE_MAX / 8, /* Bytes per second */ + .meter_policy_n_max = NIX_MTR_COUNT_MAX, + .color_aware_srtcm_rfc2697_supported = true, + .color_aware_trtcm_rfc2698_supported = true, + .color_aware_trtcm_rfc4115_supported = true, + .srtcm_rfc2697_byte_mode_supported = true, + .srtcm_rfc2697_packet_mode_supported = true, + .trtcm_rfc2698_byte_mode_supported = true, + .trtcm_rfc2698_packet_mode_supported = true, + .trtcm_rfc4115_byte_mode_supported = true, + .trtcm_rfc4115_packet_mode_supported = true, + .stats_mask = RTE_MTR_STATS_N_PKTS_GREEN | RTE_MTR_STATS_N_PKTS_YELLOW | + RTE_MTR_STATS_N_PKTS_RED | RTE_MTR_STATS_N_PKTS_DROPPED | + RTE_MTR_STATS_N_BYTES_GREEN | + RTE_MTR_STATS_N_BYTES_YELLOW | RTE_MTR_STATS_N_BYTES_RED | + RTE_MTR_STATS_N_BYTES_DROPPED}; + +static int +cn10k_nix_mtr_capabilities_get(struct rte_eth_dev *dev, + struct rte_mtr_capabilities *capa, + struct rte_mtr_error *error) +{ + RTE_SET_USED(dev); + + if (!capa) + return -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_MTR_PARAMS, NULL, + "NULL input parameter"); + *capa = mtr_capa; + return 0; +} + const struct rte_mtr_ops nix_mtr_ops = { + .capabilities_get = cn10k_nix_mtr_capabilities_get, }; int From patchwork Thu Sep 30 09:08:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100078 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 757B5A0C41; Thu, 30 Sep 2021 11:10:56 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 48F334113F; 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Thu, 30 Sep 2021 02:09:30 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:09:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:28 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 85B123F7068; Thu, 30 Sep 2021 02:09:26 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rakesh Kudurumalla Date: Thu, 30 Sep 2021 14:38:34 +0530 Message-ID: <20210930090844.1059326-17-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 2JLVFQyW2OKsrRSJ8pDChowr_whjpokQ X-Proofpoint-ORIG-GUID: 2JLVFQyW2OKsrRSJ8pDChowr_whjpokQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 17/27] net/cnxk: support ops to create meter profile X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement API to add meter profile for CN10K platform. Signed-off-by: Sunil Kumar Kori Signed-off-by: Rakesh Kudurumalla --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/net/cnxk/cn10k_ethdev_mtr.c | 138 ++++++++++++++++++++++++++++ drivers/net/cnxk/cnxk_ethdev.c | 14 +++ drivers/net/cnxk/cnxk_ethdev.h | 13 +++ 3 files changed, 165 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev_mtr.c b/drivers/net/cnxk/cn10k_ethdev_mtr.c index a1b42831a5..69efe395b5 100644 --- a/drivers/net/cnxk/cn10k_ethdev_mtr.c +++ b/drivers/net/cnxk/cn10k_ethdev_mtr.c @@ -37,6 +37,106 @@ static struct rte_mtr_capabilities mtr_capa = { RTE_MTR_STATS_N_BYTES_YELLOW | RTE_MTR_STATS_N_BYTES_RED | RTE_MTR_STATS_N_BYTES_DROPPED}; +static struct cnxk_mtr_profile_node * +nix_mtr_profile_find(struct cnxk_eth_dev *dev, uint32_t profile_id) +{ + struct cnxk_mtr_profiles *fmps = &dev->mtr_profiles; + struct cnxk_mtr_profile_node *fmp; + + TAILQ_FOREACH(fmp, fmps, next) + if (profile_id == fmp->id) + return fmp; + + return NULL; +} + +static int +nix_mtr_profile_validate(struct cnxk_eth_dev *dev, uint32_t profile_id, + struct rte_mtr_meter_profile *profile, + struct rte_mtr_error *error) +{ + int rc = 0; + + PLT_SET_USED(dev); + + if (profile == NULL) + return -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_METER_PROFILE, + NULL, "Meter profile is null."); + + if (profile_id == UINT32_MAX) + return -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_METER_PROFILE_ID, + NULL, "Meter profile id not valid."); + + switch (profile->alg) { + case RTE_MTR_SRTCM_RFC2697: + if (profile->srtcm_rfc2697.cir > mtr_capa.meter_rate_max) + rc = -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_METER_PROFILE, NULL, + "CIR exceeds max meter rate"); + + if (profile->srtcm_rfc2697.cbs > NIX_BPF_BURST_MAX) + rc = -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_METER_PROFILE, NULL, + "CBS exceeds max meter burst size"); + + if (profile->srtcm_rfc2697.ebs > NIX_BPF_BURST_MAX) + rc = -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_METER_PROFILE, NULL, + "EBS exceeds max meter burst size"); + break; + + case RTE_MTR_TRTCM_RFC2698: + if (profile->trtcm_rfc2698.cir > mtr_capa.meter_rate_max) + rc = -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_METER_PROFILE, NULL, + "CIR exceeds max meter rate"); + + if (profile->trtcm_rfc2698.pir > mtr_capa.meter_rate_max) + rc = -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_METER_PROFILE, NULL, + "PIR exceeds max meter rate"); + + if (profile->trtcm_rfc2698.cbs > NIX_BPF_BURST_MAX) + rc = -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_METER_PROFILE, NULL, + "CBS exceeds max meter burst size"); + + if (profile->trtcm_rfc2698.pbs > NIX_BPF_BURST_MAX) + rc = -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_METER_PROFILE, NULL, + "PBS exceeds max meter burst size"); + break; + + case RTE_MTR_TRTCM_RFC4115: + if ((profile->trtcm_rfc4115.cir + profile->trtcm_rfc4115.eir) > + mtr_capa.meter_rate_max) + rc = -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_METER_PROFILE, NULL, + "PIR + EIR exceeds max rate"); + + if (profile->trtcm_rfc4115.cbs > NIX_BPF_BURST_MAX) + rc = -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_METER_PROFILE, NULL, + "CBS exceeds max meter burst size"); + + if (profile->trtcm_rfc4115.ebs > NIX_BPF_BURST_MAX) + rc = -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_METER_PROFILE, NULL, + "PBS exceeds max meter burst size"); + break; + + default: + rc = -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_METER_PROFILE, NULL, + "alg is invalid"); + break; + } + + return rc; +} + static int cn10k_nix_mtr_capabilities_get(struct rte_eth_dev *dev, struct rte_mtr_capabilities *capa, @@ -52,8 +152,46 @@ cn10k_nix_mtr_capabilities_get(struct rte_eth_dev *dev, return 0; } +static int +cn10k_nix_mtr_profile_add(struct rte_eth_dev *eth_dev, uint32_t profile_id, + struct rte_mtr_meter_profile *profile, + struct rte_mtr_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_mtr_profiles *fmps = &dev->mtr_profiles; + struct cnxk_mtr_profile_node *fmp; + int ret; + + /* Check input params. */ + ret = nix_mtr_profile_validate(dev, profile_id, profile, error); + if (ret) + return ret; + + fmp = nix_mtr_profile_find(dev, profile_id); + if (fmp) { + return -rte_mtr_error_set(error, EEXIST, + RTE_MTR_ERROR_TYPE_METER_PROFILE_ID, + NULL, "Profile already exist"); + } + + fmp = plt_zmalloc(sizeof(struct cnxk_mtr_profile_node), ROC_ALIGN); + if (fmp == NULL) + return -rte_mtr_error_set(error, ENOMEM, + RTE_MTR_ERROR_TYPE_UNSPECIFIED, NULL, + "Meter profile memory " + "alloc failed."); + + fmp->id = profile_id; + fmp->profile = *profile; + + TAILQ_INSERT_TAIL(fmps, fmp, next); + + return 0; +} + const struct rte_mtr_ops nix_mtr_ops = { .capabilities_get = cn10k_nix_mtr_capabilities_get, + .meter_profile_add = cn10k_nix_mtr_profile_add, }; int diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 7152dcd002..e952aa5ec5 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -504,6 +504,14 @@ nix_free_queue_mem(struct cnxk_eth_dev *dev) dev->sqs = NULL; } +static int +nix_ingress_policer_setup(struct cnxk_eth_dev *dev) +{ + TAILQ_INIT(&dev->mtr_profiles); + + return 0; +} + static int nix_rss_default_setup(struct cnxk_eth_dev *dev) { @@ -901,6 +909,12 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) goto free_nix_lf; } + rc = nix_ingress_policer_setup(dev); + if (rc) { + plt_err("Failed to setup ingress policer rc=%d", rc); + goto free_nix_lf; + } + rc = roc_nix_tm_hierarchy_enable(nix, ROC_NIX_TM_DEFAULT, false); if (rc) { plt_err("Failed to enable default tm hierarchy, rc=%d", rc); diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 27920c84f2..2b9b5beb83 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -13,6 +13,7 @@ #include #include #include +#include #include #include "roc_api.h" @@ -144,6 +145,15 @@ struct cnxk_timesync_info { uint64_t *tx_tstamp; } __plt_cache_aligned; +struct cnxk_mtr_profile_node { + TAILQ_ENTRY(cnxk_mtr_profile_node) next; + struct rte_mtr_meter_profile profile; /**< Profile detail. */ + uint32_t ref_cnt; /**< Use count. */ + uint32_t id; /**< Profile id. */ +}; + +TAILQ_HEAD(cnxk_mtr_profiles, cnxk_mtr_profile_node); + struct cnxk_eth_dev { /* ROC NIX */ struct roc_nix nix; @@ -211,6 +221,9 @@ struct cnxk_eth_dev { double clk_freq_mult; uint64_t clk_delta; + /* Ingress policer */ + struct cnxk_mtr_profiles mtr_profiles; + /* Rx burst for cleanup(Only Primary) */ eth_rx_burst_t rx_pkt_burst_no_offload; From patchwork Thu Sep 30 09:08:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100079 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A5601A0C41; Thu, 30 Sep 2021 11:11:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5818C4116F; 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Thu, 30 Sep 2021 02:09:32 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:09:30 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:30 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id E5C9F3F706B; Thu, 30 Sep 2021 02:09:28 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rakesh Kudurumalla Date: Thu, 30 Sep 2021 14:38:35 +0530 Message-ID: <20210930090844.1059326-18-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: zt5tae7cL9WT9-qIvK9xgidbdyvAbQS4 X-Proofpoint-ORIG-GUID: zt5tae7cL9WT9-qIvK9xgidbdyvAbQS4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 18/27] net/cnxk: support ops to delete meter profile X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement API to delete meter profile for CN10K platform. Signed-off-by: Sunil Kumar Kori Signed-off-by: Rakesh Kudurumalla --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/net/cnxk/cn10k_ethdev_mtr.c | 30 +++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev_mtr.c b/drivers/net/cnxk/cn10k_ethdev_mtr.c index 69efe395b5..ea4d898cd7 100644 --- a/drivers/net/cnxk/cn10k_ethdev_mtr.c +++ b/drivers/net/cnxk/cn10k_ethdev_mtr.c @@ -189,9 +189,39 @@ cn10k_nix_mtr_profile_add(struct rte_eth_dev *eth_dev, uint32_t profile_id, return 0; } +static int +cn10k_nix_mtr_profile_delete(struct rte_eth_dev *eth_dev, uint32_t profile_id, + struct rte_mtr_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_mtr_profile_node *fmp; + + if (profile_id == UINT32_MAX) + return -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_METER_PROFILE_ID, + NULL, "Meter profile id not valid."); + + fmp = nix_mtr_profile_find(dev, profile_id); + if (fmp == NULL) + return -rte_mtr_error_set(error, ENOENT, + RTE_MTR_ERROR_TYPE_METER_PROFILE_ID, + &profile_id, + "Meter profile is invalid."); + + if (fmp->ref_cnt) + return -rte_mtr_error_set(error, EBUSY, + RTE_MTR_ERROR_TYPE_METER_PROFILE_ID, + NULL, "Meter profile is in use."); + + TAILQ_REMOVE(&dev->mtr_profiles, fmp, next); + plt_free(fmp); + return 0; +} + const struct rte_mtr_ops nix_mtr_ops = { .capabilities_get = cn10k_nix_mtr_capabilities_get, .meter_profile_add = cn10k_nix_mtr_profile_add, + .meter_profile_delete = cn10k_nix_mtr_profile_delete, }; int From patchwork Thu Sep 30 09:08:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100080 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E1211A0C41; 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Thu, 30 Sep 2021 02:09:35 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:09:33 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:33 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 51D593F7067; Thu, 30 Sep 2021 02:09:31 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rakesh Kudurumalla Date: Thu, 30 Sep 2021 14:38:36 +0530 Message-ID: <20210930090844.1059326-19-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: phkROnqNhnsFVlvoSKauRd9VewLCHhK0 X-Proofpoint-ORIG-GUID: phkROnqNhnsFVlvoSKauRd9VewLCHhK0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 19/27] net/cnxk: support ops to validate meter policy X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement API to validate meter policy for CN10K platform. Signed-off-by: Sunil Kumar Kori Signed-off-by: Rakesh Kudurumalla --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/net/cnxk/cn10k_ethdev_mtr.c | 49 +++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev_mtr.c b/drivers/net/cnxk/cn10k_ethdev_mtr.c index ea4d898cd7..4cf4ebd6fd 100644 --- a/drivers/net/cnxk/cn10k_ethdev_mtr.c +++ b/drivers/net/cnxk/cn10k_ethdev_mtr.c @@ -218,10 +218,59 @@ cn10k_nix_mtr_profile_delete(struct rte_eth_dev *eth_dev, uint32_t profile_id, return 0; } +static int +cn10k_nix_mtr_policy_validate(struct rte_eth_dev *dev, + struct rte_mtr_meter_policy_params *policy, + struct rte_mtr_error *error) +{ + static const char *const action_color[] = {"Green", "Yellow", "Red"}; + bool supported[RTE_COLORS] = {false, false, false}; + const struct rte_flow_action *action; + char message[1024]; + uint32_t i; + + RTE_SET_USED(dev); + + if (!policy) + return 0; /* Nothing to be validated */ + + for (i = 0; i < RTE_COLORS; i++) { + if (policy->actions[i]) { + for (action = policy->actions[i]; + action->type != RTE_FLOW_ACTION_TYPE_END; + action++) { + if (action->type == RTE_FLOW_ACTION_TYPE_METER) + supported[i] = true; + + if (action->type == RTE_FLOW_ACTION_TYPE_DROP) + supported[i] = true; + + if (!supported[i]) { + sprintf(message, + "%s action is not valid", + action_color[i]); + return -rte_mtr_error_set(error, + ENOTSUP, + RTE_MTR_ERROR_TYPE_METER_POLICY, NULL, + message); + } + } + } else { + sprintf(message, "%s action is null", action_color[i]); + return -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_METER_POLICY, NULL, + message); + } + } + + return 0; +} + const struct rte_mtr_ops nix_mtr_ops = { .capabilities_get = cn10k_nix_mtr_capabilities_get, .meter_profile_add = cn10k_nix_mtr_profile_add, .meter_profile_delete = cn10k_nix_mtr_profile_delete, + .meter_policy_validate = cn10k_nix_mtr_policy_validate, }; int From patchwork Thu Sep 30 09:08:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100081 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 18309A0C41; Thu, 30 Sep 2021 11:11:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C45704117B; Thu, 30 Sep 2021 11:09:42 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 5558941174 for ; Thu, 30 Sep 2021 11:09:38 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18U1KcVn001444 for ; Thu, 30 Sep 2021 02:09:37 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=NRSmHnAccV45VnGEpS+RupfO29bplFpyELI7gy6NKVs=; b=iQTo+y4r+4to+cC4pS5c3E5XNWWSqeuH1LrVhdExkZ9ZYbbbem8akIVaS3eG0JsNPjNj sNDpLkhDcLU0AHEwBqD3dtYUC7M8CZsJ6GzTREOeVO765Y1Jm5zG9Ag+WOOtVJtPFyMH LLooNh4rKzBj2+BkO04QHYf6iim0gtAx6H5Dw+W6B6tg7X3xJz85paKPvmoi33dC+Lka y3wPhxNCeQOhv890jCSqIZp6PzGvObqfNH/cBLgdW5+HDn3E4zmCV1lpDnkDXIYjUtJN 13Ex5OxPJlFG8HWgpN92nxZXBOWb2As/VYbrkI/+blQQjEGTWsUeNPK0K+IFHa1l8ScG Aw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3bd3g39kf5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 30 Sep 2021 02:09:37 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:09:35 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:35 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id B93D03F7068; Thu, 30 Sep 2021 02:09:33 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rakesh Kudurumalla Date: Thu, 30 Sep 2021 14:38:37 +0530 Message-ID: <20210930090844.1059326-20-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: L99GOwXRQmDl6JmwH71aOS3RWdpSu9fm X-Proofpoint-ORIG-GUID: L99GOwXRQmDl6JmwH71aOS3RWdpSu9fm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 20/27] net/cnxk: support ops to create meter policy X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement API to add meter policy for CN10K platform. Signed-off-by: Sunil Kumar Kori Signed-off-by: Rakesh Kudurumalla --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/net/cnxk/cn10k_ethdev_mtr.c | 84 +++++++++++++++++++++++++++++ drivers/net/cnxk/cnxk_ethdev.c | 1 + drivers/net/cnxk/cnxk_ethdev.h | 31 +++++++++++ 3 files changed, 116 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev_mtr.c b/drivers/net/cnxk/cn10k_ethdev_mtr.c index 4cf4ebd6fd..bb191666c4 100644 --- a/drivers/net/cnxk/cn10k_ethdev_mtr.c +++ b/drivers/net/cnxk/cn10k_ethdev_mtr.c @@ -50,6 +50,18 @@ nix_mtr_profile_find(struct cnxk_eth_dev *dev, uint32_t profile_id) return NULL; } +static struct cnxk_mtr_policy_node * +nix_mtr_policy_find(struct cnxk_eth_dev *dev, uint32_t meter_policy_id) +{ + struct cnxk_mtr_policy *fmps = &dev->mtr_policy; + struct cnxk_mtr_policy_node *fmp; + + TAILQ_FOREACH(fmp, fmps, next) + if (meter_policy_id == fmp->id) + return fmp; + return NULL; +} + static int nix_mtr_profile_validate(struct cnxk_eth_dev *dev, uint32_t profile_id, struct rte_mtr_meter_profile *profile, @@ -266,11 +278,83 @@ cn10k_nix_mtr_policy_validate(struct rte_eth_dev *dev, return 0; } +static void +cn10k_fill_policy_actions(struct cnxk_mtr_policy_node *fmp, + struct rte_mtr_meter_policy_params *policy) + +{ + const struct rte_flow_action_meter *mtr; + const struct rte_flow_action *action; + int i; + + for (i = 0; i < RTE_COLORS; i++) { + if (policy->actions[i]) { + for (action = policy->actions[i]; + action->type != RTE_FLOW_ACTION_TYPE_END; + action++) { + if (action->type == + RTE_FLOW_ACTION_TYPE_METER) { + fmp->actions[i].action_fate = + action->type; + mtr = (const struct + rte_flow_action_meter *) + action->conf; + fmp->actions[i].mtr_id = mtr->mtr_id; + } + + if (action->type == RTE_FLOW_ACTION_TYPE_DROP) { + fmp->actions[i].action_fate = + action->type; + } + } + } + } +} + +static int +cn10k_nix_mtr_policy_add(struct rte_eth_dev *eth_dev, uint32_t policy_id, + struct rte_mtr_meter_policy_params *policy, + struct rte_mtr_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_mtr_policy *fmps = &dev->mtr_policy; + struct cnxk_mtr_policy_node *fmp; + int rc; + + fmp = nix_mtr_policy_find(dev, policy_id); + if (fmp) { + return -rte_mtr_error_set(error, EEXIST, + RTE_MTR_ERROR_TYPE_METER_POLICY_ID, + NULL, "Policy already exist"); + } + + fmp = plt_zmalloc(sizeof(struct cnxk_mtr_policy_node), ROC_ALIGN); + if (fmp == NULL) { + return -rte_mtr_error_set(error, ENOMEM, + RTE_MTR_ERROR_TYPE_UNSPECIFIED, NULL, + "Memory allocation failure"); + } else { + rc = cn10k_nix_mtr_policy_validate(eth_dev, policy, error); + if (rc) + goto exit; + } + + fmp->id = policy_id; + cn10k_fill_policy_actions(fmp, policy); + TAILQ_INSERT_TAIL(fmps, fmp, next); + return 0; + +exit: + plt_free(fmp); + return rc; +} + const struct rte_mtr_ops nix_mtr_ops = { .capabilities_get = cn10k_nix_mtr_capabilities_get, .meter_profile_add = cn10k_nix_mtr_profile_add, .meter_profile_delete = cn10k_nix_mtr_profile_delete, .meter_policy_validate = cn10k_nix_mtr_policy_validate, + .meter_policy_add = cn10k_nix_mtr_policy_add, }; int diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index e952aa5ec5..9e75060513 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -508,6 +508,7 @@ static int nix_ingress_policer_setup(struct cnxk_eth_dev *dev) { TAILQ_INIT(&dev->mtr_profiles); + TAILQ_INIT(&dev->mtr_policy); return 0; } diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 2b9b5beb83..4e45061c86 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -145,6 +145,35 @@ struct cnxk_timesync_info { uint64_t *tx_tstamp; } __plt_cache_aligned; +struct action_rss { + enum rte_eth_hash_function func; + uint32_t level; + uint64_t types; + uint32_t key_len; + uint32_t queue_num; + uint8_t *key; + uint16_t *queue; +}; + +struct policy_actions { + uint32_t action_fate; + union { + uint16_t queue; + uint32_t mtr_id; + struct action_rss *rss_desc; + }; +}; + +struct cnxk_mtr_policy_node { + TAILQ_ENTRY(cnxk_mtr_policy_node) next; + /**< Pointer to the next flow meter structure. */ + uint32_t id; /**< Policy id */ + uint32_t mtr_id; /** Meter id */ + struct rte_mtr_meter_policy_params policy; + struct policy_actions actions[RTE_COLORS]; + uint32_t ref_cnt; +}; + struct cnxk_mtr_profile_node { TAILQ_ENTRY(cnxk_mtr_profile_node) next; struct rte_mtr_meter_profile profile; /**< Profile detail. */ @@ -153,6 +182,7 @@ struct cnxk_mtr_profile_node { }; TAILQ_HEAD(cnxk_mtr_profiles, cnxk_mtr_profile_node); +TAILQ_HEAD(cnxk_mtr_policy, cnxk_mtr_policy_node); struct cnxk_eth_dev { /* ROC NIX */ @@ -223,6 +253,7 @@ struct cnxk_eth_dev { /* Ingress policer */ struct cnxk_mtr_profiles mtr_profiles; + struct cnxk_mtr_policy mtr_policy; /* Rx burst for cleanup(Only Primary) */ eth_rx_burst_t rx_pkt_burst_no_offload; From patchwork Thu Sep 30 09:08:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100082 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F063FA0C41; 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Thu, 30 Sep 2021 02:09:39 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:09:37 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:38 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 256A43F7067; Thu, 30 Sep 2021 02:09:35 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rakesh Kudurumalla Date: Thu, 30 Sep 2021 14:38:38 +0530 Message-ID: <20210930090844.1059326-21-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: L8qwbylHoRCPEUhHMAfj5NRx-vOCja4c X-Proofpoint-ORIG-GUID: L8qwbylHoRCPEUhHMAfj5NRx-vOCja4c X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 21/27] net/cnxk: support ops to delete meter policy X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement API to delete meter policy for CN10K platform. Signed-off-by: Sunil Kumar Kori Signed-off-by: Rakesh Kudurumalla --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/net/cnxk/cn10k_ethdev_mtr.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev_mtr.c b/drivers/net/cnxk/cn10k_ethdev_mtr.c index bb191666c4..ff865b8fa6 100644 --- a/drivers/net/cnxk/cn10k_ethdev_mtr.c +++ b/drivers/net/cnxk/cn10k_ethdev_mtr.c @@ -349,12 +349,38 @@ cn10k_nix_mtr_policy_add(struct rte_eth_dev *eth_dev, uint32_t policy_id, return rc; } +static int +cn10k_nix_mtr_policy_delete(struct rte_eth_dev *eth_dev, uint32_t policy_id, + struct rte_mtr_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_mtr_policy_node *fmp; + + fmp = nix_mtr_policy_find(dev, policy_id); + if (fmp == NULL) { + return -rte_mtr_error_set(error, ENOENT, + RTE_MTR_ERROR_TYPE_METER_POLICY_ID, + NULL, "No policy found"); + } + + if (fmp->ref_cnt) + return -rte_mtr_error_set(error, EBUSY, + RTE_MTR_ERROR_TYPE_METER_POLICY_ID, + NULL, "Meter policy is in use."); + + TAILQ_REMOVE(&dev->mtr_policy, fmp, next); + plt_free(fmp); + + return 0; +} + const struct rte_mtr_ops nix_mtr_ops = { .capabilities_get = cn10k_nix_mtr_capabilities_get, .meter_profile_add = cn10k_nix_mtr_profile_add, .meter_profile_delete = cn10k_nix_mtr_profile_delete, .meter_policy_validate = cn10k_nix_mtr_policy_validate, .meter_policy_add = cn10k_nix_mtr_policy_add, + .meter_policy_delete = cn10k_nix_mtr_policy_delete, }; int From patchwork Thu Sep 30 09:08:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100083 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5732DA0C41; Thu, 30 Sep 2021 11:11:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7723841122; Thu, 30 Sep 2021 11:09:50 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 75E5F4117F for ; Thu, 30 Sep 2021 11:09:43 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18U1KPt5001361 for ; Thu, 30 Sep 2021 02:09:42 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=z0wN/4AAWWvs9bR6wEFju51A97CqRKF58nkNldm87N8=; b=T8wWXCK+pK1NB60kCHk0eSx7rEmFrL2+3aC07tnJ5FbiPJDKxBKNH2mzslvWoqA38vJM LIokzdgrMO3fcbcjdNZ/qVhmoK930bHoxYx04ViAwRh3FQS2YKWfpjvcbRJ+QEpjn5Pv NvCpl8r51MYmniuT1wuA++wVlaE2WAghnuHEp6DL4e2JW8t90z40h9sVNV6NLpIXturg BAceedXgzLoUuIdUctdRWbaiC6GBMyovzyrepEi6rV+ZSrQdgbJhrvPlzWnUM4bZJEoG icazJJvqeAiDzD6X4eegfPxiCtcSoYY78M3/AsBQr9D8wLuVjVa28vIGoExw12D/t5qF LQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3bd3g39kff-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 30 Sep 2021 02:09:42 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:09:40 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:40 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 88D903F706B; Thu, 30 Sep 2021 02:09:38 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rakesh Kudurumalla Date: Thu, 30 Sep 2021 14:38:39 +0530 Message-ID: <20210930090844.1059326-22-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ms2rTOBJfqPs7_TyIg6q1tx7GEYk6pkD X-Proofpoint-ORIG-GUID: ms2rTOBJfqPs7_TyIg6q1tx7GEYk6pkD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 22/27] net/cnxk: support ops to create meter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement API to create meter instance for CN10K platform. Signed-off-by: Sunil Kumar Kori Signed-off-by: Rakesh Kudurumalla --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/net/cnxk/cn10k_ethdev_mtr.c | 97 +++++++++++++++++++++++++++++ drivers/net/cnxk/cnxk_ethdev.c | 1 + drivers/net/cnxk/cnxk_ethdev.h | 25 ++++++++ 3 files changed, 123 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev_mtr.c b/drivers/net/cnxk/cn10k_ethdev_mtr.c index ff865b8fa6..8916dc329f 100644 --- a/drivers/net/cnxk/cn10k_ethdev_mtr.c +++ b/drivers/net/cnxk/cn10k_ethdev_mtr.c @@ -37,6 +37,18 @@ static struct rte_mtr_capabilities mtr_capa = { RTE_MTR_STATS_N_BYTES_YELLOW | RTE_MTR_STATS_N_BYTES_RED | RTE_MTR_STATS_N_BYTES_DROPPED}; +static struct cnxk_meter_node * +nix_mtr_find(struct cnxk_eth_dev *dev, uint32_t meter_id) +{ + struct cnxk_mtr *fms = &dev->mtr; + struct cnxk_meter_node *fm; + + TAILQ_FOREACH(fm, fms, next) + if (meter_id == fm->id) + return fm; + return NULL; +} + static struct cnxk_mtr_profile_node * nix_mtr_profile_find(struct cnxk_eth_dev *dev, uint32_t profile_id) { @@ -374,6 +386,90 @@ cn10k_nix_mtr_policy_delete(struct rte_eth_dev *eth_dev, uint32_t policy_id, return 0; } +static int +cn10k_nix_mtr_create(struct rte_eth_dev *eth_dev, uint32_t mtr_id, + struct rte_mtr_params *params, int shared, + struct rte_mtr_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_mtr_profile_node *profile; + struct cnxk_mtr_policy_node *policy; + struct cnxk_mtr *fm = &dev->mtr; + struct cnxk_meter_node *mtr; + int i; + + RTE_SET_USED(shared); + + if (params == NULL) + return -rte_mtr_error_set(error, ENOENT, + RTE_MTR_ERROR_TYPE_MTR_PARAMS, NULL, + "Meter params are invalid."); + + profile = nix_mtr_profile_find(dev, params->meter_profile_id); + if (profile == NULL) + return -rte_mtr_error_set(error, ENOENT, + RTE_MTR_ERROR_TYPE_METER_PROFILE_ID, + ¶ms->meter_profile_id, + "Meter profile is invalid."); + + policy = nix_mtr_policy_find(dev, params->meter_policy_id); + if (policy == NULL) + return -rte_mtr_error_set(error, ENOENT, + RTE_MTR_ERROR_TYPE_METER_POLICY_ID, + ¶ms->meter_policy_id, + "Meter policy is invalid."); + + mtr = nix_mtr_find(dev, mtr_id); + if (mtr == NULL) { + mtr = plt_zmalloc(sizeof(struct cnxk_meter_node), ROC_ALIGN); + if (mtr == NULL) { + return -rte_mtr_error_set(error, ENOMEM, + RTE_MTR_ERROR_TYPE_UNSPECIFIED, NULL, + "Meter memory alloc failed."); + } else { + mtr->id = mtr_id; + mtr->profile = profile; + mtr->policy = policy; + mtr->params = *params; + mtr->bpf_id = ROC_NIX_BPF_ID_INVALID; + mtr->prev_cnt = 0; + for (i = 0; i < MAX_PRV_MTR_NODES; i++) + mtr->prev_id[i] = ROC_NIX_BPF_ID_INVALID; + mtr->next_id = ROC_NIX_BPF_ID_INVALID; + mtr->is_prev = false; + mtr->is_next = false; + mtr->level = ROC_NIX_BPF_LEVEL_IDX_INVALID; + + if (params->dscp_table) { + mtr->params.dscp_table = + plt_zmalloc(ROC_NIX_BPF_PRE_COLOR_MAX, + ROC_ALIGN); + if (mtr->params.dscp_table == NULL) { + plt_free(mtr); + return -rte_mtr_error_set(error, ENOMEM, + RTE_MTR_ERROR_TYPE_UNSPECIFIED, + NULL, "Memory alloc failed."); + } + + for (i = 0; i < ROC_NIX_BPF_PRE_COLOR_MAX; + i++) { + mtr->params.dscp_table[i] = + params->dscp_table[i]; + } + } + } + } else { + return -rte_mtr_error_set(error, EEXIST, + RTE_MTR_ERROR_TYPE_MTR_ID, NULL, + "Meter already exist"); + } + + profile->ref_cnt++; + policy->ref_cnt++; + TAILQ_INSERT_TAIL(fm, mtr, next); + return 0; +} + const struct rte_mtr_ops nix_mtr_ops = { .capabilities_get = cn10k_nix_mtr_capabilities_get, .meter_profile_add = cn10k_nix_mtr_profile_add, @@ -381,6 +477,7 @@ const struct rte_mtr_ops nix_mtr_ops = { .meter_policy_validate = cn10k_nix_mtr_policy_validate, .meter_policy_add = cn10k_nix_mtr_policy_add, .meter_policy_delete = cn10k_nix_mtr_policy_delete, + .create = cn10k_nix_mtr_create, }; int diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 9e75060513..4c12715756 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -509,6 +509,7 @@ nix_ingress_policer_setup(struct cnxk_eth_dev *dev) { TAILQ_INIT(&dev->mtr_profiles); TAILQ_INIT(&dev->mtr_policy); + TAILQ_INIT(&dev->mtr); return 0; } diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 4e45061c86..8d94d873bb 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -145,6 +145,28 @@ struct cnxk_timesync_info { uint64_t *tx_tstamp; } __plt_cache_aligned; +struct cnxk_meter_node { +#define MAX_PRV_MTR_NODES 10 + TAILQ_ENTRY(cnxk_meter_node) next; + /**< Pointer to the next flow meter structure. */ + uint32_t id; /**< Usr mtr id. */ + struct cnxk_mtr_profile_node *profile; + struct cnxk_mtr_policy_node *policy; + uint32_t bpf_id; /**< Hw mtr id. */ + uint32_t rq_num; + uint32_t *rq_id; + uint16_t level; + uint32_t prev_id[MAX_PRV_MTR_NODES]; /**< Prev mtr id for chaining */ + uint32_t prev_cnt; + uint32_t next_id; /**< Next mtr id for chaining */ + bool is_prev; + bool is_next; + struct rte_mtr_params params; + struct roc_nix_bpf_objs profs; + bool is_used; + uint32_t ref_cnt; +}; + struct action_rss { enum rte_eth_hash_function func; uint32_t level; @@ -183,6 +205,7 @@ struct cnxk_mtr_profile_node { TAILQ_HEAD(cnxk_mtr_profiles, cnxk_mtr_profile_node); TAILQ_HEAD(cnxk_mtr_policy, cnxk_mtr_policy_node); +TAILQ_HEAD(cnxk_mtr, cnxk_meter_node); struct cnxk_eth_dev { /* ROC NIX */ @@ -252,8 +275,10 @@ struct cnxk_eth_dev { uint64_t clk_delta; /* Ingress policer */ + enum roc_nix_bpf_color precolor_tbl[ROC_NIX_BPF_PRE_COLOR_MAX]; struct cnxk_mtr_profiles mtr_profiles; struct cnxk_mtr_policy mtr_policy; + struct cnxk_mtr mtr; /* Rx burst for cleanup(Only Primary) */ eth_rx_burst_t rx_pkt_burst_no_offload; From patchwork Thu Sep 30 09:08:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100084 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F2787A0C41; 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Thu, 30 Sep 2021 02:09:44 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:09:42 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:42 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id E8A4C3F7067; Thu, 30 Sep 2021 02:09:40 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rakesh Kudurumalla Date: Thu, 30 Sep 2021 14:38:40 +0530 Message-ID: <20210930090844.1059326-23-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: z0fkmBtuOtIuvd7w-A4nrvypnrwy7BrW X-Proofpoint-ORIG-GUID: z0fkmBtuOtIuvd7w-A4nrvypnrwy7BrW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 23/27] net/cnxk: support ops to delete meter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement API to delete meter instance for CN10K platform. Signed-off-by: Sunil Kumar Kori Signed-off-by: Rakesh Kudurumalla --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/net/cnxk/cn10k_ethdev_mtr.c | 82 +++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev_mtr.c b/drivers/net/cnxk/cn10k_ethdev_mtr.c index 8916dc329f..6d48680c19 100644 --- a/drivers/net/cnxk/cn10k_ethdev_mtr.c +++ b/drivers/net/cnxk/cn10k_ethdev_mtr.c @@ -8,6 +8,10 @@ #define NIX_MTR_COUNT_MAX 73 /* 64(leaf) + 8(mid) + 1(top) */ #define NIX_MTR_COUNT_PER_FLOW 3 /* 1(leaf) + 1(mid) + 1(top) */ +static const enum roc_nix_bpf_level_flag lvl_map[] = {ROC_NIX_BPF_LEVEL_F_LEAF, + ROC_NIX_BPF_LEVEL_F_MID, + ROC_NIX_BPF_LEVEL_F_TOP}; + static struct rte_mtr_capabilities mtr_capa = { .n_max = NIX_MTR_COUNT_MAX, .n_shared_max = NIX_MTR_COUNT_PER_FLOW, @@ -470,6 +474,83 @@ cn10k_nix_mtr_create(struct rte_eth_dev *eth_dev, uint32_t mtr_id, return 0; } +static int +cn10k_nix_mtr_destroy(struct rte_eth_dev *eth_dev, uint32_t mtr_id, + struct rte_mtr_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_nix_bpf_objs profs = {0}; + struct cnxk_mtr *fm = &dev->mtr; + struct roc_nix *nix = &dev->nix; + struct cnxk_meter_node *mtr; + int rc = 0; + + mtr = nix_mtr_find(dev, mtr_id); + if (mtr == NULL) { + return -rte_mtr_error_set(error, ENOENT, + RTE_MTR_ERROR_TYPE_MTR_ID, &mtr_id, + "Meter id is invalid."); + } + + if (mtr->ref_cnt) { + return -rte_mtr_error_set(error, EADDRINUSE, + RTE_MTR_ERROR_TYPE_MTR_ID, &mtr_id, + "Meter id in use."); + } + + switch (lvl_map[mtr->level]) { + case ROC_NIX_BPF_LEVEL_F_LEAF: + if (mtr->is_next) { + rc = roc_nix_bpf_connect(nix, ROC_NIX_BPF_LEVEL_F_LEAF, + mtr_id, + ROC_NIX_BPF_ID_INVALID); + } + break; + case ROC_NIX_BPF_LEVEL_F_MID: + while (mtr->prev_cnt) { + rc = roc_nix_bpf_connect(nix, ROC_NIX_BPF_LEVEL_F_LEAF, + mtr->prev_id[mtr->prev_cnt], + ROC_NIX_BPF_ID_INVALID); + mtr->prev_cnt--; + } + if (mtr->is_next) { + rc = roc_nix_bpf_connect(nix, ROC_NIX_BPF_LEVEL_F_MID, + mtr_id, + ROC_NIX_BPF_ID_INVALID); + } + break; + case ROC_NIX_BPF_LEVEL_F_TOP: + while (mtr->prev_cnt) { + rc = roc_nix_bpf_connect(nix, ROC_NIX_BPF_LEVEL_F_MID, + mtr->prev_id[mtr->prev_cnt], + ROC_NIX_BPF_ID_INVALID); + mtr->prev_cnt--; + } + break; + default: + return -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_MTR_ID, NULL, + "Invalid meter level"); + } + + if (rc) + goto exit; + + profs.level = mtr->level; + profs.count = 1; + profs.ids[0] = mtr->bpf_id; + rc = roc_nix_bpf_free(nix, &profs, 1); + if (rc) + goto exit; + + TAILQ_REMOVE(fm, mtr, next); + plt_free(mtr->params.dscp_table); + plt_free(mtr); + +exit: + return rc; +} + const struct rte_mtr_ops nix_mtr_ops = { .capabilities_get = cn10k_nix_mtr_capabilities_get, .meter_profile_add = cn10k_nix_mtr_profile_add, @@ -478,6 +559,7 @@ const struct rte_mtr_ops nix_mtr_ops = { .meter_policy_add = cn10k_nix_mtr_policy_add, .meter_policy_delete = cn10k_nix_mtr_policy_delete, .create = cn10k_nix_mtr_create, + .destroy = cn10k_nix_mtr_destroy, }; int From patchwork Thu Sep 30 09:08:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100085 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F165DA0C41; Thu, 30 Sep 2021 11:11:57 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C55914119E; Thu, 30 Sep 2021 11:09:52 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 04CDD410F0 for ; Thu, 30 Sep 2021 11:09:48 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18U1KcVt001444 for ; Thu, 30 Sep 2021 02:09:48 -0700 DKIM-Signature: v=1; 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Thu, 30 Sep 2021 02:09:45 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 575583F7068; Thu, 30 Sep 2021 02:09:43 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rakesh Kudurumalla Date: Thu, 30 Sep 2021 14:38:41 +0530 Message-ID: <20210930090844.1059326-24-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: _Oo35N1NTOUSodZ9kKPbUyyxEXX8omNn X-Proofpoint-ORIG-GUID: _Oo35N1NTOUSodZ9kKPbUyyxEXX8omNn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 24/27] net/cnxk: support ops to enable/disable meter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement API to enable or disable meter instance for CN10K platform. Signed-off-by: Sunil Kumar Kori Signed-off-by: Rakesh Kudurumalla --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/net/cnxk/cn10k_ethdev_mtr.c | 60 +++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev_mtr.c b/drivers/net/cnxk/cn10k_ethdev_mtr.c index 6d48680c19..88153563c2 100644 --- a/drivers/net/cnxk/cn10k_ethdev_mtr.c +++ b/drivers/net/cnxk/cn10k_ethdev_mtr.c @@ -551,6 +551,64 @@ cn10k_nix_mtr_destroy(struct rte_eth_dev *eth_dev, uint32_t mtr_id, return rc; } +static int +cn10k_nix_mtr_enable(struct rte_eth_dev *eth_dev, uint32_t mtr_id, + struct rte_mtr_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_nix *nix = &dev->nix; + struct cnxk_meter_node *mtr; + struct roc_nix_rq *rq; + uint32_t i; + int rc = 0; + + mtr = nix_mtr_find(dev, mtr_id); + if (mtr == NULL) { + return -rte_mtr_error_set(error, ENOENT, + RTE_MTR_ERROR_TYPE_MTR_ID, NULL, + "Meter id is invalid."); + } + + if (mtr->level != 0) + return 0; + + for (i = 0; i < mtr->rq_num; i++) { + rq = &dev->rqs[mtr->rq_id[i]]; + rc |= roc_nix_bpf_ena_dis(nix, mtr->bpf_id, rq, true); + } + + return rc; +} + +static int +cn10k_nix_mtr_disable(struct rte_eth_dev *eth_dev, uint32_t mtr_id, + struct rte_mtr_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_nix *nix = &dev->nix; + struct cnxk_meter_node *mtr; + struct roc_nix_rq *rq; + uint32_t i; + int rc = 0; + + mtr = nix_mtr_find(dev, mtr_id); + if (mtr == NULL) { + return -rte_mtr_error_set(error, ENOENT, + RTE_MTR_ERROR_TYPE_MTR_ID, NULL, + "Meter id is invalid."); + } + + if (mtr->level != 0) + return 0; + + for (i = 0; i < mtr->rq_num; i++) { + rq = &dev->rqs[mtr->rq_id[i]]; + rc |= roc_nix_bpf_ena_dis(nix, mtr->bpf_id, rq, false); + } + + return rc; +} + const struct rte_mtr_ops nix_mtr_ops = { .capabilities_get = cn10k_nix_mtr_capabilities_get, .meter_profile_add = cn10k_nix_mtr_profile_add, @@ -560,6 +618,8 @@ const struct rte_mtr_ops nix_mtr_ops = { .meter_policy_delete = cn10k_nix_mtr_policy_delete, .create = cn10k_nix_mtr_create, .destroy = cn10k_nix_mtr_destroy, + .meter_enable = cn10k_nix_mtr_enable, + .meter_disable = cn10k_nix_mtr_disable, }; int From patchwork Thu Sep 30 09:08:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100086 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8AA8CA0C41; Thu, 30 Sep 2021 11:12:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EE152411A4; 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Thu, 30 Sep 2021 02:09:49 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:09:47 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:47 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id BBBD23F7067; Thu, 30 Sep 2021 02:09:45 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rakesh Kudurumalla Date: Thu, 30 Sep 2021 14:38:42 +0530 Message-ID: <20210930090844.1059326-25-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: HxE4ryvLjAlXzQav0DfHuDgyrJc5qQ63 X-Proofpoint-ORIG-GUID: HxE4ryvLjAlXzQav0DfHuDgyrJc5qQ63 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 25/27] net/cnxk: support ops to update precolor DSCP table X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement API to update DSCP table for pre-coloring for incoming packet per nixlf for CN10K platform. Signed-off-by: Sunil Kumar Kori Signed-off-by: Rakesh Kudurumalla --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/net/cnxk/cn10k_ethdev_mtr.c | 43 +++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev_mtr.c b/drivers/net/cnxk/cn10k_ethdev_mtr.c index 88153563c2..55485601fb 100644 --- a/drivers/net/cnxk/cn10k_ethdev_mtr.c +++ b/drivers/net/cnxk/cn10k_ethdev_mtr.c @@ -609,6 +609,48 @@ cn10k_nix_mtr_disable(struct rte_eth_dev *eth_dev, uint32_t mtr_id, return rc; } +static int +cn10k_nix_mtr_dscp_table_update(struct rte_eth_dev *eth_dev, uint32_t mtr_id, + enum rte_color *dscp_table, + struct rte_mtr_error *error) +{ + enum roc_nix_bpf_color nix_dscp_tbl[ROC_NIX_BPF_PRE_COLOR_MAX]; + enum roc_nix_bpf_color color_map[] = {ROC_NIX_BPF_COLOR_GREEN, + ROC_NIX_BPF_COLOR_YELLOW, + ROC_NIX_BPF_COLOR_RED}; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + uint8_t lvl_flag = ROC_NIX_BPF_LEVEL_F_LEAF; + struct roc_nix_bpf_precolor table; + struct roc_nix *nix = &dev->nix; + int rc, i; + + if (!dscp_table) { + for (i = 0; i < ROC_NIX_BPF_PRE_COLOR_MAX; i++) + nix_dscp_tbl[i] = ROC_NIX_BPF_COLOR_GREEN; + } else { + for (i = 0; i < ROC_NIX_BPF_PRE_COLOR_MAX; i++) + nix_dscp_tbl[i] = color_map[dscp_table[i]]; + } + + table.count = ROC_NIX_BPF_PRE_COLOR_MAX; + table.mode = ROC_NIX_BPF_PC_MODE_DSCP_OUTER; + for (i = 0; i < ROC_NIX_BPF_PRE_COLOR_MAX; i++) + table.color[i] = nix_dscp_tbl[i]; + + rc = roc_nix_bpf_pre_color_tbl_setup(nix, mtr_id, lvl_flag, &table); + if (rc) { + rte_mtr_error_set(error, rc, RTE_MTR_ERROR_TYPE_UNSPECIFIED, + NULL, NULL); + goto exit; + } + + for (i = 0; i < ROC_NIX_BPF_PRE_COLOR_MAX; i++) + dev->precolor_tbl[i] = nix_dscp_tbl[i]; + +exit: + return rc; +} + const struct rte_mtr_ops nix_mtr_ops = { .capabilities_get = cn10k_nix_mtr_capabilities_get, .meter_profile_add = cn10k_nix_mtr_profile_add, @@ -620,6 +662,7 @@ const struct rte_mtr_ops nix_mtr_ops = { .destroy = cn10k_nix_mtr_destroy, .meter_enable = cn10k_nix_mtr_enable, .meter_disable = cn10k_nix_mtr_disable, + .meter_dscp_table_update = cn10k_nix_mtr_dscp_table_update, }; int From patchwork Thu Sep 30 09:08:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100087 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9495EA0C41; Thu, 30 Sep 2021 11:12:14 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 61E57411A0; Thu, 30 Sep 2021 11:10:01 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 749A4411A0 for ; Thu, 30 Sep 2021 11:09:53 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18U1KcVx001444 for ; Thu, 30 Sep 2021 02:09:52 -0700 DKIM-Signature: v=1; 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Thu, 30 Sep 2021 02:09:50 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 2C1573F7068; Thu, 30 Sep 2021 02:09:47 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rakesh Kudurumalla Date: Thu, 30 Sep 2021 14:38:43 +0530 Message-ID: <20210930090844.1059326-26-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: zMSkoMhpcxavQYZDGKbdC2aEtLFdZWvU X-Proofpoint-ORIG-GUID: zMSkoMhpcxavQYZDGKbdC2aEtLFdZWvU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 26/27] net/cnxk: support ops to read/update meter stats X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Implement API to read and update stats corresponding to given meter instance for CN10K platform. Signed-off-by: Sunil Kumar Kori Signed-off-by: Rakesh Kudurumalla --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated drivers/net/cnxk/cn10k_ethdev_mtr.c | 141 ++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev_mtr.c b/drivers/net/cnxk/cn10k_ethdev_mtr.c index 55485601fb..62f48c534f 100644 --- a/drivers/net/cnxk/cn10k_ethdev_mtr.c +++ b/drivers/net/cnxk/cn10k_ethdev_mtr.c @@ -8,6 +8,21 @@ #define NIX_MTR_COUNT_MAX 73 /* 64(leaf) + 8(mid) + 1(top) */ #define NIX_MTR_COUNT_PER_FLOW 3 /* 1(leaf) + 1(mid) + 1(top) */ +#define NIX_BPF_STATS_MASK_ALL \ + { \ + ROC_NIX_BPF_GREEN_PKT_F_PASS | ROC_NIX_BPF_GREEN_OCTS_F_PASS | \ + ROC_NIX_BPF_GREEN_PKT_F_DROP | \ + ROC_NIX_BPF_GREEN_OCTS_F_DROP | \ + ROC_NIX_BPF_YELLOW_PKT_F_PASS | \ + ROC_NIX_BPF_YELLOW_OCTS_F_PASS | \ + ROC_NIX_BPF_YELLOW_PKT_F_DROP | \ + ROC_NIX_BPF_YELLOW_OCTS_F_DROP | \ + ROC_NIX_BPF_RED_PKT_F_PASS | \ + ROC_NIX_BPF_RED_OCTS_F_PASS | \ + ROC_NIX_BPF_RED_PKT_F_DROP | \ + ROC_NIX_BPF_RED_OCTS_F_DROP \ + } + static const enum roc_nix_bpf_level_flag lvl_map[] = {ROC_NIX_BPF_LEVEL_F_LEAF, ROC_NIX_BPF_LEVEL_F_MID, ROC_NIX_BPF_LEVEL_F_TOP}; @@ -651,6 +666,130 @@ cn10k_nix_mtr_dscp_table_update(struct rte_eth_dev *eth_dev, uint32_t mtr_id, return rc; } +static int +cn10k_nix_mtr_stats_update(struct rte_eth_dev *eth_dev, uint32_t mtr_id, + uint64_t stats_mask, struct rte_mtr_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_meter_node *mtr; + + if (!stats_mask) + return -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_MTR_PARAMS, NULL, + "no bit is set to stats mask"); + + mtr = nix_mtr_find(dev, mtr_id); + if (mtr == NULL) { + return -rte_mtr_error_set(error, ENOENT, + RTE_MTR_ERROR_TYPE_MTR_ID, NULL, + "Meter object not found"); + } + + mtr->params.stats_mask = stats_mask; + return 0; +} + +static int +cn10k_nix_mtr_stats_read(struct rte_eth_dev *eth_dev, uint32_t mtr_id, + struct rte_mtr_stats *stats, uint64_t *stats_mask, + int clear, struct rte_mtr_error *error) +{ + uint8_t yellow_pkt_pass, yellow_octs_pass, yellow_pkt_drop; + uint8_t green_octs_drop, yellow_octs_drop, red_octs_drop; + uint8_t green_pkt_pass, green_octs_pass, green_pkt_drop; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + uint8_t red_pkt_pass, red_octs_pass, red_pkt_drop; + uint64_t bpf_stats[ROC_NIX_BPF_STATS_MAX] = {0}; + uint8_t lvl_flag = ROC_NIX_BPF_LEVEL_F_LEAF; + uint64_t mask = NIX_BPF_STATS_MASK_ALL; + struct roc_nix *nix = &dev->nix; + struct cnxk_meter_node *mtr; + int rc; + + if (!stats) + return -rte_mtr_error_set(error, EINVAL, + RTE_MTR_ERROR_TYPE_MTR_PARAMS, NULL, + "stats pointer is NULL"); + + mtr = nix_mtr_find(dev, mtr_id); + if (mtr == NULL) { + return -rte_mtr_error_set(error, ENOENT, + RTE_MTR_ERROR_TYPE_MTR_ID, NULL, + "Meter object not found"); + } + + rc = roc_nix_bpf_stats_read(nix, mtr->bpf_id, mask, lvl_flag, + bpf_stats); + if (rc) { + rte_mtr_error_set(error, rc, RTE_MTR_ERROR_TYPE_UNSPECIFIED, + NULL, NULL); + goto exit; + } + + green_pkt_pass = roc_nix_bpf_stats_to_idx(ROC_NIX_BPF_GREEN_PKT_F_PASS); + green_octs_pass = + roc_nix_bpf_stats_to_idx(ROC_NIX_BPF_GREEN_OCTS_F_PASS); + green_pkt_drop = roc_nix_bpf_stats_to_idx(ROC_NIX_BPF_GREEN_PKT_F_DROP); + green_octs_drop = + roc_nix_bpf_stats_to_idx(ROC_NIX_BPF_GREEN_OCTS_F_DROP); + yellow_pkt_pass = + roc_nix_bpf_stats_to_idx(ROC_NIX_BPF_YELLOW_PKT_F_PASS); + yellow_octs_pass = + roc_nix_bpf_stats_to_idx(ROC_NIX_BPF_YELLOW_OCTS_F_PASS); + yellow_pkt_drop = + roc_nix_bpf_stats_to_idx(ROC_NIX_BPF_YELLOW_PKT_F_DROP); + yellow_octs_drop = + roc_nix_bpf_stats_to_idx(ROC_NIX_BPF_YELLOW_OCTS_F_DROP); + red_pkt_pass = roc_nix_bpf_stats_to_idx(ROC_NIX_BPF_RED_PKT_F_PASS); + red_octs_pass = roc_nix_bpf_stats_to_idx(ROC_NIX_BPF_RED_OCTS_F_PASS); + red_pkt_drop = roc_nix_bpf_stats_to_idx(ROC_NIX_BPF_RED_PKT_F_DROP); + red_octs_drop = roc_nix_bpf_stats_to_idx(ROC_NIX_BPF_RED_OCTS_F_DROP); + + if (mtr->params.stats_mask & RTE_MTR_STATS_N_PKTS_GREEN) + stats->n_pkts[RTE_COLOR_GREEN] = bpf_stats[green_pkt_pass]; + + if (mtr->params.stats_mask & RTE_MTR_STATS_N_PKTS_YELLOW) + stats->n_pkts[RTE_COLOR_YELLOW] = bpf_stats[yellow_pkt_pass]; + + if (mtr->params.stats_mask & RTE_MTR_STATS_N_PKTS_RED) + stats->n_pkts[RTE_COLOR_RED] = bpf_stats[red_pkt_pass]; + + if (mtr->params.stats_mask & RTE_MTR_STATS_N_BYTES_GREEN) + stats->n_bytes[RTE_COLOR_GREEN] = bpf_stats[green_octs_pass]; + + if (mtr->params.stats_mask & RTE_MTR_STATS_N_BYTES_YELLOW) + stats->n_bytes[RTE_COLOR_YELLOW] = bpf_stats[yellow_octs_pass]; + + if (mtr->params.stats_mask & RTE_MTR_STATS_N_BYTES_RED) + stats->n_bytes[RTE_COLOR_RED] = bpf_stats[red_octs_pass]; + + if (mtr->params.stats_mask & RTE_MTR_STATS_N_PKTS_DROPPED) + stats->n_pkts_dropped = bpf_stats[green_pkt_drop] + + bpf_stats[yellow_pkt_drop] + + bpf_stats[red_pkt_drop]; + + if (mtr->params.stats_mask & RTE_MTR_STATS_N_BYTES_DROPPED) + stats->n_bytes_dropped = bpf_stats[green_octs_drop] + + bpf_stats[yellow_octs_drop] + + bpf_stats[red_octs_drop]; + + if (stats_mask) + *stats_mask = mtr->params.stats_mask; + + if (clear) { + rc = roc_nix_bpf_stats_reset(nix, mtr->bpf_id, mask, lvl_flag); + if (rc) { + rte_mtr_error_set(error, rc, + RTE_MTR_ERROR_TYPE_UNSPECIFIED, NULL, + NULL); + goto exit; + } + } + +exit: + return rc; +} + const struct rte_mtr_ops nix_mtr_ops = { .capabilities_get = cn10k_nix_mtr_capabilities_get, .meter_profile_add = cn10k_nix_mtr_profile_add, @@ -663,6 +802,8 @@ const struct rte_mtr_ops nix_mtr_ops = { .meter_enable = cn10k_nix_mtr_enable, .meter_disable = cn10k_nix_mtr_disable, .meter_dscp_table_update = cn10k_nix_mtr_dscp_table_update, + .stats_update = cn10k_nix_mtr_stats_update, + .stats_read = cn10k_nix_mtr_stats_read, }; int From patchwork Thu Sep 30 09:08:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kumar Kori X-Patchwork-Id: 100088 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 16644A0C41; Thu, 30 Sep 2021 11:12:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 852F4410FA; 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Thu, 30 Sep 2021 02:09:54 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 02:09:52 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 02:09:52 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 932043F7067; Thu, 30 Sep 2021 02:09:50 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rakesh Kudurumalla Date: Thu, 30 Sep 2021 14:38:44 +0530 Message-ID: <20210930090844.1059326-27-skori@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930090844.1059326-1-skori@marvell.com> References: <20210927082223.757436-1-skori@marvell.com> <20210930090844.1059326-1-skori@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: StV7Ypu2SSqOQ_RuXlu1MH5LedYPrc-q X-Proofpoint-ORIG-GUID: StV7Ypu2SSqOQ_RuXlu1MH5LedYPrc-q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_02,2021-09-29_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 27/27] net/cnxk: support meter action to flow create X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Meters are configured per flow using rte_flow_create API. Implement support for meter action applied on the flow. Signed-off-by: Sunil Kumar Kori Signed-off-by: Rakesh Kudurumalla --- v3: - Rebase support on latest DPDK - Handled multilevel chaining for tree hierarchy - Fix naming convention v2: - Rebase support on latest DPDK - Handled multilevel chaining for linear hierarchy - Review comments incorporated doc/guides/nics/features/cnxk.ini | 1 + doc/guides/nics/features/cnxk_vf.ini | 1 + drivers/net/cnxk/cn10k_ethdev_mtr.c | 514 +++++++++++++++++++++++++++ drivers/net/cnxk/cn10k_rte_flow.c | 171 ++++++++- drivers/net/cnxk/cnxk_ethdev.h | 18 + drivers/net/cnxk/cnxk_rte_flow.c | 4 + 6 files changed, 708 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini index 5d456257bd..7bbce7dafc 100644 --- a/doc/guides/nics/features/cnxk.ini +++ b/doc/guides/nics/features/cnxk.ini @@ -78,6 +78,7 @@ count = Y drop = Y flag = Y mark = Y +meter = Y of_pop_vlan = Y of_push_vlan = Y of_set_vlan_pcp = Y diff --git a/doc/guides/nics/features/cnxk_vf.ini b/doc/guides/nics/features/cnxk_vf.ini index 7b4299f0be..89802a27f9 100644 --- a/doc/guides/nics/features/cnxk_vf.ini +++ b/doc/guides/nics/features/cnxk_vf.ini @@ -70,6 +70,7 @@ count = Y drop = Y flag = Y mark = Y +meter = Y of_pop_vlan = Y of_push_vlan = Y of_set_vlan_pcp = Y diff --git a/drivers/net/cnxk/cn10k_ethdev_mtr.c b/drivers/net/cnxk/cn10k_ethdev_mtr.c index 62f48c534f..0b98489dee 100644 --- a/drivers/net/cnxk/cn10k_ethdev_mtr.c +++ b/drivers/net/cnxk/cn10k_ethdev_mtr.c @@ -814,3 +814,517 @@ cn10k_nix_mtr_ops_get(struct rte_eth_dev *dev, void *ops) *(const void **)ops = &nix_mtr_ops; return 0; } + +int +nix_mtr_validate(struct rte_eth_dev *eth_dev, uint32_t id) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_mtr_profile_node *profile; + struct cnxk_mtr_policy_node *policy; + struct cnxk_meter_node *mtr; + + mtr = nix_mtr_find(dev, id); + if (mtr == NULL) + return -EINVAL; + + profile = nix_mtr_profile_find(dev, mtr->params.meter_profile_id); + if (profile == NULL) + return -EINVAL; + + policy = nix_mtr_policy_find(dev, mtr->params.meter_policy_id); + if (policy == NULL) + return -EINVAL; + + return 0; +} + +int +nix_mtr_policy_act_get(struct rte_eth_dev *eth_dev, uint32_t id, + struct cnxk_mtr_policy_node **policy_act) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_mtr_policy_node *policy; + struct cnxk_meter_node *mtr; + + mtr = nix_mtr_find(dev, id); + if (mtr == NULL) + return -EINVAL; + + policy = nix_mtr_policy_find(dev, mtr->params.meter_policy_id); + if (policy == NULL) + return -EINVAL; + + *policy_act = policy; + + return 0; +} + +int +nix_mtr_rq_update(struct rte_eth_dev *eth_dev, uint32_t id, uint32_t queue_num, + const uint16_t *queue) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_meter_node *mtr; + uint32_t i; + + mtr = nix_mtr_find(dev, id); + if (mtr == NULL) + return -EINVAL; + + mtr->rq_id = plt_zmalloc(queue_num * sizeof(uint32_t), ROC_ALIGN); + if (mtr->rq_id == NULL) + return -ENOMEM; + + mtr->rq_num = queue_num; + for (i = 0; i < queue_num; i++) + mtr->rq_id[i] = queue[i]; + + return 0; +} + +int +nix_mtr_chain_reset(struct rte_eth_dev *eth_dev, uint32_t cur_id) +{ + struct cnxk_meter_node *mtr[ROC_NIX_BPF_LEVEL_MAX] = {0}; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + uint32_t mtr_id = cur_id; + int i = 0, j = 0; + + for (i = 0; i < ROC_NIX_BPF_LEVEL_MAX; i++) { + mtr[i] = nix_mtr_find(dev, mtr_id); + if (mtr[i]) + mtr_id = mtr[i]->next_id; + } + for (i = 0; i < ROC_NIX_BPF_LEVEL_MAX; i++) { + if (mtr[i]) { + for (j = 0; j < MAX_PRV_MTR_NODES; j++) + mtr[i]->prev_id[i] = ROC_NIX_BPF_ID_INVALID; + mtr[i]->level = ROC_NIX_BPF_LEVEL_IDX_INVALID; + mtr[i]->next_id = ROC_NIX_BPF_ID_INVALID; + mtr[i]->is_prev = false; + mtr[i]->is_next = false; + mtr[i]->prev_cnt = 0; + } + } + return 0; +} + +int +nix_mtr_chain_update(struct rte_eth_dev *eth_dev, uint32_t cur_id, + uint32_t prev_id, uint32_t next_id) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_meter_node *mtr; + + mtr = nix_mtr_find(dev, cur_id); + if (mtr == NULL) + return -EINVAL; + + switch (lvl_map[mtr->level]) { + case ROC_NIX_BPF_LEVEL_F_LEAF: + mtr->prev_id[mtr->prev_cnt] = ROC_NIX_BPF_ID_INVALID; + mtr->next_id = next_id; + mtr->is_prev = false; + mtr->is_next = true; + break; + case ROC_NIX_BPF_LEVEL_F_MID: + mtr->prev_id[mtr->prev_cnt] = prev_id; + mtr->next_id = next_id; + mtr->is_prev = true; + mtr->is_next = true; + break; + case ROC_NIX_BPF_LEVEL_F_TOP: + mtr->prev_id[mtr->prev_cnt] = prev_id; + mtr->next_id = ROC_NIX_BPF_ID_INVALID; + mtr->is_prev = true; + mtr->is_next = false; + break; + default: + plt_err("Invalid meter level"); + return -EINVAL; + } + + return 0; +} + +struct cnxk_meter_node * +nix_get_mtr(struct rte_eth_dev *eth_dev, uint32_t id) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_meter_node *mtr; + + mtr = nix_mtr_find(dev, id); + if (mtr == NULL) + return NULL; + + return mtr; +} + +int +nix_mtr_level_update(struct rte_eth_dev *eth_dev, uint32_t id, uint32_t level) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_meter_node *mtr; + + mtr = nix_mtr_find(dev, id); + if (mtr == NULL) + return -EINVAL; + + mtr->level = level; + return 0; +} + +static void +nix_mtr_config_map(struct cnxk_meter_node *mtr, struct roc_nix_bpf_cfg *cfg) +{ + enum roc_nix_bpf_algo alg_map[] = { + ROC_NIX_BPF_ALGO_NONE, ROC_NIX_BPF_ALGO_2697, + ROC_NIX_BPF_ALGO_2698, ROC_NIX_BPF_ALGO_4115}; + struct cnxk_mtr_profile_node *profile = mtr->profile; + struct cnxk_mtr_policy_node *policy = mtr->policy; + + cfg->alg = alg_map[profile->profile.alg]; + cfg->lmode = profile->profile.packet_mode; + + switch (cfg->alg) { + case ROC_NIX_BPF_ALGO_2697: + cfg->algo2697.cir = profile->profile.srtcm_rfc2697.cir * 8; + cfg->algo2697.cbs = profile->profile.srtcm_rfc2697.cbs; + cfg->algo2697.ebs = profile->profile.srtcm_rfc2697.ebs; + break; + case ROC_NIX_BPF_ALGO_2698: + cfg->algo2698.cir = profile->profile.trtcm_rfc2698.cir * 8; + cfg->algo2698.pir = profile->profile.trtcm_rfc2698.pir * 8; + cfg->algo2698.cbs = profile->profile.trtcm_rfc2698.cbs; + cfg->algo2698.pbs = profile->profile.trtcm_rfc2698.pbs; + break; + case ROC_NIX_BPF_ALGO_4115: + cfg->algo4115.cir = profile->profile.trtcm_rfc4115.cir * 8; + cfg->algo4115.eir = profile->profile.trtcm_rfc4115.eir * 8; + cfg->algo4115.cbs = profile->profile.trtcm_rfc4115.cbs; + cfg->algo4115.ebs = profile->profile.trtcm_rfc4115.ebs; + break; + default: + break; + } + + cfg->action[ROC_NIX_BPF_COLOR_GREEN] = ROC_NIX_BPF_ACTION_PASS; + cfg->action[ROC_NIX_BPF_COLOR_YELLOW] = ROC_NIX_BPF_ACTION_PASS; + cfg->action[ROC_NIX_BPF_COLOR_RED] = ROC_NIX_BPF_ACTION_PASS; + + if (policy->actions[RTE_COLOR_GREEN].action_fate == + RTE_FLOW_ACTION_TYPE_DROP) + cfg->action[ROC_NIX_BPF_COLOR_GREEN] = ROC_NIX_BPF_ACTION_DROP; + + if (policy->actions[RTE_COLOR_YELLOW].action_fate == + RTE_FLOW_ACTION_TYPE_DROP) + cfg->action[ROC_NIX_BPF_COLOR_YELLOW] = ROC_NIX_BPF_ACTION_DROP; + + if (policy->actions[RTE_COLOR_RED].action_fate == + RTE_FLOW_ACTION_TYPE_DROP) + cfg->action[ROC_NIX_BPF_COLOR_RED] = ROC_NIX_BPF_ACTION_DROP; +} + +static void +nix_dscp_table_map(struct cnxk_meter_node *mtr, + struct roc_nix_bpf_precolor *tbl) +{ + enum roc_nix_bpf_color color_map[] = {ROC_NIX_BPF_COLOR_GREEN, + ROC_NIX_BPF_COLOR_YELLOW, + ROC_NIX_BPF_COLOR_RED}; + int i; + + tbl->count = ROC_NIX_BPF_PRE_COLOR_MAX; + tbl->mode = ROC_NIX_BPF_PC_MODE_DSCP_OUTER; + + for (i = 0; i < ROC_NIX_BPF_PRE_COLOR_MAX; i++) + tbl->color[i] = ROC_NIX_BPF_COLOR_GREEN; + + if (mtr->params.dscp_table) { + for (i = 0; i < ROC_NIX_BPF_PRE_COLOR_MAX; i++) + tbl->color[i] = color_map[mtr->params.dscp_table[i]]; + } +} + +int +nix_mtr_connect(struct rte_eth_dev *eth_dev, uint32_t id) +{ + enum roc_nix_bpf_level_flag lvl_flag = ROC_NIX_BPF_LEVEL_IDX_INVALID; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_meter_node *base_mtr, *next_mtr; + struct roc_nix *nix = &dev->nix; + uint32_t cur_mtr_id = id; + int rc, i; + + for (i = 0; i < ROC_NIX_BPF_LEVEL_MAX; i++) { + base_mtr = nix_mtr_find(dev, cur_mtr_id); + if (base_mtr) { + if (base_mtr->level == 0) + lvl_flag = ROC_NIX_BPF_LEVEL_F_LEAF; + if (base_mtr->level == 1) + lvl_flag = ROC_NIX_BPF_LEVEL_F_MID; + + if (base_mtr->is_next) { + next_mtr = nix_mtr_find(dev, base_mtr->next_id); + if (next_mtr) { + if (!base_mtr->is_used) { + rc = roc_nix_bpf_connect(nix, + lvl_flag, + base_mtr->bpf_id, + next_mtr->bpf_id); + if (rc) + return rc; + } + } + cur_mtr_id = base_mtr->next_id; + } + } + } + return 0; +} + +int +nix_mtr_configure(struct rte_eth_dev *eth_dev, uint32_t id) +{ + struct cnxk_meter_node *mtr[ROC_NIX_BPF_LEVEL_MAX] = {0}; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_nix_bpf_objs profs[ROC_NIX_BPF_LEVEL_MAX]; + uint8_t idx0 = ROC_NIX_BPF_LEVEL_IDX_INVALID; + uint8_t idx1 = ROC_NIX_BPF_LEVEL_IDX_INVALID; + uint8_t idx2 = ROC_NIX_BPF_LEVEL_IDX_INVALID; + uint16_t per_lvl_cnt[ROC_NIX_BPF_LEVEL_MAX]; + int num_mtr[ROC_NIX_BPF_LEVEL_MAX] = {0}; + struct roc_nix *nix = &dev->nix; + struct roc_nix_bpf_precolor tbl; + struct roc_nix_bpf_cfg cfg; + struct roc_nix_rq *rq; + uint8_t lvl_mask; + uint32_t i; + uint32_t j; + int rc; + + mtr[0] = nix_mtr_find(dev, id); + if (mtr[0] == NULL) + return -EINVAL; + + num_mtr[0] = 1; + idx0 = roc_nix_bpf_level_to_idx(lvl_map[mtr[0]->level]); + if (idx0 == ROC_NIX_BPF_LEVEL_IDX_INVALID) + return -EINVAL; + + lvl_mask = ROC_NIX_BPF_LEVEL_F_LEAF; + if (mtr[0]->is_used) + per_lvl_cnt[idx0] = 0; + else + per_lvl_cnt[idx0] = 1; + + if (mtr[0]->is_next) { + mtr[1] = nix_mtr_find(dev, mtr[0]->next_id); + if (mtr[1] == NULL) + return -EINVAL; + num_mtr[1] = 1; + idx1 = roc_nix_bpf_level_to_idx(lvl_map[mtr[1]->level]); + if (idx1 == ROC_NIX_BPF_LEVEL_IDX_INVALID) + return -EINVAL; + + lvl_mask |= ROC_NIX_BPF_LEVEL_F_MID; + if (mtr[1]->is_used) + per_lvl_cnt[idx1] = 0; + else + per_lvl_cnt[idx1] = 1; + } + + if (mtr[1] && mtr[1]->is_next) { + mtr[2] = nix_mtr_find(dev, mtr[1]->next_id); + if (mtr[2] == NULL) + return -EINVAL; + + num_mtr[2] = 1; + idx2 = roc_nix_bpf_level_to_idx(lvl_map[mtr[2]->level]); + if (idx2 == ROC_NIX_BPF_LEVEL_IDX_INVALID) + return -EINVAL; + + lvl_mask |= ROC_NIX_BPF_LEVEL_F_TOP; + if (mtr[2]->is_used) + per_lvl_cnt[idx2] = 0; + else + per_lvl_cnt[idx2] = 1; + } + + rc = roc_nix_bpf_alloc(nix, lvl_mask, per_lvl_cnt, profs); + if (rc) + return rc; + if (mtr[0]->bpf_id == ROC_NIX_BPF_ID_INVALID) + mtr[0]->bpf_id = profs[idx0].ids[0]; + + if (num_mtr[0]) + if (mtr[0]->is_next && idx1 != ROC_NIX_BPF_LEVEL_IDX_INVALID) + if (mtr[1]->bpf_id == ROC_NIX_BPF_ID_INVALID) + mtr[1]->bpf_id = profs[idx1].ids[0]; + + if (num_mtr[1]) + if (mtr[1]->is_next && idx2 != ROC_NIX_BPF_LEVEL_IDX_INVALID) + if (mtr[2]->bpf_id == ROC_NIX_BPF_ID_INVALID) + mtr[2]->bpf_id = profs[idx2].ids[0]; + + for (i = 0; i < ROC_NIX_BPF_LEVEL_MAX; i++) { + if (num_mtr[i]) { + if (!mtr[i]->is_used) { + memset(&cfg, 0, sizeof(struct roc_nix_bpf_cfg)); + nix_mtr_config_map(mtr[i], &cfg); + rc = roc_nix_bpf_config(nix, mtr[i]->bpf_id, + lvl_map[mtr[i]->level], + &cfg); + + memset(&tbl, 0, + sizeof(struct roc_nix_bpf_precolor)); + nix_dscp_table_map(mtr[i], &tbl); + rc = roc_nix_bpf_pre_color_tbl_setup(nix, + mtr[i]->bpf_id, lvl_map[mtr[i]->level], + &tbl); + + if (mtr[i]->params.meter_enable) { + for (j = 0; j < mtr[i]->rq_num; j++) { + rq = &dev->rqs[mtr[i]->rq_id + [j]]; + rc = roc_nix_bpf_ena_dis(nix, + mtr[i]->bpf_id, rq, + true); + } + } + } + } + } + + return rc; +} + +int +nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id, + uint32_t *prev_id, uint32_t *next_id, + struct cnxk_mtr_policy_node *policy, + int *tree_level) +{ + uint32_t action_fate_red = policy->actions[RTE_COLOR_RED].action_fate; + uint32_t action_fate_green = + policy->actions[RTE_COLOR_GREEN].action_fate; + uint32_t action_fate_yellow = + policy->actions[RTE_COLOR_YELLOW].action_fate; + uint32_t cur_mtr_id = *next_id; + uint32_t next_mtr_id = 0xffff; + uint32_t prev_mtr_id = 0xffff; + struct cnxk_meter_node *mtr; + + if (action_fate_green == RTE_FLOW_ACTION_TYPE_METER) + next_mtr_id = policy->actions[RTE_COLOR_GREEN].mtr_id; + + if (action_fate_yellow == RTE_FLOW_ACTION_TYPE_METER) + next_mtr_id = policy->actions[RTE_COLOR_YELLOW].mtr_id; + + if (action_fate_red == RTE_FLOW_ACTION_TYPE_METER) + next_mtr_id = policy->actions[RTE_COLOR_RED].mtr_id; + + if (next_mtr_id != 0xffff) { + switch (*tree_level) { + case 0: + mtr = nix_get_mtr(eth_dev, cur_mtr_id); + if (mtr->level == ROC_NIX_BPF_LEVEL_IDX_INVALID) { + nix_mtr_level_update(eth_dev, cur_mtr_id, 0); + nix_mtr_chain_update(eth_dev, cur_mtr_id, -1, + next_mtr_id); + } else { + if (mtr->level == 0) + mtr->is_used = true; + else + return -EINVAL; + } + (*tree_level)++; + *next_id = next_mtr_id; + break; + case 1: + mtr = nix_get_mtr(eth_dev, cur_mtr_id); + if (mtr->level == ROC_NIX_BPF_LEVEL_IDX_INVALID) { + nix_mtr_level_update(eth_dev, cur_mtr_id, 1); + prev_mtr_id = id; + nix_mtr_chain_update(eth_dev, cur_mtr_id, + prev_mtr_id, next_mtr_id); + } else { + if (mtr->level == 1) { + mtr->prev_cnt++; + prev_mtr_id = id; + nix_mtr_chain_update(eth_dev, + cur_mtr_id, prev_mtr_id, + next_mtr_id); + + mtr->is_used = true; + } else { + return -EINVAL; + } + } + (*tree_level)++; + *next_id = next_mtr_id; + *prev_id = cur_mtr_id; + break; + case 2: + nix_mtr_chain_reset(eth_dev, id); + return -EINVAL; + } + } else { + switch (*tree_level) { + case 0: + mtr = nix_get_mtr(eth_dev, cur_mtr_id); + if (mtr->level == ROC_NIX_BPF_LEVEL_IDX_INVALID) { + nix_mtr_level_update(eth_dev, cur_mtr_id, 0); + } else { + if (mtr->level == 0) + mtr->is_used = true; + else + return -EINVAL; + } + break; + case 1: + mtr = nix_get_mtr(eth_dev, cur_mtr_id); + if (mtr->level == ROC_NIX_BPF_LEVEL_IDX_INVALID) { + nix_mtr_level_update(eth_dev, cur_mtr_id, 1); + prev_mtr_id = id; + nix_mtr_chain_update(eth_dev, cur_mtr_id, + prev_mtr_id, -1); + } else { + if (mtr->level == 1) { + mtr->prev_cnt++; + prev_mtr_id = id; + nix_mtr_chain_update(eth_dev, + cur_mtr_id, + prev_mtr_id, -1); + mtr->is_used = true; + } else { + return -EINVAL; + } + } + break; + case 2: + mtr = nix_get_mtr(eth_dev, cur_mtr_id); + if (mtr->level == ROC_NIX_BPF_LEVEL_IDX_INVALID) { + nix_mtr_level_update(eth_dev, cur_mtr_id, 2); + prev_mtr_id = *prev_id; + nix_mtr_chain_update(eth_dev, cur_mtr_id, + prev_mtr_id, -1); + } else { + if (mtr->level == 2) { + mtr->prev_cnt++; + prev_mtr_id = *prev_id; + nix_mtr_chain_update(eth_dev, + cur_mtr_id, + prev_mtr_id, -1); + mtr->is_used = true; + } else { + return -EINVAL; + } + } + break; + } + *next_id = 0xffff; + } + + return 0; +} diff --git a/drivers/net/cnxk/cn10k_rte_flow.c b/drivers/net/cnxk/cn10k_rte_flow.c index b04de6a7e6..8fa0856c77 100644 --- a/drivers/net/cnxk/cn10k_rte_flow.c +++ b/drivers/net/cnxk/cn10k_rte_flow.c @@ -6,6 +6,113 @@ #include "cn10k_ethdev.h" #include "cn10k_rx.h" +static int +cn10k_mtr_connect(struct rte_eth_dev *eth_dev, uint32_t mtr_id) +{ + return nix_mtr_connect(eth_dev, mtr_id); +} + +static int +cn10k_mtr_configure(struct rte_eth_dev *eth_dev, + const struct rte_flow_action actions[]) +{ + uint32_t mtr_id = 0xffff, prev_mtr_id = 0xffff, next_mtr_id = 0xffff; + const struct rte_flow_action_meter *mtr_conf; + const struct rte_flow_action_queue *q_conf; + const struct rte_flow_action_rss *rss_conf; + struct cnxk_mtr_policy_node *policy; + bool is_mtr_act = false; + int tree_level = 0; + int rc = -EINVAL, i; + + for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) { + if (actions[i].type == RTE_FLOW_ACTION_TYPE_METER) { + mtr_conf = (const struct rte_flow_action_meter + *)(actions->conf); + mtr_id = mtr_conf->mtr_id; + is_mtr_act = true; + } + if (actions[i].type == RTE_FLOW_ACTION_TYPE_QUEUE) { + q_conf = (const struct rte_flow_action_queue + *)(actions->conf); + if (is_mtr_act) + nix_mtr_rq_update(eth_dev, mtr_id, 1, + &q_conf->index); + } + if (actions[i].type == RTE_FLOW_ACTION_TYPE_RSS) { + rss_conf = (const struct rte_flow_action_rss + *)(actions->conf); + if (is_mtr_act) + nix_mtr_rq_update(eth_dev, mtr_id, + rss_conf->queue_num, + rss_conf->queue); + } + } + + if (!is_mtr_act) + return rc; + + prev_mtr_id = mtr_id; + next_mtr_id = mtr_id; + while (next_mtr_id != 0xffff) { + rc = nix_mtr_validate(eth_dev, next_mtr_id); + if (rc) + return rc; + + rc = nix_mtr_policy_act_get(eth_dev, next_mtr_id, &policy); + if (rc) + return rc; + + rc = nix_mtr_color_action_validate(eth_dev, mtr_id, + &prev_mtr_id, &next_mtr_id, + policy, &tree_level); + if (rc) + return rc; + } + + return nix_mtr_configure(eth_dev, mtr_id); +} + +static int +cn10k_rss_action_validate(struct rte_eth_dev *eth_dev, + const struct rte_flow_attr *attr, + const struct rte_flow_action *act) +{ + const struct rte_flow_action_rss *rss; + + if (act == NULL) + return -EINVAL; + + rss = (const struct rte_flow_action_rss *)act->conf; + + if (attr->egress) { + plt_err("No support of RSS in egress"); + return -EINVAL; + } + + if (eth_dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) { + plt_err("multi-queue mode is disabled"); + return -ENOTSUP; + } + + if (!rss || !rss->queue_num) { + plt_err("no valid queues"); + return -EINVAL; + } + + if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT) { + plt_err("non-default RSS hash functions are not supported"); + return -ENOTSUP; + } + + if (rss->key_len && rss->key_len > ROC_NIX_RSS_KEY_LEN) { + plt_err("RSS hash key too large"); + return -ENOTSUP; + } + + return 0; +} + struct rte_flow * cn10k_flow_create(struct rte_eth_dev *eth_dev, const struct rte_flow_attr *attr, const struct rte_flow_item pattern[], @@ -13,13 +120,75 @@ cn10k_flow_create(struct rte_eth_dev *eth_dev, const struct rte_flow_attr *attr, struct rte_flow_error *error) { struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + const struct rte_flow_action *action_rss = NULL; + const struct rte_flow_action_meter *mtr = NULL; + const struct rte_flow_action *act_q = NULL; int mark_actions = 0, vtag_actions = 0; struct roc_npc *npc = &dev->npc; struct roc_npc_flow *flow; + uint32_t req_act = 0; + int i, rc; + + for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) { + if (actions[i].type == RTE_FLOW_ACTION_TYPE_METER) + req_act |= ROC_NPC_ACTION_TYPE_METER; + + if (actions[i].type == RTE_FLOW_ACTION_TYPE_QUEUE) { + req_act |= ROC_NPC_ACTION_TYPE_QUEUE; + act_q = &actions[i]; + } + if (actions[i].type == RTE_FLOW_ACTION_TYPE_RSS) { + req_act |= ROC_NPC_ACTION_TYPE_RSS; + action_rss = &actions[i]; + } + } + + if (req_act & ROC_NPC_ACTION_TYPE_METER) { + if ((req_act & ROC_NPC_ACTION_TYPE_RSS) && + ((req_act & ROC_NPC_ACTION_TYPE_QUEUE))) { + return NULL; + } + if (req_act & ROC_NPC_ACTION_TYPE_RSS) { + rc = cn10k_rss_action_validate(eth_dev, attr, + action_rss); + if (rc) + return NULL; + } else if (req_act & ROC_NPC_ACTION_TYPE_QUEUE) { + const struct rte_flow_action_queue *act_queue; + act_queue = (const struct rte_flow_action_queue *) + act_q->conf; + if (act_queue->index > eth_dev->data->nb_rx_queues) + return NULL; + } else { + return NULL; + } + } + + for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) { + if (actions[i].type == RTE_FLOW_ACTION_TYPE_METER) { + mtr = (const struct rte_flow_action_meter *)actions[i] + .conf; + rc = cn10k_mtr_configure(eth_dev, actions); + if (rc) { + rte_flow_error_set(error, 0, + RTE_FLOW_ERROR_TYPE_ACTION, NULL, + "Failed to configure mtr "); + return NULL; + } + break; + } + } flow = cnxk_flow_create(eth_dev, attr, pattern, actions, error); - if (!flow) + if (!flow) { + if (mtr) + nix_mtr_chain_reset(eth_dev, mtr->mtr_id); + return NULL; + } else { + if (mtr) + cn10k_mtr_connect(eth_dev, mtr->mtr_id); + } mark_actions = roc_npc_mark_actions_get(npc); diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 8d94d873bb..aee83b5abb 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -457,6 +457,24 @@ int cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev, /* Other private functions */ int nix_recalc_mtu(struct rte_eth_dev *eth_dev); +int nix_mtr_validate(struct rte_eth_dev *dev, uint32_t id); +int nix_mtr_policy_act_get(struct rte_eth_dev *eth_dev, uint32_t id, + struct cnxk_mtr_policy_node **policy); +int nix_mtr_rq_update(struct rte_eth_dev *eth_dev, uint32_t id, + uint32_t queue_num, const uint16_t *queue); +int nix_mtr_chain_update(struct rte_eth_dev *eth_dev, uint32_t cur_id, + uint32_t prev_id, uint32_t next_id); +int nix_mtr_chain_reset(struct rte_eth_dev *eth_dev, uint32_t cur_id); +struct cnxk_meter_node *nix_get_mtr(struct rte_eth_dev *eth_dev, + uint32_t cur_id); +int nix_mtr_level_update(struct rte_eth_dev *eth_dev, uint32_t id, + uint32_t level); +int nix_mtr_configure(struct rte_eth_dev *eth_dev, uint32_t id); +int nix_mtr_connect(struct rte_eth_dev *eth_dev, uint32_t id); +int nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id, + uint32_t *prev_id, uint32_t *next_id, + struct cnxk_mtr_policy_node *policy, + int *tree_level); /* Inlines */ static __rte_always_inline uint64_t diff --git a/drivers/net/cnxk/cnxk_rte_flow.c b/drivers/net/cnxk/cnxk_rte_flow.c index 32c1b5dee5..56dcd36c61 100644 --- a/drivers/net/cnxk/cnxk_rte_flow.c +++ b/drivers/net/cnxk/cnxk_rte_flow.c @@ -195,6 +195,10 @@ cnxk_map_actions(struct rte_eth_dev *eth_dev, const struct rte_flow_attr *attr, ROC_NPC_ACTION_TYPE_VLAN_PCP_INSERT; in_actions[i].conf = actions->conf; break; + case RTE_FLOW_ACTION_TYPE_METER: + in_actions[i].type = ROC_NPC_ACTION_TYPE_METER; + in_actions[i].conf = actions->conf; + break; default: plt_npc_dbg("Action is not supported = %d", actions->type);