From patchwork Fri Oct 1 05:59:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 100194 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 354D0A0C43; Fri, 1 Oct 2021 07:59:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CE53141101; Fri, 1 Oct 2021 07:59:24 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (lpdvsmtp09.broadcom.com [192.19.166.228]) by mails.dpdk.org (Postfix) with ESMTP id 67E5540040 for ; Fri, 1 Oct 2021 07:59:22 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 7A58635FB4; Thu, 30 Sep 2021 22:59:20 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 7A58635FB4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1633067961; bh=oy0ecuiYHevDZKpyRE7LSfyC39nFJfnDB97BhXfJWfc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TMWz4u68GWWbC3Vno19vfu+uY8FILnfDn6m9f6QiNmL+m6Se1VTdPjhZuCAtczmgN tQ8syo3T3xqkonQ0OLUD20TI4oLXEU+ETpCkDMtOw9l/kNWt1alTukM4nJDsn41HXy iF3mxzCm2fDyCbStyUleR8HSs96xdPbaMqXFRTY8= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Fri, 1 Oct 2021 11:29:01 +0530 Message-Id: <20211001055909.27276-2-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> References: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 1/9] net/bnxt: add nat support for dest IP and port combination X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha * Added support for nat action for the destination ip and port combination for the thor platform. This is not supported for whitney platform. * Consolidated the encapsulation and nat entries for scaling flows with nat actions. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Shahaji Bhosle Reviewed-by: Michael Baucom Reviewed-by: Randy Schacher --- .../generic_templates/ulp_template_db_act.c | 376 +++++++++++------- .../generic_templates/ulp_template_db_enum.h | 18 +- .../generic_templates/ulp_template_db_tbl.c | 14 +- .../ulp_template_db_thor_class.c | 2 +- .../ulp_template_db_wh_plus_act.c | 96 +++-- 5 files changed, 317 insertions(+), 189 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c index 0da6070d7d..ce878d8e02 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Mon May 17 15:30:41 2021 */ +/* date: Wed Aug 25 14:37:06 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -47,59 +47,67 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { [BNXT_ULP_ACT_HID_04bc] = 30, [BNXT_ULP_ACT_HID_00a9] = 31, [BNXT_ULP_ACT_HID_020f] = 32, - [BNXT_ULP_ACT_HID_04a9] = 33, - [BNXT_ULP_ACT_HID_01fc] = 34, - [BNXT_ULP_ACT_HID_04be] = 35, - [BNXT_ULP_ACT_HID_00ab] = 36, - [BNXT_ULP_ACT_HID_0211] = 37, - [BNXT_ULP_ACT_HID_04ab] = 38, - [BNXT_ULP_ACT_HID_01fe] = 39, - [BNXT_ULP_ACT_HID_0667] = 40, - [BNXT_ULP_ACT_HID_0254] = 41, - [BNXT_ULP_ACT_HID_03ba] = 42, - [BNXT_ULP_ACT_HID_0654] = 43, - [BNXT_ULP_ACT_HID_03a7] = 44, - [BNXT_ULP_ACT_HID_0669] = 45, - [BNXT_ULP_ACT_HID_0256] = 46, - [BNXT_ULP_ACT_HID_03bc] = 47, - [BNXT_ULP_ACT_HID_0656] = 48, - [BNXT_ULP_ACT_HID_03a9] = 49, - [BNXT_ULP_ACT_HID_021b] = 50, - [BNXT_ULP_ACT_HID_021c] = 51, - [BNXT_ULP_ACT_HID_021e] = 52, - [BNXT_ULP_ACT_HID_063f] = 53, - [BNXT_ULP_ACT_HID_0510] = 54, - [BNXT_ULP_ACT_HID_03c6] = 55, - [BNXT_ULP_ACT_HID_0082] = 56, - [BNXT_ULP_ACT_HID_06bb] = 57, - [BNXT_ULP_ACT_HID_021d] = 58, - [BNXT_ULP_ACT_HID_0641] = 59, - [BNXT_ULP_ACT_HID_0512] = 60, - [BNXT_ULP_ACT_HID_03c8] = 61, - [BNXT_ULP_ACT_HID_0084] = 62, - [BNXT_ULP_ACT_HID_06bd] = 63, - [BNXT_ULP_ACT_HID_06d7] = 64, - [BNXT_ULP_ACT_HID_02c4] = 65, - [BNXT_ULP_ACT_HID_042a] = 66, - [BNXT_ULP_ACT_HID_06c4] = 67, - [BNXT_ULP_ACT_HID_0417] = 68, - [BNXT_ULP_ACT_HID_06d9] = 69, - [BNXT_ULP_ACT_HID_02c6] = 70, - [BNXT_ULP_ACT_HID_042c] = 71, - [BNXT_ULP_ACT_HID_06c6] = 72, - [BNXT_ULP_ACT_HID_0419] = 73, - [BNXT_ULP_ACT_HID_0119] = 74, - [BNXT_ULP_ACT_HID_046f] = 75, - [BNXT_ULP_ACT_HID_05d5] = 76, - [BNXT_ULP_ACT_HID_0106] = 77, - [BNXT_ULP_ACT_HID_05c2] = 78, - [BNXT_ULP_ACT_HID_011b] = 79, - [BNXT_ULP_ACT_HID_0471] = 80, - [BNXT_ULP_ACT_HID_05d7] = 81, - [BNXT_ULP_ACT_HID_0108] = 82, - [BNXT_ULP_ACT_HID_05c4] = 83, - [BNXT_ULP_ACT_HID_00a2] = 84, - [BNXT_ULP_ACT_HID_00a4] = 85 + [BNXT_ULP_ACT_HID_0153] = 33, + [BNXT_ULP_ACT_HID_04a9] = 34, + [BNXT_ULP_ACT_HID_01fc] = 35, + [BNXT_ULP_ACT_HID_04be] = 36, + [BNXT_ULP_ACT_HID_00ab] = 37, + [BNXT_ULP_ACT_HID_0211] = 38, + [BNXT_ULP_ACT_HID_0155] = 39, + [BNXT_ULP_ACT_HID_04ab] = 40, + [BNXT_ULP_ACT_HID_01fe] = 41, + [BNXT_ULP_ACT_HID_0667] = 42, + [BNXT_ULP_ACT_HID_0254] = 43, + [BNXT_ULP_ACT_HID_03ba] = 44, + [BNXT_ULP_ACT_HID_02fe] = 45, + [BNXT_ULP_ACT_HID_0654] = 46, + [BNXT_ULP_ACT_HID_03a7] = 47, + [BNXT_ULP_ACT_HID_0669] = 48, + [BNXT_ULP_ACT_HID_0256] = 49, + [BNXT_ULP_ACT_HID_03bc] = 50, + [BNXT_ULP_ACT_HID_0300] = 51, + [BNXT_ULP_ACT_HID_0656] = 52, + [BNXT_ULP_ACT_HID_03a9] = 53, + [BNXT_ULP_ACT_HID_021b] = 54, + [BNXT_ULP_ACT_HID_021c] = 55, + [BNXT_ULP_ACT_HID_021e] = 56, + [BNXT_ULP_ACT_HID_063f] = 57, + [BNXT_ULP_ACT_HID_0510] = 58, + [BNXT_ULP_ACT_HID_03c6] = 59, + [BNXT_ULP_ACT_HID_0082] = 60, + [BNXT_ULP_ACT_HID_06bb] = 61, + [BNXT_ULP_ACT_HID_021d] = 62, + [BNXT_ULP_ACT_HID_0641] = 63, + [BNXT_ULP_ACT_HID_0512] = 64, + [BNXT_ULP_ACT_HID_03c8] = 65, + [BNXT_ULP_ACT_HID_0084] = 66, + [BNXT_ULP_ACT_HID_06bd] = 67, + [BNXT_ULP_ACT_HID_06d7] = 68, + [BNXT_ULP_ACT_HID_02c4] = 69, + [BNXT_ULP_ACT_HID_042a] = 70, + [BNXT_ULP_ACT_HID_036e] = 71, + [BNXT_ULP_ACT_HID_06c4] = 72, + [BNXT_ULP_ACT_HID_0417] = 73, + [BNXT_ULP_ACT_HID_06d9] = 74, + [BNXT_ULP_ACT_HID_02c6] = 75, + [BNXT_ULP_ACT_HID_042c] = 76, + [BNXT_ULP_ACT_HID_0370] = 77, + [BNXT_ULP_ACT_HID_06c6] = 78, + [BNXT_ULP_ACT_HID_0419] = 79, + [BNXT_ULP_ACT_HID_0119] = 80, + [BNXT_ULP_ACT_HID_046f] = 81, + [BNXT_ULP_ACT_HID_05d5] = 82, + [BNXT_ULP_ACT_HID_0519] = 83, + [BNXT_ULP_ACT_HID_0106] = 84, + [BNXT_ULP_ACT_HID_05c2] = 85, + [BNXT_ULP_ACT_HID_011b] = 86, + [BNXT_ULP_ACT_HID_0471] = 87, + [BNXT_ULP_ACT_HID_05d7] = 88, + [BNXT_ULP_ACT_HID_051b] = 89, + [BNXT_ULP_ACT_HID_0108] = 90, + [BNXT_ULP_ACT_HID_05c4] = 91, + [BNXT_ULP_ACT_HID_00a2] = 92, + [BNXT_ULP_ACT_HID_00a4] = 93 }; /* Array for the act matcher list */ @@ -429,22 +437,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 3 }, [33] = { - .act_hid = BNXT_ULP_ACT_HID_04a9, + .act_hid = BNXT_ULP_ACT_HID_0153, .act_pattern_id = 3, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [34] = { - .act_hid = BNXT_ULP_ACT_HID_01fc, + .act_hid = BNXT_ULP_ACT_HID_04a9, .act_pattern_id = 4, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | @@ -452,40 +458,63 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { .act_tid = 3 }, [35] = { - .act_hid = BNXT_ULP_ACT_HID_04be, + .act_hid = BNXT_ULP_ACT_HID_01fc, .act_pattern_id = 5, .app_sig = 0, .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [36] = { - .act_hid = BNXT_ULP_ACT_HID_00ab, + .act_hid = BNXT_ULP_ACT_HID_04be, .act_pattern_id = 6, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [37] = { - .act_hid = BNXT_ULP_ACT_HID_0211, + .act_hid = BNXT_ULP_ACT_HID_00ab, .act_pattern_id = 7, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, [38] = { - .act_hid = BNXT_ULP_ACT_HID_04ab, + .act_hid = BNXT_ULP_ACT_HID_0211, .act_pattern_id = 8, .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [39] = { + .act_hid = BNXT_ULP_ACT_HID_0155, + .act_pattern_id = 9, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [40] = { + .act_hid = BNXT_ULP_ACT_HID_04ab, + .act_pattern_id = 10, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_DST | @@ -494,9 +523,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [39] = { + [41] = { .act_hid = BNXT_ULP_ACT_HID_01fe, - .act_pattern_id = 9, + .act_pattern_id = 11, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -507,9 +536,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [40] = { + [42] = { .act_hid = BNXT_ULP_ACT_HID_0667, - .act_pattern_id = 10, + .act_pattern_id = 12, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -517,9 +546,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [41] = { + [43] = { .act_hid = BNXT_ULP_ACT_HID_0254, - .act_pattern_id = 11, + .act_pattern_id = 13, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -528,9 +557,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [42] = { + [44] = { .act_hid = BNXT_ULP_ACT_HID_03ba, - .act_pattern_id = 12, + .act_pattern_id = 14, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -538,9 +567,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [43] = { + [45] = { + .act_hid = BNXT_ULP_ACT_HID_02fe, + .act_pattern_id = 15, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [46] = { .act_hid = BNXT_ULP_ACT_HID_0654, - .act_pattern_id = 13, + .act_pattern_id = 16, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -550,9 +590,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [44] = { + [47] = { .act_hid = BNXT_ULP_ACT_HID_03a7, - .act_pattern_id = 14, + .act_pattern_id = 17, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -563,9 +603,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [45] = { + [48] = { .act_hid = BNXT_ULP_ACT_HID_0669, - .act_pattern_id = 15, + .act_pattern_id = 18, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -574,9 +614,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [46] = { + [49] = { .act_hid = BNXT_ULP_ACT_HID_0256, - .act_pattern_id = 16, + .act_pattern_id = 19, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -586,9 +626,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [47] = { + [50] = { .act_hid = BNXT_ULP_ACT_HID_03bc, - .act_pattern_id = 17, + .act_pattern_id = 20, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -597,9 +637,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [48] = { + [51] = { + .act_hid = BNXT_ULP_ACT_HID_0300, + .act_pattern_id = 21, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [52] = { .act_hid = BNXT_ULP_ACT_HID_0656, - .act_pattern_id = 18, + .act_pattern_id = 22, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -610,9 +662,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [49] = { + [53] = { .act_hid = BNXT_ULP_ACT_HID_03a9, - .act_pattern_id = 19, + .act_pattern_id = 23, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -624,7 +676,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 3 }, - [50] = { + [54] = { .act_hid = BNXT_ULP_ACT_HID_021b, .act_pattern_id = 0, .app_sig = 0, @@ -632,7 +684,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [51] = { + [55] = { .act_hid = BNXT_ULP_ACT_HID_021c, .act_pattern_id = 1, .app_sig = 0, @@ -641,7 +693,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [52] = { + [56] = { .act_hid = BNXT_ULP_ACT_HID_021e, .act_pattern_id = 2, .app_sig = 0, @@ -651,7 +703,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [53] = { + [57] = { .act_hid = BNXT_ULP_ACT_HID_063f, .act_pattern_id = 3, .app_sig = 0, @@ -662,7 +714,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [54] = { + [58] = { .act_hid = BNXT_ULP_ACT_HID_0510, .act_pattern_id = 4, .app_sig = 0, @@ -672,7 +724,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [55] = { + [59] = { .act_hid = BNXT_ULP_ACT_HID_03c6, .act_pattern_id = 5, .app_sig = 0, @@ -681,7 +733,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [56] = { + [60] = { .act_hid = BNXT_ULP_ACT_HID_0082, .act_pattern_id = 6, .app_sig = 0, @@ -693,7 +745,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [57] = { + [61] = { .act_hid = BNXT_ULP_ACT_HID_06bb, .act_pattern_id = 7, .app_sig = 0, @@ -704,7 +756,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [58] = { + [62] = { .act_hid = BNXT_ULP_ACT_HID_021d, .act_pattern_id = 8, .app_sig = 0, @@ -713,7 +765,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [59] = { + [63] = { .act_hid = BNXT_ULP_ACT_HID_0641, .act_pattern_id = 9, .app_sig = 0, @@ -725,7 +777,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [60] = { + [64] = { .act_hid = BNXT_ULP_ACT_HID_0512, .act_pattern_id = 10, .app_sig = 0, @@ -736,7 +788,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [61] = { + [65] = { .act_hid = BNXT_ULP_ACT_HID_03c8, .act_pattern_id = 11, .app_sig = 0, @@ -746,7 +798,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [62] = { + [66] = { .act_hid = BNXT_ULP_ACT_HID_0084, .act_pattern_id = 12, .app_sig = 0, @@ -759,7 +811,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [63] = { + [67] = { .act_hid = BNXT_ULP_ACT_HID_06bd, .act_pattern_id = 13, .app_sig = 0, @@ -771,7 +823,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 4 }, - [64] = { + [68] = { .act_hid = BNXT_ULP_ACT_HID_06d7, .act_pattern_id = 0, .app_sig = 0, @@ -780,7 +832,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [65] = { + [69] = { .act_hid = BNXT_ULP_ACT_HID_02c4, .act_pattern_id = 1, .app_sig = 0, @@ -790,7 +842,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [66] = { + [70] = { .act_hid = BNXT_ULP_ACT_HID_042a, .act_pattern_id = 2, .app_sig = 0, @@ -799,10 +851,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [67] = { - .act_hid = BNXT_ULP_ACT_HID_06c4, + [71] = { + .act_hid = BNXT_ULP_ACT_HID_036e, .act_pattern_id = 3, .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [72] = { + .act_hid = BNXT_ULP_ACT_HID_06c4, + .act_pattern_id = 4, + .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | @@ -810,9 +872,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [68] = { + [73] = { .act_hid = BNXT_ULP_ACT_HID_0417, - .act_pattern_id = 4, + .act_pattern_id = 5, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_SET_IPV4_SRC | @@ -822,9 +884,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [69] = { + [74] = { .act_hid = BNXT_ULP_ACT_HID_06d9, - .act_pattern_id = 5, + .act_pattern_id = 6, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -832,9 +894,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [70] = { + [75] = { .act_hid = BNXT_ULP_ACT_HID_02c6, - .act_pattern_id = 6, + .act_pattern_id = 7, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -843,9 +905,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [71] = { + [76] = { .act_hid = BNXT_ULP_ACT_HID_042c, - .act_pattern_id = 7, + .act_pattern_id = 8, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -853,9 +915,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [72] = { + [77] = { + .act_hid = BNXT_ULP_ACT_HID_0370, + .act_pattern_id = 9, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [78] = { .act_hid = BNXT_ULP_ACT_HID_06c6, - .act_pattern_id = 8, + .act_pattern_id = 10, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -865,9 +938,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [73] = { + [79] = { .act_hid = BNXT_ULP_ACT_HID_0419, - .act_pattern_id = 9, + .act_pattern_id = 11, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_COUNT | @@ -878,9 +951,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [74] = { + [80] = { .act_hid = BNXT_ULP_ACT_HID_0119, - .act_pattern_id = 10, + .act_pattern_id = 12, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -888,9 +961,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [75] = { + [81] = { .act_hid = BNXT_ULP_ACT_HID_046f, - .act_pattern_id = 11, + .act_pattern_id = 13, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -899,9 +972,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [76] = { + [82] = { .act_hid = BNXT_ULP_ACT_HID_05d5, - .act_pattern_id = 12, + .act_pattern_id = 14, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -909,9 +982,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [77] = { + [83] = { + .act_hid = BNXT_ULP_ACT_HID_0519, + .act_pattern_id = 15, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [84] = { .act_hid = BNXT_ULP_ACT_HID_0106, - .act_pattern_id = 13, + .act_pattern_id = 16, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -921,9 +1005,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [78] = { + [85] = { .act_hid = BNXT_ULP_ACT_HID_05c2, - .act_pattern_id = 14, + .act_pattern_id = 17, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -934,9 +1018,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [79] = { + [86] = { .act_hid = BNXT_ULP_ACT_HID_011b, - .act_pattern_id = 15, + .act_pattern_id = 18, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -945,9 +1029,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [80] = { + [87] = { .act_hid = BNXT_ULP_ACT_HID_0471, - .act_pattern_id = 16, + .act_pattern_id = 19, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -957,9 +1041,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [81] = { + [88] = { .act_hid = BNXT_ULP_ACT_HID_05d7, - .act_pattern_id = 17, + .act_pattern_id = 20, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -968,9 +1052,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [82] = { + [89] = { + .act_hid = BNXT_ULP_ACT_HID_051b, + .act_pattern_id = 21, + .app_sig = 0, + .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [90] = { .act_hid = BNXT_ULP_ACT_HID_0108, - .act_pattern_id = 18, + .act_pattern_id = 22, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -981,9 +1077,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [83] = { + [91] = { .act_hid = BNXT_ULP_ACT_HID_05c4, - .act_pattern_id = 19, + .act_pattern_id = 23, .app_sig = 0, .act_sig = { .bits = BNXT_ULP_ACT_BIT_DEC_TTL | @@ -995,7 +1091,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 5 }, - [84] = { + [92] = { .act_hid = BNXT_ULP_ACT_HID_00a2, .act_pattern_id = 0, .app_sig = 0, @@ -1004,7 +1100,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 6 }, - [85] = { + [93] = { .act_hid = BNXT_ULP_ACT_HID_00a4, .act_pattern_id = 1, .app_sig = 0, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index c016e1940a..fcd460e707 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Aug 20 17:59:14 2021 */ +/* date: Thu Aug 26 17:43:36 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -20,7 +20,7 @@ #define BNXT_ULP_CLASS_HID_SHFTL 28 #define BNXT_ULP_CLASS_HID_MASK 65535 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048 -#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86 +#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 94 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 #define BNXT_ULP_ACT_HID_HIGH_PRIME 3793 #define BNXT_ULP_ACT_HID_SHFTR 27 @@ -29,7 +29,7 @@ #define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110 #define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50 -#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 278 +#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 277 #define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8 #define BNXT_ULP_COND_GOTO_REJECT 1023 #define BNXT_ULP_COND_GOTO_RF 0x10000 @@ -50,11 +50,11 @@ #define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313 #define ULP_THOR_CLASS_COND_LIST_SIZE 55 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7 -#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35 +#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1 #define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536 -#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39 +#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 41 #define ULP_THOR_ACT_TMPL_LIST_SIZE 7 #define ULP_THOR_ACT_TBL_LIST_SIZE 36 #define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16 @@ -2224,21 +2224,25 @@ enum bnxt_ulp_act_hid { BNXT_ULP_ACT_HID_04bc = 0x04bc, BNXT_ULP_ACT_HID_00a9 = 0x00a9, BNXT_ULP_ACT_HID_020f = 0x020f, + BNXT_ULP_ACT_HID_0153 = 0x0153, BNXT_ULP_ACT_HID_04a9 = 0x04a9, BNXT_ULP_ACT_HID_01fc = 0x01fc, BNXT_ULP_ACT_HID_04be = 0x04be, BNXT_ULP_ACT_HID_00ab = 0x00ab, BNXT_ULP_ACT_HID_0211 = 0x0211, + BNXT_ULP_ACT_HID_0155 = 0x0155, BNXT_ULP_ACT_HID_04ab = 0x04ab, BNXT_ULP_ACT_HID_01fe = 0x01fe, BNXT_ULP_ACT_HID_0667 = 0x0667, BNXT_ULP_ACT_HID_0254 = 0x0254, BNXT_ULP_ACT_HID_03ba = 0x03ba, + BNXT_ULP_ACT_HID_02fe = 0x02fe, BNXT_ULP_ACT_HID_0654 = 0x0654, BNXT_ULP_ACT_HID_03a7 = 0x03a7, BNXT_ULP_ACT_HID_0669 = 0x0669, BNXT_ULP_ACT_HID_0256 = 0x0256, BNXT_ULP_ACT_HID_03bc = 0x03bc, + BNXT_ULP_ACT_HID_0300 = 0x0300, BNXT_ULP_ACT_HID_0656 = 0x0656, BNXT_ULP_ACT_HID_03a9 = 0x03a9, BNXT_ULP_ACT_HID_021b = 0x021b, @@ -2258,21 +2262,25 @@ enum bnxt_ulp_act_hid { BNXT_ULP_ACT_HID_06d7 = 0x06d7, BNXT_ULP_ACT_HID_02c4 = 0x02c4, BNXT_ULP_ACT_HID_042a = 0x042a, + BNXT_ULP_ACT_HID_036e = 0x036e, BNXT_ULP_ACT_HID_06c4 = 0x06c4, BNXT_ULP_ACT_HID_0417 = 0x0417, BNXT_ULP_ACT_HID_06d9 = 0x06d9, BNXT_ULP_ACT_HID_02c6 = 0x02c6, BNXT_ULP_ACT_HID_042c = 0x042c, + BNXT_ULP_ACT_HID_0370 = 0x0370, BNXT_ULP_ACT_HID_06c6 = 0x06c6, BNXT_ULP_ACT_HID_0419 = 0x0419, BNXT_ULP_ACT_HID_0119 = 0x0119, BNXT_ULP_ACT_HID_046f = 0x046f, BNXT_ULP_ACT_HID_05d5 = 0x05d5, + BNXT_ULP_ACT_HID_0519 = 0x0519, BNXT_ULP_ACT_HID_0106 = 0x0106, BNXT_ULP_ACT_HID_05c2 = 0x05c2, BNXT_ULP_ACT_HID_011b = 0x011b, BNXT_ULP_ACT_HID_0471 = 0x0471, BNXT_ULP_ACT_HID_05d7 = 0x05d7, + BNXT_ULP_ACT_HID_051b = 0x051b, BNXT_ULP_ACT_HID_0108 = 0x0108, BNXT_ULP_ACT_HID_05c4 = 0x05c4, BNXT_ULP_ACT_HID_00a2 = 0x00a2, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 684fa66f48..84be09b368 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Aug 17 12:16:42 2021 */ +/* date: Thu Aug 26 17:43:36 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -2121,7 +2121,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_RX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 64 + .count = 2048 }, { .app_id = 0, @@ -2249,7 +2249,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, - .count = 64 + .count = 2048 }, { .app_id = 0, @@ -2263,14 +2263,6 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = { .app_id = 0, .device_id = BNXT_ULP_DEVICE_ID_THOR, .direction = TF_DIR_TX, - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, - .count = 32 - }, - { - .app_id = 0, - .device_id = BNXT_ULP_DEVICE_ID_THOR, - .direction = TF_DIR_TX, .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .count = 272 diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 68c1e292b2..95205a2421 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri Aug 20 18:05:25 2021 */ +/* date: Wed Aug 25 16:41:37 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c index 578ede8bba..4a2d201c2d 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Tue Jun 1 16:05:30 2021 */ +/* date: Wed Aug 25 14:37:06 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -35,7 +35,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { /* act_tid: 3, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, + .num_tbls = 7, .start_tbl_idx = 12, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, @@ -46,30 +46,30 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = { [4] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 5, - .start_tbl_idx = 18, + .start_tbl_idx = 19, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 20, + .cond_start_idx = 21, .cond_nums = 0 } }, /* act_tid: 5, egress */ [5] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 23, + .num_tbls = 7, + .start_tbl_idx = 24, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 28, + .cond_start_idx = 29, .cond_nums = 0 } }, /* act_tid: 6, egress */ [6] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 6, - .start_tbl_idx = 29, + .start_tbl_idx = 31, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 0 } } }; @@ -322,6 +322,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_bit_size = 34, .result_num_fields = 2 }, + { /* act_tid: 3, , table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 15, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, { /* act_tid: 3, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, @@ -332,7 +343,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 15, + .cond_start_idx = 16, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -351,7 +362,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 16, + .cond_start_idx = 17, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, @@ -370,7 +381,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 17, + .cond_start_idx = 18, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, @@ -389,7 +400,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 18, + .cond_start_idx = 19, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, @@ -410,7 +421,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 18, + .cond_start_idx = 19, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -429,7 +440,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 19, + .cond_start_idx = 20, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -449,7 +460,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 20, + .cond_start_idx = 21, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -468,7 +479,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 21, + .cond_start_idx = 22, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, @@ -489,7 +500,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 23, + .cond_start_idx = 24, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -508,7 +519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, + .cond_start_idx = 25, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -528,7 +539,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 26, + .cond_start_idx = 27, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -538,6 +549,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .result_num_fields = 26, .encap_num_fields = 11 }, + { /* act_tid: 5, , table: control.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 29, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, { /* act_tid: 5, , table: int_flow_counter_tbl.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_STATS_64, @@ -548,7 +570,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 28, + .cond_start_idx = 30, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -567,7 +589,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 29, + .cond_start_idx = 31, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0, @@ -586,7 +608,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, + .cond_start_idx = 32, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0, @@ -605,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 33, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR, @@ -626,7 +648,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 31, + .cond_start_idx = 33, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -645,7 +667,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, + .cond_start_idx = 34, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -665,7 +687,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 33, + .cond_start_idx = 35, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, @@ -684,7 +706,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, + .cond_start_idx = 36, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, @@ -705,7 +727,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, + .cond_start_idx = 37, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, @@ -726,7 +748,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, + .cond_start_idx = 38, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, @@ -747,7 +769,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, + .cond_start_idx = 39, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -766,7 +788,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 38, + .cond_start_idx = 40, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -844,6 +866,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT }, + /* cond_execute: act_tid: 3, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, /* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, @@ -900,6 +927,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN }, + /* cond_execute: act_tid: 5, control.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, /* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, From patchwork Fri Oct 1 05:59:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 100195 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E9C3BA0C43; Fri, 1 Oct 2021 07:59:38 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5D8B941120; Fri, 1 Oct 2021 07:59:26 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.166.228]) by mails.dpdk.org (Postfix) with ESMTP id 43503410FF for ; Fri, 1 Oct 2021 07:59:24 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 5271E35F9F; Thu, 30 Sep 2021 22:59:22 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 5271E35F9F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1633067963; bh=lEh5kZOzGdbg97L57bJ6njMhKCKasoDRGtApoFnbdqM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HhsVlyk9vpMPiklwu5LQPFKHUAbtrqMX8u5kE5LJo1aCPwhup//Gx3TJvDeVsGQVg l50aQ1hS0FiDCTmRxAb4G3TFNOTZdJ1+riXqclq/HptnASXddQyDcrDbmSipiv+5K3 /4t5GBkQb80uPXWGXKVmZyyqpnsrvKnaP+AU16Pg= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Fri, 1 Oct 2021 11:29:02 +0530 Message-Id: <20211001055909.27276-3-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> References: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 2/9] net/bnxt: support multi root capability flag X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha Update driver to read the multi root capability and ignore pci address check while creating ulp session when multi root capability is enabled in the hardware. DPDK HSI version updated from 1.10.1.70 to 1.10.2.54. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom Reviewed-by: Ajit Khaparde Reviewed-by: Randy Schacher --- drivers/net/bnxt/bnxt.h | 8 + drivers/net/bnxt/bnxt_hwrm.c | 8 + drivers/net/bnxt/hsi_struct_def_dpdk.h | 2698 +++++++++++++++++++++--- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 10 +- 4 files changed, 2420 insertions(+), 304 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 5121d05da6..b9e120d94b 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -724,6 +724,14 @@ struct bnxt { uint16_t chip_num; #define CHIP_NUM_58818 0xd818 #define BNXT_CHIP_SR2(bp) ((bp)->chip_num == CHIP_NUM_58818) +#define BNXT_FLAGS2_TESTPMD_EN BIT(3) +#define BNXT_TESTPMD_EN(bp) \ + ((bp)->flags2 & BNXT_FLAGS2_TESTPMD_EN) +#define BNXT_THOR_PTP_TIMESYNC_ENABLED(bp) \ + ((bp)->flags & BNXT_FLAGS_PTP_TIMESYNC_ENABLED) +#define BNXT_FLAGS2_MULTIROOT_EN BIT(4) +#define BNXT_MULTIROOT_EN(bp) \ + ((bp)->flags2 & BNXT_FLAGS2_MULTIROOT_EN) uint32_t fw_cap; #define BNXT_FW_CAP_HOT_RESET BIT(0) diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 503add42fd..8ccee79f0a 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -3385,6 +3385,7 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp) { struct hwrm_func_qcfg_input req = {0}; struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; + uint16_t flags; int rc; if (!BNXT_VF_IS_TRUSTED(bp)) @@ -3408,6 +3409,13 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp) bp->parent->fid = rte_le_to_cpu_16(resp->fid); bp->parent->port_id = rte_le_to_cpu_16(resp->port_id); + flags = rte_le_to_cpu_16(resp->flags); + /* check for the multi-root support */ + if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT) { + bp->flags2 |= BNXT_FLAGS2_MULTIROOT_EN; + PMD_DRV_LOG(DEBUG, "PF enabled with multi root capability\n"); + } + HWRM_UNLOCK(); return 0; diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 4d7efb19f4..9ed66525b7 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -657,6 +657,8 @@ struct cmd_nums { #define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0) /* PTP - Query extended PTP configuration. */ #define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1) + /* The command is used to allocate KTLS crypto key contexts. */ + #define HWRM_FUNC_KEY_CTX_ALLOC UINT32_C(0x1a2) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -1056,8 +1058,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 44 -#define HWRM_VERSION_STR "1.10.2.44" +#define HWRM_VERSION_RSVD 54 +#define HWRM_VERSION_STR "1.10.2.54" /**************** * hwrm_ver_get * @@ -1357,6 +1359,12 @@ struct hwrm_ver_get_output { */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \ UINT32_C(0x4000) + /* + * If set to 1, then firmware supports secure boot. + * If set to 0, then firmware doesn't support secure boot. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE \ + UINT32_C(0x8000) /* * This field represents the major version of RoCE firmware. * A change in major version represents a major release. @@ -8283,8 +8291,14 @@ struct hwrm_async_event_cmpl_reset_notify { /* Fast reset */ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \ (UINT32_C(0x4) << 8) + /* + * Reset was a result of a firmware activation. That is, the + * fw_activation flag was set in a FW_RESET operation. + */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION \ + (UINT32_C(0x5) << 8) #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \ - HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION /* * Minimum time before driver should attempt access - units 100ms ticks. * Range 0-65535 @@ -10244,8 +10258,21 @@ struct hwrm_async_event_cmpl_error_report_base { */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL \ UINT32_C(0x2) + /* + * There was a low level error with an NVM write or erase. + * See nvm_err_type for more details. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM \ + UINT32_C(0x3) + /* + * This indicates doorbell drop threshold was hit. When this + * threshold is crossed, it indicates one or more doorbells for + * the function were dropped by hardware. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \ + UINT32_C(0x4) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD } __rte_packed; /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ @@ -10386,6 +10413,162 @@ struct hwrm_async_event_cmpl_error_report_invalid_signal { HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL } __rte_packed; +/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_nvm { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + /* Indicates the address where error was detected */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK \ + UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT \ + 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * There was a low level error with an NVM operation. + * See nvm_err_type for more details. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR \ + UINT32_C(0x3) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR + /* The specific type of NVM error */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT \ + 8 + /* + * There was a low level error with an NVM write operation. + * Verification of written data did not match. + * event_data2 will be the failing address. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE \ + (UINT32_C(0x1) << 8) + /* + * There was a low level error with an NVM erase operation. + * All the bits were not erased. + * event_data2 will be the failing address. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE \ + (UINT32_C(0x2) << 8) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE +} __rte_packed; + +/* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ +struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT \ + UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT \ + 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT \ + 0 + /* + * This indicates doorbell drop threshold was hit. When this + * threshold is crossed, it indicates one or more doorbells for + * the function were dropped by hardware. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD \ + UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD +} __rte_packed; + /* metadata_base_msg (size:64b/8B) */ struct metadata_base_msg { uint16_t md_type_link; @@ -11204,6 +11387,18 @@ struct hwrm_func_vf_cfg_input { */ #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \ UINT32_C(0x800) + /* + * This bit must be '1' for the num_tx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_KEY_CTXS \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the num_rx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_KEY_CTXS \ + UINT32_C(0x2000) /* * The maximum transmission unit requested on the function. * The HWRM should make sure that the mtu of @@ -11353,7 +11548,10 @@ struct hwrm_func_vf_cfg_input { uint16_t num_stat_ctxs; /* The number of HW ring groups requested for the VF. */ uint16_t num_hw_ring_grps; - uint8_t unused_0[4]; + /* Number of Tx Key Contexts requested. */ + uint16_t num_tx_key_ctxs; + /* Number of Rx Key Contexts requested. */ + uint16_t num_rx_key_ctxs; } __rte_packed; /* hwrm_func_vf_cfg_output (size:128b/16B) */ @@ -11423,7 +11621,7 @@ struct hwrm_func_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcaps_output (size:704b/88B) */ +/* hwrm_func_qcaps_output (size:768b/96B) */ struct hwrm_func_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -11787,7 +11985,13 @@ struct hwrm_func_qcaps_output { * (max_tx_rings) to the function. */ uint16_t max_sp_tx_rings; - uint8_t unused_0[2]; + /* + * The maximum number of MSI-X vectors that may be allocated across + * all VFs for the function. This is valid only on the PF with SR-IOV + * enabled. Returns zero if this command is called on a PF with + * SR-IOV disabled or on a VF. + */ + uint16_t max_msix_vfs; uint32_t flags_ext; /* * If 1, the device can be configured to set the ECN bits in the @@ -11965,7 +12169,12 @@ struct hwrm_func_qcaps_output { * to the primate processor block. */ #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10) - uint8_t unused_1; + /* + * Maximum number of Key Contexts supported per HWRM + * function call for allocating Key Contexts. + */ + uint16_t max_key_ctxs_alloc; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12023,7 +12232,7 @@ struct hwrm_func_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcfg_output (size:832b/104B) */ +/* hwrm_func_qcfg_output (size:896b/112B) */ struct hwrm_func_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -12614,7 +12823,11 @@ struct hwrm_func_qcfg_output { * value is used if ring MTU is not specified. */ uint16_t host_mtu; - uint8_t unused_3; + /* Number of Tx Key Contexts allocated. */ + uint16_t alloc_tx_key_ctxs; + /* Number of Rx Key Contexts allocated. */ + uint16_t alloc_rx_key_ctxs; + uint8_t unused_3[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12630,7 +12843,7 @@ struct hwrm_func_qcfg_output { *****************/ -/* hwrm_func_cfg_input (size:832b/104B) */ +/* hwrm_func_cfg_input (size:896b/112B) */ struct hwrm_func_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -12663,7 +12876,7 @@ struct hwrm_func_cfg_input { /* * Function ID of the function that is being * configured. - * If set to 0xFF... (All Fs), then the configuration is + * If set to 0xFF... (All Fs), then the the configuration is * for the requesting function. */ uint16_t fid; @@ -13076,6 +13289,18 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU \ UINT32_C(0x20000000) + /* + * This bit must be '1' for the number of Tx Key Contexts + * field to be configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_TX_KEY_CTXS \ + UINT32_C(0x40000000) + /* + * This bit must be '1' for the number of Rx Key Contexts + * field to be configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_RX_KEY_CTXS \ + UINT32_C(0x80000000) /* * This field can be used by the admin PF to configure * mtu of foster PFs. @@ -13390,7 +13615,7 @@ struct hwrm_func_cfg_input { /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the TX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block block. When this bit is ‘0’, this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE \ UINT32_C(0x20) @@ -13404,7 +13629,7 @@ struct hwrm_func_cfg_input { /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the RX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block block. When this bit is ‘0’, this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE \ UINT32_C(0x80) @@ -13527,6 +13752,11 @@ struct hwrm_func_cfg_input { * ring that is assigned to a function has a valid mtu. */ uint16_t host_mtu; + /* Number of Tx Key Contexts requested. */ + uint16_t num_tx_key_ctxs; + /* Number of Rx Key Contexts requested. */ + uint16_t num_rx_key_ctxs; + uint8_t unused_0[4]; } __rte_packed; /* hwrm_func_cfg_output (size:128b/16B) */ @@ -14103,6 +14333,13 @@ struct hwrm_func_drv_rgtr_input { */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT \ UINT32_C(0x100) + /* + * When this bit is 1, the function's driver is indicating the + * support of handling the NPAR 1.2 feature where the s-tag may be + * a value other than 0x8100 or 0x88a8. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \ + UINT32_C(0x200) uint32_t enables; /* * This bit must be '1' for the os_type field to be @@ -14664,7 +14901,7 @@ struct hwrm_func_resource_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_resource_qcaps_output (size:448b/56B) */ +/* hwrm_func_resource_qcaps_output (size:512b/64B) */ struct hwrm_func_resource_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -14739,6 +14976,14 @@ struct hwrm_func_resource_qcaps_output { */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + /* Minimum guaranteed number of Tx Key Contexts */ + uint16_t min_tx_key_ctxs; + /* Maximum non-guaranteed number of Tx Key Contexts */ + uint16_t max_tx_key_ctxs; + /* Minimum guaranteed number of Rx Key Contexts */ + uint16_t min_rx_key_ctxs; + /* Maximum non-guaranteed number of Rx Key Contexts */ + uint16_t max_rx_key_ctxs; uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output @@ -14755,7 +15000,7 @@ struct hwrm_func_resource_qcaps_output { *****************************/ -/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ +/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */ struct hwrm_func_vf_resource_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -14829,6 +15074,14 @@ struct hwrm_func_vf_resource_cfg_input { */ #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + /* Minimum guaranteed number of Tx Key Contexts */ + uint16_t min_tx_key_ctxs; + /* Maximum non-guaranteed number of Tx Key Contexts */ + uint16_t max_tx_key_ctxs; + /* Minimum guaranteed number of Rx Key Contexts */ + uint16_t min_rx_key_ctxs; + /* Maximum non-guaranteed number of Rx Key Contexts */ + uint16_t max_rx_key_ctxs; uint8_t unused_0[2]; } __rte_packed; @@ -14858,7 +15111,11 @@ struct hwrm_func_vf_resource_cfg_output { uint16_t reserved_stat_ctx; /* Reserved number of ring groups */ uint16_t reserved_hw_ring_grps; - uint8_t unused_0[7]; + /* Actual number of Tx Key Contexts reserved */ + uint16_t reserved_tx_key_ctxs; + /* Actual number of Rx Key Contexts reserved */ + uint16_t reserved_rx_key_ctxs; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -18132,7 +18389,7 @@ struct hwrm_error_recovery_qcfg_output { /*************************** * hwrm_func_echo_response * - ****************************/ + ***************************/ /* hwrm_func_echo_response_input (size:192b/24B) */ @@ -18190,13 +18447,13 @@ struct hwrm_func_echo_response_output { uint8_t valid; } __rte_packed; -/*********************** - * hwrm_func_vlan_qcfg * - ***********************/ +/************************** + * hwrm_func_ptp_pin_qcfg * + **************************/ -/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ -struct hwrm_func_vlan_qcfg_input { +/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ +struct hwrm_func_ptp_pin_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18225,18 +18482,11 @@ struct hwrm_func_vlan_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. - */ - uint16_t fid; - uint8_t unused_0[6]; + uint8_t unused_0[8]; } __rte_packed; -/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ -struct hwrm_func_vlan_qcfg_output { +/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ +struct hwrm_func_ptp_pin_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18245,32 +18495,94 @@ struct hwrm_func_vlan_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint64_t unused_0; - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. + * The number of TSIO pins that are configured on this board + * Up to 4 pins can be returned in the response. */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; + uint8_t num_pins; + /* Pin state */ + uint8_t state; /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * When this bit is '1', TSIO pin 0 is enabled. + * When this bit is '0', TSIO pin 0 is disabled. */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd2; - /* Future use. */ - uint32_t rsvd3; - uint8_t unused_3[3]; + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN0_ENABLED \ + UINT32_C(0x1) + /* + * When this bit is '1', TSIO pin 1 is enabled. + * When this bit is '0', TSIO pin 1 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN1_ENABLED \ + UINT32_C(0x2) + /* + * When this bit is '1', TSIO pin 2 is enabled. + * When this bit is '0', TSIO pin 2 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN2_ENABLED \ + UINT32_C(0x4) + /* + * When this bit is '1', TSIO pin 3 is enabled. + * When this bit is '0', TSIO pin 3 is disabled. + */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN3_ENABLED \ + UINT32_C(0x8) + /* Type of function for Pin #0. */ + uint8_t pin0_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT + /* Type of function for Pin #1. */ + uint8_t pin1_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT + /* Type of function for Pin #2. */ + uint8_t pin2_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT + /* Type of function for Pin #3. */ + uint8_t pin3_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT + uint8_t unused_0; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -18281,13 +18593,13 @@ struct hwrm_func_vlan_qcfg_output { uint8_t valid; } __rte_packed; -/********************** - * hwrm_func_vlan_cfg * - **********************/ +/************************* + * hwrm_func_ptp_pin_cfg * + *************************/ -/* hwrm_func_vlan_cfg_input (size:384b/48B) */ -struct hwrm_func_vlan_cfg_input { +/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ +struct hwrm_func_ptp_pin_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -18316,74 +18628,148 @@ struct hwrm_func_vlan_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. - */ - uint16_t fid; - uint8_t unused_0[2]; uint32_t enables; /* - * This bit must be '1' for the stag_vid field to be + * This bit must be '1' for the pin0_state field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_STATE \ + UINT32_C(0x1) /* - * This bit must be '1' for the ctag_vid field to be + * This bit must be '1' for the pin0_usage field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_USAGE \ + UINT32_C(0x2) /* - * This bit must be '1' for the stag_pcp field to be + * This bit must be '1' for the pin1_state field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_STATE \ + UINT32_C(0x4) /* - * This bit must be '1' for the ctag_pcp field to be + * This bit must be '1' for the pin1_usage field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_USAGE \ + UINT32_C(0x8) /* - * This bit must be '1' for the stag_tpid field to be + * This bit must be '1' for the pin2_state field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_STATE \ + UINT32_C(0x10) /* - * This bit must be '1' for the ctag_tpid field to be + * This bit must be '1' for the pin2_usage field to be * configured. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20) - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_USAGE \ + UINT32_C(0x20) /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. + * This bit must be '1' for the pin3_state field to be + * configured. */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_STATE \ + UINT32_C(0x40) /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * This bit must be '1' for the pin3_usage field to be + * configured. */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd1; - /* Future use. */ - uint32_t rsvd2; - uint8_t unused_3[4]; + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_USAGE \ + UINT32_C(0x80) + /* Enable or disable functionality of Pin #0. */ + uint8_t pin0_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED + /* Configure function for TSIO pin#0. */ + uint8_t pin0_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #1. */ + uint8_t pin1_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED + /* Configure function for TSIO pin#1. */ + uint8_t pin1_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #2. */ + uint8_t pin2_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED + /* Configure function for TSIO pin#2. */ + uint8_t pin2_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT + /* Enable or disable functionality of Pin #3. */ + uint8_t pin3_state; + /* Disabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_DISABLED UINT32_C(0x0) + /* Enabled */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED + /* Configure function for TSIO pin#3. */ + uint8_t pin3_usage; + /* No function is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0) + /* PPS IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + /* PPS OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + /* SYNC IN is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + /* SYNC OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \ + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT + uint8_t unused_0[4]; } __rte_packed; -/* hwrm_func_vlan_cfg_output (size:128b/16B) */ -struct hwrm_func_vlan_cfg_output { +/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_pin_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -18403,13 +18789,812 @@ struct hwrm_func_vlan_cfg_output { uint8_t valid; } __rte_packed; -/******************************* - * hwrm_func_vf_vnic_ids_query * - *******************************/ +/********************* + * hwrm_func_ptp_cfg * + *********************/ -/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ -struct hwrm_func_vf_vnic_ids_query_input { +/* hwrm_func_ptp_cfg_input (size:320b/40B) */ +struct hwrm_func_ptp_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* + * This bit must be '1' for the ptp_pps_event field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_PPS_EVENT \ + UINT32_C(0x1) + /* + * This bit must be '1' for the ptp_freq_adj_dll_source field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE \ + UINT32_C(0x2) + /* + * This bit must be '1' for the ptp_freq_adj_dll_phase field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_PHASE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the ptp_freq_adj_ext_period field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD \ + UINT32_C(0x8) + /* + * This bit must be '1' for the ptp_freq_adj_ext_up field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_UP \ + UINT32_C(0x10) + /* + * This bit must be '1' for the ptp_freq_adj_ext_phase field to be + * configured. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PHASE \ + UINT32_C(0x20) + /* This field is used to enable interrupt for a specific PPS event. */ + uint8_t ptp_pps_event; + /* + * When this bit is set to '1', interrupt is enabled for internal + * PPS event. Latches timestamp on PPS_OUT TSIO Pin. If user does + * not configure PPS_OUT on a TSIO pin, then firmware will allocate + * PPS_OUT to an unallocated pin. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_INTERNAL \ + UINT32_C(0x1) + /* + * When this bit is set to '1', interrupt is enabled for external + * PPS event. Latches timestamp on PPS_IN TSIO pin. + */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_EXTERNAL \ + UINT32_C(0x2) + /* + * This field is used to set the source signal used to discipline + * PHC (PTP Hardware Clock) + */ + uint8_t ptp_freq_adj_dll_source; + /* No source is selected. Use servo to discipline PHC */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_NONE \ + UINT32_C(0x0) + /* TSIO Pin #0 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 \ + UINT32_C(0x1) + /* TSIO Pin #1 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 \ + UINT32_C(0x2) + /* TSIO Pin #2 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 \ + UINT32_C(0x3) + /* TSIO Pin #3 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 \ + UINT32_C(0x4) + /* Port #0 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 \ + UINT32_C(0x5) + /* Port #1 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 \ + UINT32_C(0x6) + /* Port #2 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 \ + UINT32_C(0x7) + /* Port #3 is selected as source signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 \ + UINT32_C(0x8) + /* Invalid signal. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID \ + UINT32_C(0xff) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_LAST \ + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID + /* + * This field is used to provide phase adjustment for DLL + * used to discipline PHC (PTP Hardware clock) + */ + uint8_t ptp_freq_adj_dll_phase; + /* No Phase adjustment. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_NONE \ + UINT32_C(0x0) + /* 4Khz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_4K \ + UINT32_C(0x1) + /* 8Khz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K \ + UINT32_C(0x2) + /* 10Mhz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M \ + UINT32_C(0x3) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST \ + HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M + uint8_t unused_0[3]; + /* + * Period in nanoseconds (ns) for external signal + * input. + */ + uint32_t ptp_freq_adj_ext_period; + /* + * Up time in nanoseconds (ns) of the duty cycle + * of the external signal. This value should be + * less than ptp_freq_adj_ext_period. + */ + uint32_t ptp_freq_adj_ext_up; + /* + * Phase value is provided. This field provides the + * least significant 32 bits of the phase input. The + * most significant 16 bits come from + * ptp_freq_adj_ext_phase_upper field. Setting this + * field requires setting ptp_freq_adj_ext_period + * field as well to identify the external signal + * pin. + */ + uint32_t ptp_freq_adj_ext_phase_lower; + /* + * Phase value is provided. The lower 16 bits of this field is used + * with the 32 bit value from ptp_freq_adj_ext_phase_lower + * to provide a 48 bit value input for Phase. + */ + uint32_t ptp_freq_adj_ext_phase_upper; +} __rte_packed; + +/* hwrm_func_ptp_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_ts_query * + **************************/ + + +/* hwrm_func_ptp_ts_query_input (size:192b/24B) */ +struct hwrm_func_ptp_ts_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* If set, the response includes PPS event timestamps */ + #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PPS_TIME UINT32_C(0x1) + /* If set, the response includes PTM timestamps */ + #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME UINT32_C(0x2) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_ptp_ts_query_output (size:320b/40B) */ +struct hwrm_func_ptp_ts_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Timestamp value of last PPS event latched. */ + uint64_t pps_event_ts; + /* PTM local timestamp value. */ + uint64_t ptm_res_local_ts; + /* PTM Master timestamp value. */ + uint64_t ptm_pmstr_ts; + /* PTM Master propagation delay */ + uint32_t ptm_mstr_prop_dly; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_func_ptp_ext_cfg * + *************************/ + + +/* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ +struct hwrm_func_ptp_ext_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* + * This bit must be '1' for the phc_master_fid field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_MASTER_FID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the phc_sec_fid field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_FID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the phc_sec_mode field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_MODE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the failover_timer field to be + * configured. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_FAILOVER_TIMER \ + UINT32_C(0x8) + /* + * This field is used to configure the Master function. Only this + * function can modify or condition the PHC. Only driver calls from + * this function are allowed to adjust frequency of PHC or configure + * PPS functionality. + * If driver does not specify this FID, then firmware will auto select + * the first function that makes the call to modify PHC as the Master. + */ + uint16_t phc_master_fid; + /* + * This field is used to configure the secondary function. This + * function becomes the Master function in case of failover from + * Master function. + * If driver does not specify this FID, firmware will auto select + * the last non-master function to make a call to condition PHC as + * secondary. + */ + uint16_t phc_sec_fid; + /* + * This field is used to configure conditions under which a function + * can become a secondary function. + */ + uint8_t phc_sec_mode; + /* + * Immediately failover to the current secondary function. If there + * is no secondary function available, failover does not happen. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_SWITCH UINT32_C(0x0) + /* + * All functions (PF and VF) can be used during auto selection + * of a secondary function. This is not used in case of admin + * configured secondary function. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_ALL UINT32_C(0x1) + /* + * Only PF's can be selected as a secondary function during auto + * selection. This is not used in case of admin configured secondary + * function. + */ + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY UINT32_C(0x2) + #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_LAST \ + HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY + uint8_t unused_0; + /* + * This field indicates the failover time is milliseconds. If the + * timeout expires, firmware will failover PTP configurability from + * current master to secondary fid. + * 0 - Failover timer is automatically selected based on the last + * adjFreq() call. If adjFreq() is not called for 3 * (last interval) + * the failover kicks in. For example, if last interval between + * adjFreq() calls was 2 seconds and the next adjFreq() is not made for + * at least 6 seconds, then secondary takes over as master to condition + * PHC. Firmware rounds up the failover timer to be a multiple of 250 + * ms. Firmware checks every 250 ms to see if timer expired. + * 0xFFFFFFFF - If driver specifies this value, then failover never + * happens. Admin or auto selected Master will always be used for + * conditioning PHC. + * X - If driver specifies any other value, this is admin indicated + * failover timeout. If no adjFreq() call is made within this timeout + * value, then failover happens. This value should be a multiple of + * 250 ms. Firmware checks every 250 ms to see if timer expired. + */ + uint32_t failover_timer; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ +struct hwrm_func_ptp_ext_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_ptp_ext_qcfg * + **************************/ + + +/* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ +struct hwrm_func_ptp_ext_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} __rte_packed; + +/* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ +struct hwrm_func_ptp_ext_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Firmware returns the current PHC master function. This function + * could either be admin selected or auto selected. + */ + uint16_t phc_master_fid; + /* + * Firmware returns the current PHC secondary function. This function + * could either be admin selected or auto selected. + */ + uint16_t phc_sec_fid; + /* + * Firmware returns the last non-master/non-secondary function to + * make a call to condition PHC. + */ + uint16_t phc_active_fid0; + /* + * Firmware returns the second last non-master/non-secondary function + * to make a call to condition PHC. + */ + uint16_t phc_active_fid1; + /* + * Timestamp indicating the last time a failover happened. The master + * and secondary functions in the failover event is indicated in the + * next two fields. + */ + uint32_t last_failover_event; + /* + * Last failover happened from this function. This was the master + * function at the time of failover. + */ + uint16_t from_fid; + /* + * Last failover happened to this function. This was the secondary + * function at the time of failover. + */ + uint16_t to_fid; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_func_key_ctx_alloc * + ***************************/ + + +/* hwrm_func_key_ctx_alloc_input (size:320b/40B) */ +struct hwrm_func_key_ctx_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Function ID. */ + uint16_t fid; + /* Number of Key Contexts to be allocated. */ + uint16_t num_key_ctxs; + /* DMA buffer size in bytes. */ + uint32_t dma_bufr_size_bytes; + /* Key Context type. */ + uint8_t key_ctx_type; + /* Tx Key Context. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0) + /* Rx KTLS Context. */ + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1) + #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST \ + HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX + uint8_t unused_0[7]; + /* Host DMA address to send back KTLS context IDs. */ + uint64_t host_dma_addr; +} __rte_packed; + +/* hwrm_func_key_ctx_alloc_output (size:128b/16B) */ +struct hwrm_func_key_ctx_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Actual number of Key Contexts allocated. */ + uint16_t num_key_ctxs_allocated; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_func_vlan_qcfg * + ***********************/ + + +/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ +struct hwrm_func_vlan_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ +struct hwrm_func_vlan_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint64_t unused_0; + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd2; + /* Future use. */ + uint32_t rsvd3; + uint8_t unused_3[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_vlan_cfg * + **********************/ + + +/* hwrm_func_vlan_cfg_input (size:384b/48B) */ +struct hwrm_func_vlan_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[2]; + uint32_t enables; + /* + * This bit must be '1' for the stag_vid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1) + /* + * This bit must be '1' for the ctag_vid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2) + /* + * This bit must be '1' for the stag_pcp field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4) + /* + * This bit must be '1' for the ctag_pcp field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8) + /* + * This bit must be '1' for the stag_tpid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10) + /* + * This bit must be '1' for the ctag_tpid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20) + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd1; + /* Future use. */ + uint32_t rsvd2; + uint8_t unused_3[4]; +} __rte_packed; + +/* hwrm_func_vlan_cfg_output (size:128b/16B) */ +struct hwrm_func_vlan_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_func_vf_vnic_ids_query * + *******************************/ + + +/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ +struct hwrm_func_vf_vnic_ids_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -19128,7 +20313,7 @@ struct hwrm_func_spd_cfg_input { UINT32_C(0x10) /* * Ethertype value used in the encapsulated SPD packet header. - * The user must choose a value that is not conflicting with + * The user must chooose a value that is not conflicting with * publicly defined ethertype values. By default, the ethertype * value of 0xffff is used if there is no user specified value. */ @@ -19387,7 +20572,7 @@ struct hwrm_func_spd_qcfg_output { uint8_t unused_1; /* * Ethertype value used in the encapsulated SPD packet header. - * The user must choose a value that is not conflicting with + * The user must chooose a value that is not conflicting with * publicly defined ethertype values. By default, the ethertype * value of 0xffff is used if there is no user specified value. */ @@ -21398,6 +22583,12 @@ struct hwrm_port_mac_cfg_input { */ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \ UINT32_C(0x200) + /* + * This bit must be '1' for the ptp_adj_phase field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE \ + UINT32_C(0x400) /* Port ID of port that is to be configured. */ uint16_t port_id; /* @@ -21590,7 +22781,12 @@ struct hwrm_port_mac_cfg_input { * of sync timer updates (measured in parts per billion). */ int32_t ptp_freq_adj_ppb; - uint8_t unused_1[4]; + /* + * This unsigned field specifies the phase offset to be applied + * to the PHC (PTP Hardware Clock). This field is specified in + * nanoseconds. + */ + uint32_t ptp_adj_phase; } __rte_packed; /* hwrm_port_mac_cfg_output (size:128b/16B) */ @@ -21991,7 +23187,7 @@ struct hwrm_port_mac_ptp_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ +/* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ struct hwrm_port_mac_ptp_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -22024,10 +23220,23 @@ struct hwrm_port_mac_ptp_qcfg_output { */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ UINT32_C(0x8) + /* + * When this bit is set to '1', two specific registers for current + * time (ts_ref_clock_reg_lower and ts_ref_clock_reg_upper) are + * directly accessible by the host. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK \ + UINT32_C(0x10) uint8_t unused_0[3]; - /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */ + /* + * Offset of the PTP register for the lower 32 bits of timestamp + * for RX. + */ uint32_t rx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */ + /* + * Offset of the PTP register for the upper 32 bits of timestamp + * for RX. + */ uint32_t rx_ts_reg_off_upper; /* Offset of the PTP register for the sequence ID for RX. */ uint32_t rx_ts_reg_off_seq_id; @@ -22045,9 +23254,15 @@ struct hwrm_port_mac_ptp_qcfg_output { uint32_t rx_ts_reg_off_fifo_adv; /* PTP timestamp granularity for RX. */ uint32_t rx_ts_reg_off_granularity; - /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */ + /* + * Offset of the PTP register for the lower 32 bits of timestamp + * for TX. + */ uint32_t tx_ts_reg_off_lower; - /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */ + /* + * Offset of the PTP register for the upper 32 bits of timestamp + * for TX. + */ uint32_t tx_ts_reg_off_upper; /* Offset of the PTP register for the sequence ID for TX. */ uint32_t tx_ts_reg_off_seq_id; @@ -22055,6 +23270,10 @@ struct hwrm_port_mac_ptp_qcfg_output { uint32_t tx_ts_reg_off_fifo; /* PTP timestamp granularity for TX. */ uint32_t tx_ts_reg_off_granularity; + /* Offset of register to get lower 32 bits of current time. */ + uint32_t ts_ref_clock_reg_lower; + /* Offset of register to get upper 32 bits of current time. */ + uint32_t ts_ref_clock_reg_upper; uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output @@ -22578,7 +23797,7 @@ struct tx_port_stats_ext { } __rte_packed; /* Port Rx Statistics extended Format */ -/* rx_port_stats_ext (size:3648b/456B) */ +/* rx_port_stats_ext (size:3776b/472B) */ struct rx_port_stats_ext { /* Number of times link state changed to down */ uint64_t link_down_events; @@ -22697,6 +23916,13 @@ struct rx_port_stats_ext { uint64_t rx_discard_packets_cos6; /* Total number of rx discard packets count on cos queue 7 */ uint64_t rx_discard_packets_cos7; + /* Total number of FEC blocks corrected by the FEC function in the PHY */ + uint64_t rx_fec_corrected_blocks; + /* + * Total number of FEC blocks determined to be uncorrectable by the + * FEC function in the PHY + */ + uint64_t rx_fec_uncorrectable_blocks; } __rte_packed; /* @@ -25981,6 +27207,309 @@ struct hwrm_port_tx_fir_qcfg_output { uint8_t valid; } __rte_packed; +/*********************** + * hwrm_port_ep_tx_cfg * + ***********************/ + + +/* hwrm_port_ep_tx_cfg_input (size:256b/32B) */ +struct hwrm_port_ep_tx_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t enables; + /* When this bit is '1', the value in the ep0_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MIN_BW UINT32_C(0x1) + /* When this bit is '1', the value in the ep0_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MAX_BW UINT32_C(0x2) + /* When this bit is '1', the value in the ep1_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MIN_BW UINT32_C(0x4) + /* When this bit is '1', the value in the ep1_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MAX_BW UINT32_C(0x8) + /* When this bit is '1', the value in the ep2_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MIN_BW UINT32_C(0x10) + /* When this bit is '1', the value in the ep2_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MAX_BW UINT32_C(0x20) + /* When this bit is '1', the value in the ep3_min_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MIN_BW UINT32_C(0x40) + /* When this bit is '1', the value in the ep3_max_bw field is valid. */ + #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MAX_BW UINT32_C(0x80) + /* A port index, from 0 to the number of front panel ports, minus 1. */ + uint8_t port_id; + uint8_t unused; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep0_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep0_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep1_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep1_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep2_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set of + * PFs and VFs on PCIe endpoint 2 may use. The value is a percentage of + * the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep2_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep3_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep3_max_bw; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_port_ep_tx_cfg_output (size:128b/16B) */ +struct hwrm_port_ep_tx_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_port_ep_tx_cfg_cmd_err (size:64b/8B) */ +struct hwrm_port_ep_tx_cfg_cmd_err { + /* + * command specific error codes for the cmd_err field in + * hwrm_err_output + */ + uint8_t code; + /* Unknown error. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* The port ID is invalid */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_PORT_ID_INVALID \ + UINT32_C(0x1) + /* One of the PCIe endpoints configured is not active. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_EP_INACTIVE \ + UINT32_C(0x2) + /* A minimum bandwidth is out of range. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_RANGE \ + UINT32_C(0x3) + /* + * One endpoint's minimum bandwidth is more than its maximum + * bandwidth. + */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_MORE_THAN_MAX \ + UINT32_C(0x4) + /* The sum of the minimum bandwidths on the port is more than 100%. */ + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM \ + UINT32_C(0x5) + #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_LAST \ + HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM + uint8_t unused_0[7]; +} __rte_packed; + +/************************ + * hwrm_port_ep_tx_qcfg * + ************************/ + + +/* hwrm_port_ep_tx_qcfg_input (size:192b/24B) */ +struct hwrm_port_ep_tx_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The port whose endpoint rate limits are queried. */ + uint8_t port_id; + uint8_t unused[7]; +} __rte_packed; + +/* hwrm_port_ep_tx_qcfg_output (size:192b/24B) */ +struct hwrm_port_ep_tx_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep0_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep0_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 1 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep1_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 1 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep1_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 2 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep2_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 2 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep2_max_bw; + /* + * Specifies a minimum guaranteed bandwidth, as a percentage of the + * port bandwidth, for the set of PFs and VFs on PCIe endpoint 3 for + * the specified port. The range is 0 to 100. A value of 0 indicates no + * minimum rate. The endpoint's min_bw must be less than or equal to + * max_bw. The sum of all configured minimum bandwidths for a port must + * be less than or equal to 100. + */ + uint8_t ep3_min_bw; + /* + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 3 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no + * maximum rate. + */ + uint8_t ep3_max_bw; + uint8_t unused_0[7]; + /* + * This field is used in output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /*********************** * hwrm_queue_qportcfg * ***********************/ @@ -26097,6 +27626,13 @@ struct hwrm_queue_qportcfg_output { */ #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \ UINT32_C(0x1) + /* + * If this flag is set to '1', then service_profile will carry + * either lossy/lossless type and the new service_profile_type + * field will be used to determine if the queue is for L2/ROCE/CNP. + */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_USE_PROFILE_TYPE \ + UINT32_C(0x2) /* * Bitmask indicating which queues can be configured by the * hwrm_queue_pfcenable_cfg command. @@ -30204,67 +31740,221 @@ struct hwrm_queue_vlanpri2pri_qcfg_input { * to configure VLAN priority to user priority mapping on this port. */ uint8_t port_id; - uint8_t unused_0[7]; -} __rte_packed; - -/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */ -struct hwrm_queue_vlanpri2pri_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + uint8_t unused_0[7]; +} __rte_packed; + +/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */ +struct hwrm_queue_vlanpri2pri_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * User priority assigned to VLAN priority 0. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri0_user_pri_id; + /* + * User priority assigned to VLAN priority 1. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri1_user_pri_id; + /* + * User priority assigned to VLAN priority 2. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri2_user_pri_id; + /* + * User priority assigned to VLAN priority 3. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri3_user_pri_id; + /* + * User priority assigned to VLAN priority 4. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri4_user_pri_id; + /* + * User priority assigned to VLAN priority 5. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri5_user_pri_id; + /* + * User priority assigned to VLAN priority 6. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri6_user_pri_id; + /* + * User priority assigned to VLAN priority 7. A value of 0xff + * indicates that no user priority is assigned. The default user + * priority will be used. + */ + uint8_t vlanpri7_user_pri_id; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_queue_vlanpri2pri_cfg * + ******************************/ + + +/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */ +struct hwrm_queue_vlanpri2pri_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the vlanpri0_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the vlanpri1_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the vlanpri2_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \ + UINT32_C(0x4) + /* + * This bit must be '1' for the vlanpri3_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \ + UINT32_C(0x8) + /* + * This bit must be '1' for the vlanpri4_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \ + UINT32_C(0x10) + /* + * This bit must be '1' for the vlanpri5_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the vlanpri6_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the vlanpri7_user_pri_id field to be + * configured. + */ + #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \ + UINT32_C(0x80) + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure VLAN priority to user priority mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[3]; /* - * User priority assigned to VLAN priority 0. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 0. This value can only + * be changed before traffic has started. */ uint8_t vlanpri0_user_pri_id; /* - * User priority assigned to VLAN priority 1. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 1. This value can only + * be changed before traffic has started. */ uint8_t vlanpri1_user_pri_id; /* - * User priority assigned to VLAN priority 2. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 2. This value can only + * be changed before traffic has started. */ uint8_t vlanpri2_user_pri_id; /* - * User priority assigned to VLAN priority 3. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 3. This value can only + * be changed before traffic has started. */ uint8_t vlanpri3_user_pri_id; /* - * User priority assigned to VLAN priority 4. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 4. This value can only + * be changed before traffic has started. */ uint8_t vlanpri4_user_pri_id; /* - * User priority assigned to VLAN priority 5. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 5. This value can only + * be changed before traffic has started. */ uint8_t vlanpri5_user_pri_id; /* - * User priority assigned to VLAN priority 6. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 6. This value can only + * be changed before traffic has started. */ uint8_t vlanpri6_user_pri_id; /* - * User priority assigned to VLAN priority 7. A value of 0xff - * indicates that no user priority is assigned. The default user - * priority will be used. + * User priority assigned to VLAN priority 7. This value can only + * be changed before traffic has started. */ uint8_t vlanpri7_user_pri_id; +} __rte_packed; + +/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_vlanpri2pri_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -30276,13 +31966,13 @@ struct hwrm_queue_vlanpri2pri_qcfg_output { uint8_t valid; } __rte_packed; -/****************************** - * hwrm_queue_vlanpri2pri_cfg * - ******************************/ +/************************* + * hwrm_queue_global_cfg * + *************************/ -/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */ -struct hwrm_queue_vlanpri2pri_cfg_input { +/* hwrm_queue_global_cfg_input (size:192b/24B) */ +struct hwrm_queue_global_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30311,106 +32001,142 @@ struct hwrm_queue_vlanpri2pri_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the vlanpri0_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \ - UINT32_C(0x1) - /* - * This bit must be '1' for the vlanpri1_user_pri_id field to be - * configured. - */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \ - UINT32_C(0x2) /* - * This bit must be '1' for the vlanpri2_user_pri_id field to be - * configured. + * Configuration mode for rx cos queues, configuring whether they + * use one shared buffer pool (across ports or PCIe endpoints) or + * independent per port or per endpoint buffer pools. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \ - UINT32_C(0x4) + uint8_t mode; + /* One shared buffer pool to be used by all RX CoS queues */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_SHARED UINT32_C(0x0) /* - * This bit must be '1' for the vlanpri3_user_pri_id field to be - * configured. + * Each port or PCIe endpoint to use an independent buffer pool + * for its RX CoS queues */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \ - UINT32_C(0x8) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_LAST \ + HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT + uint8_t unused_0; + uint16_t enables; + /* This bit must be '1' when the mode field is configured. */ + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_MODE UINT32_C(0x1) /* - * This bit must be '1' for the vlanpri4_user_pri_id field to be - * configured. + * This bit must be '1' when the maximum bandwidth for queue group 0 + * (g0_max_bw) is configured. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \ - UINT32_C(0x10) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G0_MAX_BW UINT32_C(0x2) /* - * This bit must be '1' for the vlanpri5_user_pri_id field to be - * configured. + * This bit must be '1' when the maximum bandwidth for queue group 1 + * (g1_max_bw) is configured. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \ - UINT32_C(0x20) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G1_MAX_BW UINT32_C(0x4) /* - * This bit must be '1' for the vlanpri6_user_pri_id field to be - * configured. + * This bit must be '1' when the maximum bandwidth for queue group 2 + * (g2_max_bw) is configured. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \ - UINT32_C(0x40) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G2_MAX_BW UINT32_C(0x8) /* - * This bit must be '1' for the vlanpri7_user_pri_id field to be - * configured. + * This bit must be '1' when the maximum bandwidth for queue group 3 + * (g3_max_bw) is configured. */ - #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \ - UINT32_C(0x80) + #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G3_MAX_BW \ + UINT32_C(0x10) /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure VLAN priority to user priority mapping on this port. + * Specifies the maximum receive rate, as a percentage of total link + * bandwidth, of the receive traffic through queue group 0. A value + * of 0 indicates no rate limit. + * + * A queue group is a set of queues, one per traffic class. In + * single-host mode, each panel port has its own queue group, and thus, + * this rate limit shapes the traffic received on a port, in this case, + * through port 0. In multi-root or multi-host mode, each PCIe endpoint + * on the NIC has its own queue group. In these cases, the rate limit + * shapes the traffic sent to the host through one of the PCIe + * endpoints, in this case endpoint 0. */ - uint8_t port_id; - uint8_t unused_0[3]; + uint8_t g0_max_bw; /* - * User priority assigned to VLAN priority 0. This value can only - * be changed before traffic has started. + * Specifies the maximum rate of the traffic through receive CoS queue + * group 1 (for port 1 or PCIe endpoint 1). The rate is a percentage of + * total link bandwidth (the sum of the bandwidths of all links). A + * value of 0 indicates no rate limit. */ - uint8_t vlanpri0_user_pri_id; + uint8_t g1_max_bw; /* - * User priority assigned to VLAN priority 1. This value can only - * be changed before traffic has started. + * Specifies the maximum rate of the traffic through receive CoS queue + * group 2 (for port 2 or PCIe endpoint 2). The rate is a percentage of + * total link bandwidth (the sum of the bandwidths of all links). A + * value of 0 indicates no rate limit. */ - uint8_t vlanpri1_user_pri_id; + uint8_t g2_max_bw; /* - * User priority assigned to VLAN priority 2. This value can only - * be changed before traffic has started. + * Specifies the maximum receive rate, in Mbps, of the receive traffic + * through queue group 3 (for port 3 or PCIe endpoint 3). A value of 0 + * indicates no rate limit. */ - uint8_t vlanpri2_user_pri_id; + uint8_t g3_max_bw; +} __rte_packed; + +/* hwrm_queue_global_cfg_output (size:128b/16B) */ +struct hwrm_queue_global_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * User priority assigned to VLAN priority 3. This value can only - * be changed before traffic has started. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint8_t vlanpri3_user_pri_id; + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_queue_global_qcfg * + **************************/ + + +/* hwrm_queue_global_qcfg_input (size:128b/16B) */ +struct hwrm_queue_global_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * User priority assigned to VLAN priority 4. This value can only - * be changed before traffic has started. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint8_t vlanpri4_user_pri_id; + uint16_t cmpl_ring; /* - * User priority assigned to VLAN priority 5. This value can only - * be changed before traffic has started. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint8_t vlanpri5_user_pri_id; + uint16_t seq_id; /* - * User priority assigned to VLAN priority 6. This value can only - * be changed before traffic has started. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint8_t vlanpri6_user_pri_id; + uint16_t target_id; /* - * User priority assigned to VLAN priority 7. This value can only - * be changed before traffic has started. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint8_t vlanpri7_user_pri_id; + uint64_t resp_addr; } __rte_packed; -/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */ -struct hwrm_queue_vlanpri2pri_cfg_output { +/* hwrm_queue_global_qcfg_output (size:320b/40B) */ +struct hwrm_queue_global_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30419,7 +32145,95 @@ struct hwrm_queue_vlanpri2pri_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Port or PCIe endpoint id to be mapped for buffer pool 0. */ + uint8_t buffer_pool_id0_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 1. */ + uint8_t buffer_pool_id1_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 2. */ + uint8_t buffer_pool_id2_map; + /* Port or PCIe endpoint id to be mapped for buffer pool 3. */ + uint8_t buffer_pool_id3_map; + /* Size of buffer pool 0 (KBytes). */ + uint32_t buffer_pool_id0_size; + /* Size of buffer pool 1 (KBytes). */ + uint32_t buffer_pool_id1_size; + /* Size of buffer pool 2 (KBytes). */ + uint32_t buffer_pool_id2_size; + /* Size of buffer pool 3 (KBytes). */ + uint32_t buffer_pool_id3_size; + uint16_t flags; + /* + * Enumeration denoting whether the rx buffer pool mapping is + * per port or per PCIe endpoint + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING \ + UINT32_C(0x1) + /* + * The buffer_pool_id[0-3]_map field represents mapping of rx + * buffer pools to a port. + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_PORT \ + UINT32_C(0x0) + /* + * The buffer_pool_id[0-3]_map field represents mapping of rx + * buffer pools to a PCIe endpoint. + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT \ + UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_LAST \ + HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT + /* + * Configuration mode for rx cos queues, configuring whether they + * use one shared buffer pool (across ports or PCIe endpoints) or + * independent per port or per endpoint buffer pools. + */ + uint8_t mode; + /* One shared buffer pool to be used by all RX CoS queues */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_SHARED UINT32_C(0x0) + /* + * Each port or PCIe endpoint to use an independent buffer pool + * for its RX CoS queues + */ + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT UINT32_C(0x1) + #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_LAST \ + HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT + uint8_t unused_0; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 0. The rate limit is a percentage of total link bandwidth. A + * value of 0 indicates no rate limit. + * + * A queue group is a set of queues, one per traffic class. In + * single-host mode, each panel port has its own queue group, and thus, + * this rate limit shapes the traffic received on a port, in this case, + * through port 0. In multi-root or multi-host mode, each PCIe endpoint + * on the NIC has its own queue group. In these cases, the rate limit + * shapes the traffic sent to the host through one of the PCIe + * endpoints, in this case endpoint 0. + */ + uint8_t g0_max_bw; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 1 (for port 1 or PCIe endpoint 1). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. + */ + uint8_t g1_max_bw; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 2 (for port 2 or PCIe endpoint 2). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. + */ + uint8_t g2_max_bw; + /* + * Reports the rate limit applied to traffic through receive CoS queue + * group 3 (for port 3 or PCIe endpoint 3). The rate limit is a + * percentage of total link bandwidth. A value of 0 indicates no rate + * limit. + */ + uint8_t g3_max_bw; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -30902,7 +32716,7 @@ struct hwrm_vnic_cfg_input { * queue ID will be arriving on this VNIC. Packet priority to CoS mapping * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode, * ntuple filters with VNIC destination specified are invalid since they - * conflict with the CoS to VNIC steering rules in this mode. + * conflict with the the CoS to VNIC steering rules in this mode. * * If this field is not specified, packet to VNIC steering will be * subject to the standard L2 filter rules and any additional ntuple @@ -31324,6 +33138,13 @@ struct hwrm_vnic_qcaps_output { */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \ UINT32_C(0x1000) + /* + * When this bit is set '1', it indicates that firmware returns + * INVALID_PARAM error, if host drivers choose invalid hash type + * bit combinations in vnic_rss_cfg. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP \ + UINT32_C(0x2000) /* * This field advertises the maximum concurrent TPA aggregations * supported by the VNIC on new devices that support TPA v2. @@ -31674,7 +33495,34 @@ struct hwrm_vnic_rss_cfg_input { uint64_t hash_key_tbl_addr; /* Index to the rss indirection table. */ uint16_t rss_ctx_idx; - uint8_t unused_1[6]; + uint8_t flags; + /* + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to add to the current + * hash. Zeroes designate the hash_type state bits that should remain + * unchanged, if possible. If this constraint on the existing state + * cannot be satisfied, then the implementation should preference + * adding other headers so as to honor the request to add the + * specified headers. It is an error to set this flag concurrently + * with hash_type_exclude. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to remove from the + * current hash. Zeroes designate the hash_type state bits that + * should remain unchanged, if possible. If this constraint on the + * existing state cannot be satisfied, then the implementation should + * preference removing other headers so as to honor the request to + * remove the specified headers. It is an error to set this flag + * concurrently with hash_type_include. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE \ + UINT32_C(0x2) + uint8_t unused_1[5]; } __rte_packed; /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ @@ -42426,14 +44274,14 @@ struct hwrm_cfa_eem_qcaps_output { #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \ UINT32_C(0x2) /* - * When set to 1, indicates the FW supports the Centralized + * When set to 1, indicates the the FW supports the Centralized * Memory Model. The concept designates one entity for the * memory allocation while all others ‘subscribe’ to it. */ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ UINT32_C(0x4) /* - * When set to 1, indicates the FW supports the Detached + * When set to 1, indicates the the FW supports the Detached * Centralized Memory Model. The memory is allocated and managed * as a separate entity. All PFs and VFs will be granted direct * or semi-direct access to the allocated memory while none of @@ -43062,6 +44910,161 @@ struct hwrm_cfa_tflib_output { uint8_t valid; } __rte_packed; +/********************************** + * hwrm_cfa_lag_group_member_rgtr * + **********************************/ + + +/* hwrm_cfa_lag_group_member_rgtr_input (size:192b/24B) */ +struct hwrm_cfa_lag_group_member_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t mode; + /* + * Transmit only on the active port. Automatically failover + * to backup port. + */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP \ + UINT32_C(0x1) + /* + * Transmit based on packet header ntuple hash. Packet with only + * layer 2 headers will hash using the destination MAC, source MAC + * and Ethertype fields. Packets with layer 3 (IP) headers will + * hash using the destination MAC, source MAC, IP protocol/next + * header, source IP address and destination IP address. Packets + * with layer 4 (TCP/UDP) headers will hash using the destination + * MAC, source MAC, IP protocol/next header, source IP address, + * destination IP address, source port and destination port fields. + */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR \ + UINT32_C(0x2) + /* Transmit packets on all specified ports. */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST \ + UINT32_C(0x3) + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_LAST \ + HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST + /* + * Supports up to 5 ports. bit0 = port 0, bit1 = port 1, + * bit2 = port 2, bit3 = port 4, bit4 = loopback port + */ + uint8_t port_bitmap; + /* Specify the active port when active-backup mode is specified */ + uint8_t active_port; + uint8_t unused_0[5]; +} __rte_packed; + +/* hwrm_cfa_lag_group_member_rgtr_output (size:128b/16B) */ +struct hwrm_cfa_lag_group_member_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************************ + * hwrm_cfa_lag_group_member_unrgtr * + ************************************/ + + +/* hwrm_cfa_lag_group_member_unrgtr_input (size:192b/24B) */ +struct hwrm_cfa_lag_group_member_unrgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_cfa_lag_group_member_unrgtr_output (size:128b/16B) */ +struct hwrm_cfa_lag_group_member_unrgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + /*********** * hwrm_tf * ***********/ @@ -43263,8 +45266,13 @@ struct hwrm_tf_session_open_output { * the newly created session. */ uint32_t fw_session_client_id; + /* This field is used to return the status of fw session to host. */ uint32_t flags; - /* Indicates if the shared session has been created. */ + /* + * Indicates if the shared session has been created. Shared seesion + * should be the first session created ever. Its fw_rm_client_id + * should be 1. The AFM session's fw_rm_client_id is 0. + */ #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \ UINT32_C(0x1) /* @@ -43745,7 +45753,7 @@ struct hwrm_tf_session_resc_qcaps_input { #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX @@ -43860,7 +45868,7 @@ struct hwrm_tf_session_resc_alloc_input { #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX @@ -43959,7 +45967,7 @@ struct hwrm_tf_session_resc_free_input { #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX @@ -44043,7 +46051,7 @@ struct hwrm_tf_session_resc_flush_input { #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \ HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX @@ -44248,7 +46256,7 @@ struct hwrm_tf_tbl_type_get_input { #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX @@ -44337,7 +46345,7 @@ struct hwrm_tf_tbl_type_set_input { #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX @@ -44819,7 +46827,7 @@ struct hwrm_tf_ext_em_qcaps_input { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \ @@ -44843,14 +46851,14 @@ struct hwrm_tf_ext_em_qcaps_output { uint16_t resp_len; uint32_t flags; /* - * When set to 1, indicates the FW supports the Centralized + * When set to 1, indicates the the FW supports the Centralized * Memory Model. The concept designates one entity for the * memory allocation while all others ‘subscribe’ to it. */ #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ UINT32_C(0x1) /* - * When set to 1, indicates the FW supports the Detached + * When set to 1, indicates the the FW supports the Detached * Centralized Memory Model. The memory is allocated and managed * as a separate entity. All PFs and VFs will be granted direct * or semi-direct access to the allocated memory while none of @@ -44997,7 +47005,7 @@ struct hwrm_tf_ext_em_op_input { #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX @@ -45104,7 +47112,7 @@ struct hwrm_tf_ext_em_cfg_input { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \ @@ -45309,7 +47317,7 @@ struct hwrm_tf_ext_em_qcfg_input { #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX @@ -45335,7 +47343,7 @@ struct hwrm_tf_ext_em_qcfg_output { /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \ UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \ UINT32_C(0x1) #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \ @@ -45475,7 +47483,7 @@ struct hwrm_tf_em_insert_input { #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX @@ -45556,7 +47564,7 @@ struct hwrm_tf_em_hash_insert_input { #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX @@ -45637,13 +47645,13 @@ struct hwrm_tf_em_delete_input { #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX /* Unused0 */ uint16_t unused0; - /* EM internal flow hanndle. */ + /* EM internal flow handle. */ uint64_t flow_handle; /* EM Key value */ uint64_t em_key[8]; @@ -45785,7 +47793,7 @@ struct hwrm_tf_tcam_set_input { #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX @@ -45887,7 +47895,7 @@ struct hwrm_tf_tcam_get_input { #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX @@ -45983,7 +47991,7 @@ struct hwrm_tf_tcam_move_input { #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX @@ -46066,7 +48074,7 @@ struct hwrm_tf_tcam_free_input { #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX @@ -46149,7 +48157,7 @@ struct hwrm_tf_global_cfg_set_input { #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX @@ -46233,7 +48241,7 @@ struct hwrm_tf_global_cfg_get_input { #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX @@ -46308,7 +48316,7 @@ struct hwrm_tf_if_tbl_get_input { #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX @@ -46397,7 +48405,7 @@ struct hwrm_tf_if_tbl_set_input { #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX @@ -46484,7 +48492,7 @@ struct hwrm_tf_tbl_type_bulk_get_input { #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates that tx flow. */ + /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX @@ -48261,7 +50269,7 @@ struct hwrm_nvm_get_dir_info_output { ******************/ -/* hwrm_nvm_write_input (size:384b/48B) */ +/* hwrm_nvm_write_input (size:448b/56B) */ struct hwrm_nvm_write_input { /* The HWRM command request type. */ uint16_t req_type; @@ -48296,10 +50304,7 @@ struct hwrm_nvm_write_input { * This is where the source data is. */ uint64_t host_src_addr; - /* - * The Directory Entry Type (valid values are defined in the - * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). - */ + /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */ uint16_t dir_type; /* * Directory ordinal. @@ -48311,10 +50316,8 @@ struct hwrm_nvm_write_input { /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */ uint16_t dir_attr; /* - * Length of data to write, in bytes.May be - * less than or equal to the allocated size for the directory entry. - * The data length stored in the directory entry will be updated to - * reflect this value once the write is complete. + * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry. + * The data length stored in the directory entry will be updated to reflect this value once the write is complete. */ uint32_t dir_data_length; /* Option. */ @@ -48327,17 +50330,41 @@ struct hwrm_nvm_write_input { #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \ UINT32_C(0x1) /* - * The requested length of the allocated NVM for the item, in bytes. - * This value may be greater than or equal to the specified data length (dir_data_length). + * This flag indicates the sender wants to modify a continuous + * NVRAM area using a batch of this HWRM requests. The + * offset of a request must be continuous to the end of previous + * request's. Firmware does not update the directory entry until + * receiving the last request, which is indicated by the batch_last + * flag. This flag is set usually when a sender does not have a + * block of memory that is big enough to hold the entire NVRAM + * data for send at one time. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE \ + UINT32_C(0x2) + /* + * This flag can be used only when the batch_mode flag is set. It + * indicates this request is the last of batch requests. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST \ + UINT32_C(0x4) + /* + * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length). * If this value is less than the specified data length, it will be ignored. - * The response will contain the actual allocated item length, which may - * be greater than the requested item length. - * The purpose for allocating more than the required number of bytes for - * an item's data is to pre-allocate extra storage (padding) to accommodate - * the potential future growth of an item (e.g. upgraded firmware with - * a size increase, log growth, expanded configuration data). + * The response will contain the actual allocated item length, which may be greater than the requested item length. + * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate + * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data). */ uint32_t dir_item_length; + /* + * 32-bit offset of data blob from where data is being written. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t offset; + /* + * Length of data to be written.Should be non-zero. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t len; uint32_t unused_0; } __rte_packed; @@ -48352,10 +50379,8 @@ struct hwrm_nvm_write_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Length of the allocated NVM for the item, in bytes. The value may be - * greater than or equal to the specified data length or the requested item length. - * The actual item length used when creating a new directory entry will - * be a multiple of an NVM block size. + * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length. + * The actual item length used when creating a new directory entry will be a multiple of an NVM block size. */ uint32_t dir_item_length; /* The directory index of the created or modified item. */ @@ -48699,10 +50724,7 @@ struct hwrm_nvm_get_dev_info_output { /* Total size, in bytes of the NVRAM device. */ uint32_t nvram_size; uint32_t reserved_size; - /* - * Available size that can be used, in bytes. Available size is the - * NVRAM size take away the used size and reserved size. - */ + /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */ uint32_t available_size; /* This field represents the major version of NVM cfg */ uint8_t nvm_cfg_ver_maj; @@ -48844,10 +50866,7 @@ struct hwrm_nvm_mod_dir_entry_input { * The (0-based) instance of this Directory Type. */ uint16_t dir_ordinal; - /* - * The Directory Entry Extension flags (see BNX_DIR_EXT_* for - * extension flag definitions). - */ + /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */ uint16_t dir_ext; /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */ uint16_t dir_attr; @@ -49016,10 +51035,8 @@ struct hwrm_nvm_install_update_input { #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \ UINT32_C(0x1) /* - * If set to 1, then unspecified images, images not in the package file, - * will be safely deleted. - * When combined with erase_unused_space then unspecified images will be - * securely erased. + * If set to 1, then unspecified images, images not in the package file, will be safely deleted. + * When combined with erase_unused_space then unspecified images will be securely erased. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \ UINT32_C(0x2) @@ -49116,13 +51133,19 @@ struct hwrm_nvm_install_update_cmd_err { */ uint8_t code; /* Unknown error */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) /* Unable to complete operation due to fragmentation */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR \ + UINT32_C(0x1) /* nvm is completely full. */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE \ + UINT32_C(0x2) + /* Firmware update failed due to Anti-rollback. */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \ + UINT32_C(0x3) #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \ - HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE + HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK uint8_t unused_0[7]; } __rte_packed; @@ -49404,10 +51427,7 @@ struct hwrm_nvm_set_variable_input { /* index for the 4th dimensions */ uint16_t index_3; uint8_t flags; - /* - * When this bit is 1, flush internal cache after this write operation - * (see hwrm_nvm_flush command.) - */ + /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */ #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \ UINT32_C(0x1) /* encryption method */ @@ -49589,6 +51609,84 @@ struct hwrm_nvm_validate_option_cmd_err { uint8_t unused_0[7]; } __rte_packed; +/******************* + * hwrm_nvm_defrag * + *******************/ + + +/* hwrm_nvm_defrag_input (size:192b/24B) */ +struct hwrm_nvm_defrag_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* This bit must be '1' to perform NVM defragmentation. */ + #define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_nvm_defrag_output (size:128b/16B) */ +struct hwrm_nvm_defrag_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_nvm_defrag_cmd_err (size:64b/8B) */ +struct hwrm_nvm_defrag_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* NVM defragmentation could not be performed */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1) + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_LAST \ + HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL + uint8_t unused_0[7]; +} __rte_packed; + /**************** * hwrm_oem_cmd * ****************/ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 3b86410fb1..092c22e505 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1015,13 +1015,15 @@ ulp_context_initialized(struct bnxt_ulp_session_state *session, bool *init) * pointer, otherwise allocate a new session. */ static struct bnxt_ulp_session_state * -ulp_get_session(struct rte_pci_addr *pci_addr) +ulp_get_session(struct bnxt *bp, struct rte_pci_addr *pci_addr) { struct bnxt_ulp_session_state *session; + /* if multi root capability is enabled, then ignore the pci bus id */ STAILQ_FOREACH(session, &bnxt_ulp_session_list, next) { if (session->pci_info.domain == pci_addr->domain && - session->pci_info.bus == pci_addr->bus) { + (BNXT_MULTIROOT_EN(bp) || + session->pci_info.bus == pci_addr->bus)) { return session; } } @@ -1049,7 +1051,7 @@ ulp_session_init(struct bnxt *bp, pthread_mutex_lock(&bnxt_ulp_global_mutex); - session = ulp_get_session(pci_addr); + session = ulp_get_session(bp, pci_addr); if (!session) { /* Not Found the session Allocate a new one */ session = rte_zmalloc("bnxt_ulp_session", @@ -1552,7 +1554,7 @@ bnxt_ulp_port_deinit(struct bnxt *bp) pci_dev = RTE_DEV_TO_PCI(bp->eth_dev->device); pci_addr = &pci_dev->addr; pthread_mutex_lock(&bnxt_ulp_global_mutex); - session = ulp_get_session(pci_addr); + session = ulp_get_session(bp, pci_addr); pthread_mutex_unlock(&bnxt_ulp_global_mutex); /* session not found then just exit */ From patchwork Fri Oct 1 05:59:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 100196 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A9989A0C43; Fri, 1 Oct 2021 07:59:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 07A9A41137; Fri, 1 Oct 2021 07:59:28 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (lpdvsmtp09.broadcom.com [192.19.166.228]) by mails.dpdk.org (Postfix) with ESMTP id 1A8444111D; Fri, 1 Oct 2021 07:59:26 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 2E74224ABB; Thu, 30 Sep 2021 22:59:23 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 2E74224ABB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1633067965; bh=P+pZZ/o2EppbPlbM/iIN8lZYkbJ0QCHCaILScgfB45s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DkllkI6363eNbwIKEMCQJkHdXMq+zo2O1Rf1aU2P5ZPsNlQnd3JVGv4ka4aO4mF0j rzCnoKFiA7U6Rii58FI8IbrBry77djuMXYWPHm7UIsFNiHqyOxVa1fZwikuLqqtERg aDKPCZCMqTvJ/pJDZW1CxKuZ+UuoeNQYyQk6fK0c= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , stable@dpdk.org, Venkat Duvvuru Date: Fri, 1 Oct 2021 11:29:03 +0530 Message-Id: <20211001055909.27276-4-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> References: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 3/9] net/bnxt: fix the out of boundary issue in hash list X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha The number of hash bucket list calculation is fixed and added check to limit the out of boundary condition Fixes: 0001cc58d362 ("net/bnxt: support generic hash table") Cc: stable@dpdk.org Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom Reviewed-by: Randy Schacher --- drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c index 3c6e7fe924..84c83de35c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c @@ -16,20 +16,21 @@ int32_t ulp_bit_alloc_list_alloc(struct bit_alloc_list *blist, { uint64_t bentry; uint32_t idx = 0, jdx = 0; + uint32_t bsize_64 = blist->bsize / ULP_64B_IN_BYTES; /* Iterate all numbers that have all 1's */ do { bentry = blist->bdata[idx++]; - } while (bentry == -1UL && idx < blist->bsize); + } while (bentry == -1UL && idx <= bsize_64); - if (idx < blist->bsize) { + if (idx <= bsize_64) { if (bentry) jdx = __builtin_clzl(~bentry); *index = ((idx - 1) * ULP_INDEX_BITMAP_SIZE) + jdx; ULP_INDEX_BITMAP_SET(blist->bdata[(idx - 1)], jdx); return 0; } - jdx = (uint32_t)(blist->bsize * ULP_INDEX_BITMAP_SIZE); + jdx = (uint32_t)(bsize_64 * ULP_INDEX_BITMAP_SIZE); BNXT_TF_DBG(ERR, "bit allocator is full reached max:%x\n", jdx); return -1; } @@ -39,9 +40,10 @@ int32_t ulp_bit_alloc_list_dealloc(struct bit_alloc_list *blist, uint32_t index) { uint32_t idx = 0, jdx; + uint32_t bsize_64 = blist->bsize / ULP_64B_IN_BYTES; idx = index / ULP_INDEX_BITMAP_SIZE; - if (idx >= blist->bsize) { + if (idx >= bsize_64) { BNXT_TF_DBG(ERR, "invalid bit index %x:%x\n", idx, blist->bsize); return -EINVAL; @@ -127,7 +129,8 @@ ulp_gen_hash_tbl_list_init(struct ulp_hash_create_params *cparams, hash_tbl->hash_mask = size - 1; /* allocate the memory for the bit allocator */ - size = (cparams->num_key_entries / sizeof(uint64_t)) + 1; + size = (cparams->num_key_entries / sizeof(uint64_t)); + size = ULP_BYTE_ROUND_OFF_8(size); hash_tbl->bit_list.bsize = size; hash_tbl->bit_list.bdata = rte_zmalloc("Generic hash bit alloc", size, ULP_BUFFER_ALIGN_64_BYTE); @@ -311,7 +314,12 @@ ulp_gen_hash_tbl_list_add(struct ulp_gen_hash_tbl *hash_tbl, BNXT_TF_DBG(ERR, "Error in bit list alloc\n"); return -ENOMEM; } - + if (key_index > hash_tbl->num_key_entries) { + BNXT_TF_DBG(ERR, "reached max size %u:%u\n", key_index, + hash_tbl->num_key_entries); + ulp_bit_alloc_list_dealloc(&hash_tbl->bit_list, key_index); + return -ENOMEM; + } /* Update the hash entry */ ULP_HASH_BUCKET_MARK_INUSE(bucket, (uint16_t)key_index); From patchwork Fri Oct 1 05:59:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 100197 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AC0E6A0C43; Fri, 1 Oct 2021 07:59:56 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 631AD4113C; Fri, 1 Oct 2021 07:59:29 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (lpdvacalvio01.broadcom.com [192.19.166.228]) by mails.dpdk.org (Postfix) with ESMTP id E9DDC41134 for ; Fri, 1 Oct 2021 07:59:27 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 08A3D35F9F; Thu, 30 Sep 2021 22:59:25 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 08A3D35F9F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1633067967; bh=3gP0lf/dm01nYnb7Ia1zW2ybWt8JNIIioCw2c+LUmGw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ev5B/t6KZjDPc+B4krJDC8cupHA5eWxB+nIcGg/lgsFX5sYqmjba6Q0A1Tn/7s+DA IqtbPvbzdu3dA2FHV9KA+W3rsWrJ5M7rlOh7Xvolzim225LTIzTrsZwwjSaq3HQReW OP2jiQs9XEredfjRoKj/wR0HVb492b9Fygq+v8DE= From: Venkat Duvvuru To: dev@dpdk.org Cc: Farah Smith , Kishore Padmanabha , Venkat Duvvuru Date: Fri, 1 Oct 2021 11:29:04 +0530 Message-Id: <20211001055909.27276-5-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> References: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 4/9] net/bnxt: add clear on read stats support for Thor X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Farah Smith Currently, the flow stats are not cleared after they are read from the fw. This patch adds support for clear on read. Since clear on read support is added for flow stats in Thor, the flow accumulation is enabled on Thor as well. Signed-off-by: Farah Smith Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Randy Schacher Reviewed-by: Shahaji Bhosle --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 34 ++++++++++++++++++++------ drivers/net/bnxt/tf_core/tf_msg.c | 24 +++++++++++++++--- drivers/net/bnxt/tf_core/tf_msg.h | 6 +++-- drivers/net/bnxt/tf_core/tf_tbl.c | 6 +++-- drivers/net/bnxt/tf_core/tf_tbl_sram.c | 13 ++++++++-- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 3 ++- 6 files changed, 67 insertions(+), 19 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 9ed66525b7..c2146bd53c 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1058,8 +1058,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 54 -#define HWRM_VERSION_STR "1.10.2.54" +#define HWRM_VERSION_RSVD 55 +#define HWRM_VERSION_STR "1.10.2.55" /**************** * hwrm_ver_get * @@ -46253,13 +46253,22 @@ struct hwrm_tf_tbl_type_get_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entry on read. + */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* @@ -48489,13 +48498,22 @@ struct hwrm_tf_tbl_type_bulk_get_input { /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entries on read. + */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 0fbb2fe837..ea6e2af7ce 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -1851,7 +1851,8 @@ tf_msg_get_tbl_entry(struct tf *tfp, uint16_t hcapi_type, uint16_t size, uint8_t *data, - uint32_t index) + uint32_t index, + bool clear_on_read) { int rc; struct hwrm_tf_tbl_type_get_input req = { 0 }; @@ -1860,6 +1861,7 @@ tf_msg_get_tbl_entry(struct tf *tfp, uint8_t fw_session_id; struct tf_dev_info *dev; struct tf_session *tfs; + uint32_t flags = 0; /* Retrieve the session information */ rc = tf_session_get_session_internal(tfp, &tfs); @@ -1889,10 +1891,16 @@ tf_msg_get_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } + flags = (dir == TF_DIR_TX ? + HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX : + HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX); + + if (clear_on_read) + flags |= HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ; /* Populate the request */ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); - req.flags = tfp_cpu_to_le_16(dir); + req.flags = tfp_cpu_to_le_16(flags); req.type = tfp_cpu_to_le_32(hcapi_type); req.index = tfp_cpu_to_le_32(index); @@ -2105,7 +2113,8 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint32_t starting_idx, uint16_t num_entries, uint16_t entry_sz_in_bytes, - uint64_t physical_mem_addr) + uint64_t physical_mem_addr, + bool clear_on_read) { int rc; struct tfp_send_msg_parms parms = { 0 }; @@ -2115,6 +2124,7 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint8_t fw_session_id; struct tf_dev_info *dev; struct tf_session *tfs; + uint32_t flags = 0; /* Retrieve the session information */ rc = tf_session_get_session(tfp, &tfs); @@ -2144,10 +2154,16 @@ tf_msg_bulk_get_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } + flags = (dir == TF_DIR_TX ? + HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX : + HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX); + + if (clear_on_read) + flags |= HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ; /* Populate the request */ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id); - req.flags = tfp_cpu_to_le_16(dir); + req.flags = tfp_cpu_to_le_16(flags); req.type = tfp_cpu_to_le_32(hcapi_type); req.start_index = tfp_cpu_to_le_32(starting_idx); req.num_entries = tfp_cpu_to_le_32(num_entries); diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index b26b15bfa3..718bc2f3b2 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -652,7 +652,8 @@ int tf_msg_get_tbl_entry(struct tf *tfp, uint16_t hcapi_type, uint16_t size, uint8_t *data, - uint32_t index); + uint32_t index, + bool clear_on_read); /* HWRM Tunneled messages */ @@ -704,7 +705,8 @@ int tf_msg_bulk_get_tbl_entry(struct tf *tfp, uint32_t starting_idx, uint16_t num_entries, uint16_t entry_sz_in_bytes, - uint64_t physical_mem_addr); + uint64_t physical_mem_addr, + bool clear_on_read); /** * Sends Set message of a IF Table Type element to the firmware. diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 0a8720e7b6..12eca36491 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -441,7 +441,8 @@ tf_tbl_get(struct tf *tfp, hcapi_type, parms->data_sz_in_bytes, parms->data, - parms->idx); + parms->idx, + false); if (rc) { TFP_DRV_LOG(ERR, "%s, Get failed, type:%s, rc:%s\n", @@ -526,7 +527,8 @@ tf_tbl_bulk_get(struct tf *tfp, parms->starting_idx, parms->num_entries, parms->entry_sz_in_bytes, - parms->physical_mem_addr); + parms->physical_mem_addr, + false); if (rc) { TFP_DRV_LOG(ERR, "%s, Bulk get failed, type:%s, rc:%s\n", diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c index 636811bc2d..567f912dfa 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c +++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c @@ -539,6 +539,7 @@ tf_tbl_sram_get(struct tf *tfp, struct tf_tbl_sram_get_info_parms iparms = { 0 }; struct tf_sram_mgr_is_allocated_parms aparms = { 0 }; void *sram_handle = NULL; + bool clear_on_read = false; TF_CHECK_PARMS3(tfp, parms, parms->data); @@ -608,6 +609,8 @@ tf_tbl_sram_get(struct tf *tfp, strerror(-rc)); return rc; } + if (parms->type == TF_TBL_TYPE_ACT_STATS_64) + clear_on_read = true; /* Get the entry */ rc = tf_msg_get_tbl_entry(tfp, @@ -615,7 +618,8 @@ tf_tbl_sram_get(struct tf *tfp, hcapi_type, parms->data_sz_in_bytes, parms->data, - parms->idx); + parms->idx, + clear_on_read); if (rc) { TFP_DRV_LOG(ERR, "%s, Get failed, type:%s, rc:%s\n", @@ -643,6 +647,7 @@ tf_tbl_sram_bulk_get(struct tf *tfp, struct tf_sram_mgr_is_allocated_parms aparms = { 0 }; bool allocated = false; void *sram_handle = NULL; + bool clear_on_read = false; TF_CHECK_PARMS2(tfp, parms); @@ -728,6 +733,9 @@ tf_tbl_sram_bulk_get(struct tf *tfp, return rc; } + if (parms->type == TF_TBL_TYPE_ACT_STATS_64) + clear_on_read = true; + /* Get the entries */ rc = tf_msg_bulk_get_tbl_entry(tfp, parms->dir, @@ -735,7 +743,8 @@ tf_tbl_sram_bulk_get(struct tf *tfp, parms->starting_idx, parms->num_entries, parms->entry_sz_in_bytes, - parms->physical_mem_addr); + parms->physical_mem_addr, + clear_on_read); if (rc) { TFP_DRV_LOG(ERR, "%s, Bulk get failed, type:%s, rc:%s\n", diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 092c22e505..3083c40113 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -1488,7 +1488,8 @@ bnxt_ulp_port_init(struct bnxt *bp) goto jump_to_error; } - if (devid != BNXT_ULP_DEVICE_ID_THOR && BNXT_ACCUM_STATS_EN(bp)) + /* set the accumulation of the stats */ + if (BNXT_ACCUM_STATS_EN(bp)) bp->ulp_ctx->cfg_data->accum_stats = true; BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port init, accum_stats:%d\n", From patchwork Fri Oct 1 05:59:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 100198 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5B8EBA0C43; Fri, 1 Oct 2021 08:00:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 71E094113A; Fri, 1 Oct 2021 07:59:31 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (lpdvsmtp09.broadcom.com [192.19.166.228]) by mails.dpdk.org (Postfix) with ESMTP id 901524113F for ; Fri, 1 Oct 2021 07:59:29 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id D870F35FB4; Thu, 30 Sep 2021 22:59:27 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com D870F35FB4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1633067969; bh=bB9UIqyRV7GDkFpC00faejL2w3kT/vK/a7ZwZKTAbrc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YA/DL9vefEdk361w7vLlVK39b+Todu4XOiZUg3MR+PmnImjm8WFQ/o64+nM1uSqrh 4kW2nfGAJBLf9un/2Lm/rWqJgGChb3JtUlcTP1bZZoxfZjCYu8+R716IZD6PXvXkiC PekfEyLHafLc2Y2tOTUkVgDzhG8Hi6veJYlb6lx0= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Fri, 1 Oct 2021 11:29:05 +0530 Message-Id: <20211001055909.27276-6-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> References: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 5/9] net/bnxt: add feature capability option for socket direct X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha Added support for socket direct feature capability so applications can enable or disable this feature. This patch contains the template changes. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom Reviewed-by: Randy Schacher --- drivers/net/bnxt/bnxt.h | 13 -- drivers/net/bnxt/bnxt_ethdev.c | 203 ------------------ drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 11 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 6 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 10 +- .../generic_templates/ulp_template_db_enum.h | 8 +- .../generic_templates/ulp_template_db_tbl.c | 5 +- 7 files changed, 30 insertions(+), 226 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index b9e120d94b..9bf6697006 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -1060,19 +1060,6 @@ int32_t bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); int32_t bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr); -void bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, - uint8_t *mac, uint8_t *parent_mac); -uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); -struct bnxt *bnxt_get_bp(uint16_t port); -uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, - enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type); -uint16_t bnxt_get_phy_port_id(uint16_t port); -uint16_t bnxt_get_vport(uint16_t port); -enum bnxt_ulp_intf_type -bnxt_get_interface_type(uint16_t port); int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev); void bnxt_cancel_fc_thread(struct bnxt *bp); diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index aa7e7fdc85..63d764f968 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -5068,209 +5068,6 @@ static void bnxt_config_vf_req_fwd(struct bnxt *bp) BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); } -struct bnxt * -bnxt_get_bp(uint16_t port) -{ - struct bnxt *bp; - struct rte_eth_dev *dev; - - if (!rte_eth_dev_is_valid_port(port)) { - PMD_DRV_LOG(ERR, "Invalid port %d\n", port); - return NULL; - } - - dev = &rte_eth_devices[port]; - if (!is_bnxt_supported(dev)) { - PMD_DRV_LOG(ERR, "Device %d not supported\n", port); - return NULL; - } - - bp = (struct bnxt *)dev->data->dev_private; - if (!BNXT_TRUFLOW_EN(bp)) { - PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n"); - return NULL; - } - - return bp; -} - -uint16_t -bnxt_get_svif(uint16_t port_id, bool func_svif, - enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->svif; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return func_svif ? bp->func_svif : bp->port_svif; -} - -void -bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, - uint8_t *mac, uint8_t *parent_mac) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF && - type != BNXT_ULP_INTF_TYPE_PF) - return; - - eth_dev = &rte_eth_devices[port]; - bp = eth_dev->data->dev_private; - memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN); - - if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF) - memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN); -} - -uint16_t -bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF) - return 0; - - eth_dev = &rte_eth_devices[port]; - bp = eth_dev->data->dev_private; - - return bp->parent->vnic; -} -uint16_t -bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt_vnic_info *vnic; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->dflt_vnic_id; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - vnic = BNXT_GET_DEFAULT_VNIC(bp); - - return vnic->fw_vnic_id; -} - -uint16_t -bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->fw_fid; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return bp->fw_fid; -} - -enum bnxt_ulp_intf_type -bnxt_get_interface_type(uint16_t port) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) - return BNXT_ULP_INTF_TYPE_VF_REP; - - bp = eth_dev->data->dev_private; - if (BNXT_PF(bp)) - return BNXT_ULP_INTF_TYPE_PF; - else if (BNXT_VF_IS_TRUSTED(bp)) - return BNXT_ULP_INTF_TYPE_TRUSTED_VF; - else if (BNXT_VF(bp)) - return BNXT_ULP_INTF_TYPE_VF; - - return BNXT_ULP_INTF_TYPE_INVALID; -} - -uint16_t -bnxt_get_phy_port_id(uint16_t port_id) -{ - struct bnxt_representor *vfr; - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; -} - -uint16_t -bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) -{ - struct rte_eth_dev *eth_dev; - struct bnxt *bp; - - eth_dev = &rte_eth_devices[port_id]; - if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { - struct bnxt_representor *vfr = eth_dev->data->dev_private; - if (!vfr) - return 0; - - if (type == BNXT_ULP_INTF_TYPE_VF_REP) - return vfr->fw_fid - 1; - - eth_dev = vfr->parent_dev; - } - - bp = eth_dev->data->dev_private; - - return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; -} - -uint16_t -bnxt_get_vport(uint16_t port_id) -{ - return (1 << bnxt_get_phy_port_id(port_id)); -} - static void bnxt_alloc_error_recovery_info(struct bnxt *bp) { struct bnxt_error_recovery_info *info = bp->recovery_info; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 3083c40113..58a58a431d 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -301,13 +301,14 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx, } int32_t -bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, uint8_t app_id, uint32_t dev_id) { struct bnxt_ulp_app_capabilities_info *info; uint32_t num = 0; uint16_t i; bool found = false; + struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx; if (ULP_APP_DEV_UNSUPPORTED_ENABLED(ulp_ctx->cfg_data->ulp_flags)) { BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", @@ -334,6 +335,12 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, if (info[i].flags & BNXT_ULP_APP_CAP_UNICAST_ONLY) ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_APP_UNICAST_ONLY; + if (info[i].flags & BNXT_ULP_APP_CAP_SOCKET_DIRECT) { + /* Enable socket direction only if MR is enabled in fw*/ + if (BNXT_MULTIROOT_EN(bp)) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_SOCKET_DIRECT; + } } if (!found) { BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", @@ -837,7 +844,7 @@ ulp_ctx_init(struct bnxt *bp, } BNXT_TF_DBG(DEBUG, "Ulp initialized with app id %d\n", bp->app_id); - rc = bnxt_ulp_cntxt_app_caps_init(bp->ulp_ctx, bp->app_id, devid); + rc = bnxt_ulp_cntxt_app_caps_init(bp, bp->app_id, devid); if (rc) { BNXT_TF_DBG(ERR, "Unable to set caps for app(%x)/dev(%x)\n", bp->app_id, devid); diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 006df9cbc5..68f1470c61 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -13,6 +13,7 @@ #include "rte_version.h" #include "rte_ethdev.h" +#include "bnxt.h" #include "ulp_template_db_enum.h" #include "ulp_tun.h" #include "bnxt_tf_common.h" @@ -33,12 +34,15 @@ #define BNXT_ULP_APP_DEV_UNSUPPORTED 0x4 #define BNXT_ULP_HIGH_AVAIL_ENABLED 0x8 #define BNXT_ULP_APP_UNICAST_ONLY 0x10 +#define BNXT_ULP_APP_SOCKET_DIRECT 0x20 + #define ULP_VF_REP_IS_ENABLED(flag) ((flag) & BNXT_ULP_VF_REP_ENABLED) #define ULP_SHARED_SESSION_IS_ENABLED(flag) ((flag) &\ BNXT_ULP_SHARED_SESSION_ENABLED) #define ULP_APP_DEV_UNSUPPORTED_ENABLED(flag) ((flag) &\ BNXT_ULP_APP_DEV_UNSUPPORTED) #define ULP_HIGH_AVAIL_IS_ENABLED(flag) ((flag) & BNXT_ULP_HIGH_AVAIL_ENABLED) +#define ULP_SOCKET_DIRECT_IS_ENABLED(flag) ((flag) & BNXT_ULP_APP_SOCKET_DIRECT) enum bnxt_ulp_flow_mem_type { BNXT_ULP_FLOW_MEM_TYPE_INT = 0, @@ -287,7 +291,7 @@ struct bnxt_ulp_app_capabilities_info * bnxt_ulp_app_cap_list_get(uint32_t *num_entries); int32_t -bnxt_ulp_cntxt_app_caps_init(struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, uint8_t app_id, uint32_t dev_id); struct bnxt_ulp_resource_resv_info * diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 413e4c3b26..6413afdaf2 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -118,9 +118,11 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_FLOW_SIG_ID, params->flow_sig_id); + if (bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags)) + return; + /* update the WC Priority flag */ - if (!bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags) && - ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) { + if (ULP_HIGH_AVAIL_IS_ENABLED(ulp_flags)) { enum ulp_ha_mgr_region region = ULP_HA_REGION_LOW; int32_t rc; @@ -132,6 +134,10 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG, 1); } + + /* Update the socket direct flag */ + if (ULP_SOCKET_DIRECT_IS_ENABLED(ulp_flags)) + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT, 1); } /* Function to create the rte flow. */ diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index fcd460e707..31a94c14dc 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Aug 26 17:43:36 2021 */ +/* date: Thu Sep 9 11:11:05 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -211,7 +211,8 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 71, BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72, BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73, - BNXT_ULP_CF_IDX_LAST = 74 + BNXT_ULP_CF_IDX_SOCKET_DIRECT = 74, + BNXT_ULP_CF_IDX_LAST = 75 }; enum bnxt_ulp_cond_list_opc { @@ -582,7 +583,8 @@ enum bnxt_ulp_template_type { enum bnxt_ulp_app_cap { BNXT_ULP_APP_CAP_SHARED_EN = 0x00000001, BNXT_ULP_APP_CAP_HOT_UPGRADE_EN = 0x00000002, - BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004 + BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004, + BNXT_ULP_APP_CAP_SOCKET_DIRECT = 0x00000008 }; enum bnxt_ulp_fdb_resource_flags { diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 84be09b368..5383e2cd70 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Aug 26 17:43:36 2021 */ +/* date: Thu Sep 9 11:11:05 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -347,7 +347,8 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = { .device_id = BNXT_ULP_DEVICE_ID_THOR, .flags = BNXT_ULP_APP_CAP_SHARED_EN | BNXT_ULP_APP_CAP_HOT_UPGRADE_EN | - BNXT_ULP_APP_CAP_UNICAST_ONLY + BNXT_ULP_APP_CAP_UNICAST_ONLY | + BNXT_ULP_APP_CAP_SOCKET_DIRECT }, { .app_id = 2, From patchwork Fri Oct 1 05:59:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 100199 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 00758A0C43; Fri, 1 Oct 2021 08:00:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 004794114D; Fri, 1 Oct 2021 07:59:32 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.166.228]) by mails.dpdk.org (Postfix) with ESMTP id 32A4F41124 for ; Fri, 1 Oct 2021 07:59:31 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 7A82F24ABB; Thu, 30 Sep 2021 22:59:29 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 7A82F24ABB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1633067970; bh=P1UdG4+M0btTq7b/CCKqQgT0GcU5JPFnGIa2PmPCy9A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=stfanJpbMFZXf3CZTXoMPdAAzV+nGqou3G9HnVjJ4WJ8mVYAKSjbUxcl5dQUJZdsY pR4mgMB70RxJOlneDoxCgc1soL8im0nbWxb2izo2nOhyxF+nMXDMgtk92IzUdw73Rd aSeEj3Lf/YifEiSLjyHrERapGneiLfcJIF+qP1+E= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Fri, 1 Oct 2021 11:29:06 +0530 Message-Id: <20211001055909.27276-7-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> References: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 6/9] net/bnxt: enable wildcard match for ingress flows X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha Enabled wildcard match support for ipv4 ingress flows. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom Reviewed-by: Randy Schacher --- .../generic_templates/ulp_template_db_enum.h | 4 +- .../ulp_template_db_thor_class.c | 251 +++++++++--------- 2 files changed, 125 insertions(+), 130 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index 31a94c14dc..8706e45f28 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 9 11:11:05 2021 */ +/* date: Thu Sep 9 12:11:08 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -48,7 +48,7 @@ #define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2323 #define ULP_THOR_CLASS_IDENT_LIST_SIZE 38 #define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313 -#define ULP_THOR_CLASS_COND_LIST_SIZE 55 +#define ULP_THOR_CLASS_COND_LIST_SIZE 54 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7 #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2 diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 95205a2421..54bc032b0c 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Aug 25 16:41:37 2021 */ +/* date: Thu Sep 9 12:11:08 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -18,9 +18,9 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .num_tbls = 28, .start_tbl_idx = 0, .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 0, - .cond_nums = 1 } + .cond_nums = 0 } }, /* class_tid: 2, ingress */ [2] = { @@ -29,7 +29,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 28, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 } }, /* class_tid: 3, egress */ @@ -39,7 +39,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 52, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 0 } }, /* class_tid: 4, ingress */ @@ -49,7 +49,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 70, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 } }, /* class_tid: 5, egress */ @@ -59,7 +59,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .start_tbl_idx = 91, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 } } }; @@ -74,7 +74,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 0, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -96,7 +96,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 5, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 1, + .cond_start_idx = 0, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -117,7 +117,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -136,7 +136,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 2, + .cond_start_idx = 1, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -149,7 +149,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -176,7 +176,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -196,7 +196,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 3, + .cond_start_idx = 2, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -209,7 +209,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 4, + .cond_start_idx = 3, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -228,7 +228,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 5, + .cond_start_idx = 4, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -240,7 +240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 6, + .cond_start_idx = 5, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -259,7 +259,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 7, + .cond_start_idx = 6, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -277,7 +277,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 7, + .cond_start_idx = 6, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -307,7 +307,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -328,7 +328,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -349,7 +349,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -368,7 +368,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 6, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 8, + .cond_start_idx = 7, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -381,7 +381,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 9, + .cond_start_idx = 8, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, @@ -398,7 +398,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 10, + .cond_start_idx = 9, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2, @@ -415,7 +415,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 11, + .cond_start_idx = 10, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -443,7 +443,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 13, + .cond_start_idx = 12, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -473,7 +473,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 13, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -494,7 +494,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 14, + .cond_start_idx = 13, .cond_nums = 3 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -519,7 +519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 17, + .cond_start_idx = 16, .cond_nums = 3 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -544,7 +544,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 20, + .cond_start_idx = 19, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -569,7 +569,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 22, + .cond_start_idx = 21, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -594,7 +594,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, + .cond_start_idx = 23, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -619,7 +619,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 25, + .cond_start_idx = 24, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -644,7 +644,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 27, + .cond_start_idx = 26, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -670,7 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -691,7 +691,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -710,7 +710,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 29, + .cond_start_idx = 28, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -723,7 +723,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -750,7 +750,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -770,7 +770,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -783,7 +783,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 30, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -802,7 +802,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 31, + .cond_start_idx = 30, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -815,7 +815,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -842,7 +842,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, @@ -862,7 +862,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, + .cond_start_idx = 31, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -875,7 +875,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 33, + .cond_start_idx = 32, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -894,7 +894,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, + .cond_start_idx = 33, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -906,7 +906,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, + .cond_start_idx = 34, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -925,7 +925,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -943,7 +943,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -973,7 +973,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -994,7 +994,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -1016,7 +1016,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1035,7 +1035,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, + .cond_start_idx = 35, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1048,7 +1048,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, + .cond_start_idx = 36, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4, @@ -1065,7 +1065,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1093,7 +1093,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1114,7 +1114,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 38, + .cond_start_idx = 37, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1140,7 +1140,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1159,7 +1159,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 8, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -1172,7 +1172,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 40, + .cond_start_idx = 39, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1191,7 +1191,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 41, + .cond_start_idx = 40, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1203,7 +1203,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 4, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 42, + .cond_start_idx = 41, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .func_info = { @@ -1222,7 +1222,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, @@ -1240,7 +1240,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1270,7 +1270,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1291,7 +1291,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -1312,7 +1312,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1331,7 +1331,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 43, + .cond_start_idx = 42, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1344,7 +1344,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 44, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, @@ -1361,7 +1361,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 44, + .cond_start_idx = 43, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1389,7 +1389,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -1419,7 +1419,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1440,7 +1440,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 45, + .cond_start_idx = 44, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1465,7 +1465,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 47, + .cond_start_idx = 46, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1490,7 +1490,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, @@ -1517,7 +1517,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, @@ -1536,7 +1536,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1558,7 +1558,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1577,7 +1577,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 48, + .cond_start_idx = 47, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1590,7 +1590,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1619,7 +1619,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1640,7 +1640,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, @@ -1657,7 +1657,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, @@ -1676,7 +1676,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -1696,7 +1696,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1716,7 +1716,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 49, + .cond_start_idx = 48, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, @@ -1729,7 +1729,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 50, + .cond_start_idx = 49, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1748,7 +1748,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 50, + .cond_start_idx = 49, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1761,7 +1761,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF, @@ -1780,7 +1780,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1802,7 +1802,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1821,7 +1821,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 51, + .cond_start_idx = 50, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1834,7 +1834,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1861,7 +1861,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1882,7 +1882,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, @@ -1899,7 +1899,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, @@ -1918,7 +1918,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, @@ -1938,7 +1938,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1960,7 +1960,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -1979,7 +1979,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 52, + .cond_start_idx = 51, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -1992,7 +1992,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -2019,7 +2019,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2040,7 +2040,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, @@ -2057,7 +2057,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, @@ -2076,7 +2076,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2095,7 +2095,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF, @@ -2114,7 +2114,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2133,7 +2133,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 53, + .cond_start_idx = 52, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -2146,7 +2146,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF, @@ -2165,7 +2165,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2188,7 +2188,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0, @@ -2207,7 +2207,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, @@ -2227,7 +2227,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2246,7 +2246,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2265,7 +2265,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 54, + .cond_start_idx = 53, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID @@ -2278,7 +2278,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -2306,7 +2306,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0, @@ -2323,7 +2323,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, @@ -2350,7 +2350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, @@ -2373,7 +2373,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, @@ -2391,7 +2391,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 54, .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, @@ -2406,11 +2406,6 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { }; struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = { - /* cond_reject: thor, class_tid: 1 */ - { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH - }, /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */ { .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, From patchwork Fri Oct 1 05:59:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 100200 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 05A98A0C43; Fri, 1 Oct 2021 08:00:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 916A241157; Fri, 1 Oct 2021 07:59:34 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (lpdvsmtp09.broadcom.com [192.19.166.228]) by mails.dpdk.org (Postfix) with ESMTP id C5AC94114A for ; Fri, 1 Oct 2021 07:59:32 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 1DD4F35FB4; Thu, 30 Sep 2021 22:59:30 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 1DD4F35FB4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1633067972; bh=TrogNaSSr6OHfKhBjCDv0vxWeIvzQ4uqlV+0s6Kn/ds=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=f/rHDnjAMNyXUJxh3Xy0XcBNhi9vVYZ8z9Z1MQrLtGI/Ay6JDPYQxTMquMoU6fd8+ fsESrZKk2qYmdNduQXFYDpli6HECuqE6r3lTKq5yWJ7FGZxsOA82ubtNrGM7cKUnSd mhTjxCfKThXOAgBp1EQSQjreus3bH0zPUGfC4rdc= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Fri, 1 Oct 2021 11:29:07 +0530 Message-Id: <20211001055909.27276-8-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> References: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 7/9] net/bnxt: support inner IP header for GRE tunnel flows X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha This change allows adding ip header matches for GRE flows that does not specify outer ip header in the flow match pattern. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Michael Baucom Reviewed-by: Ajit Khaparde Reviewed-by: Randy Schacher --- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 7 ++++--- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 3a9c9bba27..09ebfeb785 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -1079,7 +1079,8 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, /* Set the ipv4 header bitmap and computed l3 header bitmaps */ if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || - ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) { + ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6) || + ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV4); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1); inner_flag = 1; @@ -1205,7 +1206,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, /* Set the ipv6 header bitmap and computed l3 header bitmaps */ if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || - ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) { + ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6) || + ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV6); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1); inner_flag = 1; @@ -2087,7 +2089,6 @@ ulp_rte_vxlan_decap_act_handler(const struct rte_flow_action *action_item BNXT_ULP_ACT_BIT_VXLAN_DECAP); /* Update computational field with tunnel decap info */ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN_DECAP, 1); - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1); return BNXT_TF_RC_SUCCESS; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index d3bfb8c12d..7d1bc06a3e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -27,7 +27,7 @@ #define BNXT_ULP_PROTO_HDR_UDP_NUM 4 #define BNXT_ULP_PROTO_HDR_TCP_NUM 9 #define BNXT_ULP_PROTO_HDR_VXLAN_NUM 4 -#define BNXT_ULP_PROTO_HDR_GRE_NUM 6 +#define BNXT_ULP_PROTO_HDR_GRE_NUM 2 #define BNXT_ULP_PROTO_HDR_ICMP_NUM 5 #define BNXT_ULP_PROTO_HDR_MAX 128 #define BNXT_ULP_PROTO_HDR_ENCAP_MAX 64 From patchwork Fri Oct 1 05:59:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 100201 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1205CA0C43; Fri, 1 Oct 2021 08:00:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A8A484115E; Fri, 1 Oct 2021 07:59:36 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.166.228]) by mails.dpdk.org (Postfix) with ESMTP id 6517C41154 for ; Fri, 1 Oct 2021 07:59:34 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id B194A24ABB; Thu, 30 Sep 2021 22:59:32 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com B194A24ABB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1633067973; bh=OwHRSNf736MGZ3nH+Nda2nFu8a9agsdIZMEff7KccTs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Zj3GuzSDXB++RAvlI5Uw41UZdF9QSl4FIiZtBGC1EpvdERWpOSXAeKfjyLDDeRR0M AiJ1M1X6qmh6zKZ46I0j1ZX2WJ9iP+zDW9CA3bFdMBve21NJfrpSrJKNSieibSRr/k lQPJkPTMZvJlwxEHQI2i6qhAxOd4vcv2GpY7htqQ= From: Venkat Duvvuru To: dev@dpdk.org Cc: Jay Ding , Venkat Duvvuru Date: Fri, 1 Oct 2021 11:29:08 +0530 Message-Id: <20211001055909.27276-9-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> References: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 8/9] net/bnxt: get Truflow version X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jay Ding Implement TF_GET_VERSION that returns Truflow version numbers and CFA resources capabilities. Signed-off-by: Jay Ding Signed-off-by: Venkat Duvvuru Reviewed-by: Farah Smith Reviewed-by: Randy Schacher Reviewed-by: Peter Spreadborough --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 15 ++-- drivers/net/bnxt/tf_core/tf_core.c | 30 ++++++++ drivers/net/bnxt/tf_core/tf_core.h | 75 ++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device.h | 50 ++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p4.c | 65 +++++++++++++++++- drivers/net/bnxt/tf_core/tf_device_p4.h | 79 +++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p58.c | 65 +++++++++++++++++- drivers/net/bnxt/tf_core/tf_device_p58.h | 87 ++++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_msg.c | 35 ++++++++++ drivers/net/bnxt/tf_core/tf_msg.h | 19 ++++++ 10 files changed, 514 insertions(+), 6 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index c2146bd53c..114e9fcc88 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1058,8 +1058,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 55 -#define HWRM_VERSION_STR "1.10.2.55" +#define HWRM_VERSION_RSVD 58 +#define HWRM_VERSION_STR "1.10.2.58" /**************** * hwrm_ver_get * @@ -45178,7 +45178,7 @@ struct hwrm_tf_version_get_input { uint64_t resp_addr; } __rte_packed; -/* hwrm_tf_version_get_output (size:128b/16B) */ +/* hwrm_tf_version_get_output (size:256b/32B) */ struct hwrm_tf_version_get_output { /* The specific error status for the command. */ uint16_t error_code; @@ -45195,7 +45195,14 @@ struct hwrm_tf_version_get_output { /* Version Update number. */ uint8_t update; /* unused. */ - uint8_t unused0[4]; + uint8_t unused0[5]; + /* + * This field is used to indicate device's capabilities and + * configurations. + */ + uint64_t dev_caps_cfg; + /* unused. */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 936102c804..7873bfc02c 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1802,3 +1802,33 @@ int tf_get_session_info(struct tf *tfp, return 0; } + +int tf_get_version(struct tf *tfp, + struct tf_get_version_parms *parms) +{ + int rc; + struct tf_dev_info dev; + + TF_CHECK_PARMS2(tfp, parms); + + /* This function can be called before open session, filter + * out any non-supported device types on the Core side. + */ + if (parms->device_type != TF_DEVICE_TYPE_WH && + parms->device_type != TF_DEVICE_TYPE_THOR && + parms->device_type != TF_DEVICE_TYPE_SR) { + TFP_DRV_LOG(ERR, + "Unsupported device type %d\n", + parms->device_type); + return -ENOTSUP; + } + + tf_dev_bind_ops(parms->device_type, &dev); + + rc = tf_msg_get_version(parms->bp, &dev, parms); + if (rc) + return rc; + + return 0; +} + diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index fb02c2b161..ba9881c69d 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -2363,4 +2363,79 @@ struct tf_get_if_tbl_entry_parms { int tf_get_if_tbl_entry(struct tf *tfp, struct tf_get_if_tbl_entry_parms *parms); +/** + * tf_get_version parameters definition. + */ +struct tf_get_version_parms { + /** + * [in] device type + * + * Device type for the session. + */ + enum tf_device_type device_type; + + /** + * [in] bp + * The pointer to the parent bp struct. This is only used for HWRM + * message passing within the portability layer. The type is struct + * bnxt. + */ + void *bp; + + /* [out] major + * + * Version Major number. + */ + uint8_t major; + + /* [out] minor + * + * Version Minor number. + */ + uint8_t minor; + + /* [out] update + * + * Version Update number. + */ + uint8_t update; + + /** + * [out] dev_ident_caps + * + * fw available identifier resource list + */ + uint32_t dev_ident_caps; + + /** + * [out] dev_tbl_caps + * + * fw available table resource list + */ + uint32_t dev_tbl_caps; + + /** + * [out] dev_tcam_caps + * + * fw available tcam resource list + */ + uint32_t dev_tcam_caps; + + /** + * [out] dev_em_caps + * + * fw available em resource list + */ + uint32_t dev_em_caps; +}; + +/** + * Get tf fw version + * + * Used to retrieve Truflow fw version information. + * + * Returns success or failure code. + */ +int tf_get_version(struct tf *tfp, + struct tf_get_version_parms *parms); #endif /* _TF_CORE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index 9b0c037db0..88bd4515ff 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -6,6 +6,7 @@ #ifndef _TF_DEVICE_H_ #define _TF_DEVICE_H_ +#include "cfa_resource_types.h" #include "tf_core.h" #include "tf_identifier.h" #include "tf_tbl.h" @@ -36,6 +37,21 @@ struct tf_dev_info { const struct tf_dev_ops *ops; }; +/** + * This structure can be used to translate the CFA resource type to TF type. + */ +struct tf_hcapi_resource_map { + /** + * Truflow module type associated with this resource type. + */ + enum tf_module_type module_type; + + /** + * Bitmap of TF sub-type for the element. + */ + uint32_t type_caps; +}; + /** * @page device Device * @@ -1037,6 +1053,34 @@ struct tf_dev_ops { */ uint64_t (*tf_dev_cfa_key_hash)(uint64_t *key_data, uint16_t bitlen); + + /** + * Translate the CFA resource type to Truflow type + * + * [in] hcapi_types + * CFA resource type bitmap + * + * [out] ident_types + * Pointer to identifier type bitmap + * + * [out] tcam_types + * Pointer to tcam type bitmap + * + * [out] tbl_types + * Pointer to table type bitmap + * + * [out] em_types + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_map_hcapi_caps)(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps); }; /** @@ -1047,4 +1091,10 @@ extern const struct tf_dev_ops tf_dev_ops_p4; extern const struct tf_dev_ops tf_dev_ops_p58_init; extern const struct tf_dev_ops tf_dev_ops_p58; +/** + * Supported device resource type mapping structures + */ +extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1]; +extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p58[CFA_RESOURCE_TYPE_P58_LAST + 1]; + #endif /* _TF_DEVICE_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 826cd0cdbc..8089785b82 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -271,6 +271,67 @@ static bool tf_dev_p4_is_sram_managed(struct tf *tfp __rte_unused, { return false; } + +/** + * Device specific function that maps the hcapi resource types + * to Truflow type. + * + * [in] hcapi_caps + * CFA resource type bitmap + * + * [out] ident_caps + * Pointer to identifier type bitmap + * + * [out] tcam_caps + * Pointer to tcam type bitmap + * + * [out] tbl_caps + * Pointer to table type bitmap + * + * [out] em_caps + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p4_map_hcapi_caps(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps) +{ + uint32_t i; + + *ident_caps = 0; + *tcam_caps = 0; + *tbl_caps = 0; + *em_caps = 0; + + for (i = 0; i <= CFA_RESOURCE_TYPE_P4_LAST; i++) { + if (hcapi_caps & 1ULL << i) { + switch (tf_hcapi_res_map_p4[i].module_type) { + case TF_MODULE_TYPE_IDENTIFIER: + *ident_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_TABLE: + *tbl_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_TCAM: + *tcam_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + case TF_MODULE_TYPE_EM: + *em_caps |= tf_hcapi_res_map_p4[i].type_caps; + break; + default: + return -EINVAL; + } + } + } + + return 0; +} + /** * Truflow P4 device specific functions */ @@ -321,6 +382,7 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = NULL, + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps }; /** @@ -382,5 +444,6 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p4_get_mailbox, .tf_dev_word_align = tf_dev_p4_word_align, - .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash + .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash, + .tf_dev_map_hcapi_caps = tf_dev_p4_map_hcapi_caps }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index c1357913f1..e84c0f9e83 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -157,4 +157,83 @@ struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = { TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK }, }; + +const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { + [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_HIGH + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_LOW + }, + [CFA_RESOURCE_TYPE_P4_PROF_FUNC] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_PROF_FUNC + }, + [CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_WC_PROF + }, + [CFA_RESOURCE_TYPE_P4_EM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_EM_PROF + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH + }, + [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW + }, + [CFA_RESOURCE_TYPE_P4_PROF_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_PROF_TCAM + }, + [CFA_RESOURCE_TYPE_P4_WC_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_WC_TCAM + }, + [CFA_RESOURCE_TYPE_P4_SP_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_SP_TCAM + }, + [CFA_RESOURCE_TYPE_P4_NAT_IPV4] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_MODIFY_IPV4 + }, + [CFA_RESOURCE_TYPE_P4_METER_PROF] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_PROF + }, + [CFA_RESOURCE_TYPE_P4_METER] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_INST + }, + [CFA_RESOURCE_TYPE_P4_MIRROR] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MIRROR_CONFIG + }, + [CFA_RESOURCE_TYPE_P4_FULL_ACTION] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_FULL_ACT_RECORD + }, + [CFA_RESOURCE_TYPE_P4_MCG] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MCAST_GROUPS + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_8B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_8B + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_16B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_16B + }, + [CFA_RESOURCE_TYPE_P4_ENCAP_64B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_64B + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV4 + }, + [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV6 + }, + [CFA_RESOURCE_TYPE_P4_COUNTER_64B] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_STATS_64 + }, + [CFA_RESOURCE_TYPE_P4_EM_REC] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_EM_RECORD + }, + [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_TBL_SCOPE + }, +}; + #endif /* _TF_DEVICE_P4_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 47d7836a58..03e72b90f5 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -45,6 +45,7 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { [CFA_RESOURCE_TYPE_P58_WC_FKB] = "wc_fkb ", [CFA_RESOURCE_TYPE_P58_VEB_TCAM] = "veb ", [CFA_RESOURCE_TYPE_P58_METADATA] = "metadata", + [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = "meter_dc", }; /** @@ -336,6 +337,66 @@ static int tf_dev_p58_get_sram_tbl_info(struct tf *tfp __rte_unused, return 0; } +/** + * Device specific function that maps the hcapi resource types + * to Truflow type. + * + * [in] hcapi_caps + * CFA resource type bitmap + * + * [out] ident_caps + * Pointer to identifier type bitmap + * + * [out] tcam_caps + * Pointer to tcam type bitmap + * + * [out] tbl_caps + * Pointer to table type bitmap + * + * [out] em_caps + * Pointer to em type bitmap + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int tf_dev_p58_map_hcapi_caps(uint64_t hcapi_caps, + uint32_t *ident_caps, + uint32_t *tcam_caps, + uint32_t *tbl_caps, + uint32_t *em_caps) +{ + uint32_t i; + + *ident_caps = 0; + *tcam_caps = 0; + *tbl_caps = 0; + *em_caps = 0; + + for (i = 0; i <= CFA_RESOURCE_TYPE_P58_LAST; i++) { + if (hcapi_caps & 1ULL << i) { + switch (tf_hcapi_res_map_p58[i].module_type) { + case TF_MODULE_TYPE_IDENTIFIER: + *ident_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_TABLE: + *tbl_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_TCAM: + *tcam_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + case TF_MODULE_TYPE_EM: + *em_caps |= tf_hcapi_res_map_p58[i].type_caps; + break; + default: + return -EINVAL; + } + } + } + + return 0; +} + /** * Truflow P58 device specific functions */ @@ -386,6 +447,7 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_global_cfg = NULL, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = NULL, + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps }; /** @@ -448,5 +510,6 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_global_cfg = tf_global_cfg_get, .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, .tf_dev_word_align = tf_dev_p58_word_align, - .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash + .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash, + .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index 3e8759f2df..f6e66936f3 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -209,4 +209,91 @@ struct tf_global_cfg_cfg tf_global_cfg_p58[TF_GLOBAL_CFG_TYPE_MAX] = { TF_GLOBAL_CFG_CFG_HCAPI, TF_METER_INTERVAL_CFG }, }; + +const struct tf_hcapi_resource_map tf_hcapi_res_map_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { + [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_HIGH + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_LOW + }, + [CFA_RESOURCE_TYPE_P58_PROF_FUNC] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_PROF_FUNC + }, + [CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_WC_PROF + }, + [CFA_RESOURCE_TYPE_P58_EM_PROF_ID] = { + TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_EM_PROF + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH + }, + [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW + }, + [CFA_RESOURCE_TYPE_P58_PROF_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_PROF_TCAM + }, + [CFA_RESOURCE_TYPE_P58_WC_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_WC_TCAM + }, + [CFA_RESOURCE_TYPE_P58_VEB_TCAM] = { + TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_VEB_TCAM + }, + [CFA_RESOURCE_TYPE_P58_EM_FKB] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_EM_FKB + }, + [CFA_RESOURCE_TYPE_P58_WC_FKB] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_WC_FKB + }, + [CFA_RESOURCE_TYPE_P58_METER_PROF] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_PROF + }, + [CFA_RESOURCE_TYPE_P58_METER] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_INST + }, + [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_DROP_CNT + }, + [CFA_RESOURCE_TYPE_P58_MIRROR] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MIRROR_CONFIG + }, + [CFA_RESOURCE_TYPE_P58_METADATA] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METADATA + }, + /* Resources in bank 1 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_1] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_FULL_ACT_RECORD + | 1 << TF_TBL_TYPE_COMPACT_ACT_RECORD + }, + /* Resources in bank 2 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_2] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_ACT_ENCAP_8B | + 1 << TF_TBL_TYPE_ACT_ENCAP_16B | + 1 << TF_TBL_TYPE_ACT_ENCAP_32B | + 1 << TF_TBL_TYPE_ACT_ENCAP_64B | + 1 << TF_TBL_TYPE_ACT_MODIFY_8B | + 1 << TF_TBL_TYPE_ACT_MODIFY_16B | + 1 << TF_TBL_TYPE_ACT_MODIFY_32B | + 1 << TF_TBL_TYPE_ACT_MODIFY_64B + + }, + /* Resources in bank 0 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_0] = { + TF_MODULE_TYPE_TABLE, + 1 << TF_TBL_TYPE_ACT_SP_SMAC | + 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV4 | + 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV6 + }, + /* Resources in bank 3 */ + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_3] = { + TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_STATS_64 + }, + [CFA_RESOURCE_TYPE_P58_EM_REC] = { + TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_EM_RECORD + }, +}; #endif /* _TF_DEVICE_P58_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index ea6e2af7ce..25bf026658 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -2306,3 +2306,38 @@ tf_msg_set_if_tbl_entry(struct tf *tfp, return 0; } + +int +tf_msg_get_version(struct bnxt *bp, + struct tf_dev_info *dev, + struct tf_get_version_parms *params) + +{ + int rc; + struct hwrm_tf_version_get_input req = { 0 }; + struct hwrm_tf_version_get_output resp = { 0 }; + struct tfp_send_msg_parms parms = { 0 }; + + /* Populate the request */ + parms.tf_type = HWRM_TF_VERSION_GET, + parms.req_data = (uint32_t *)&req; + parms.req_size = sizeof(req); + parms.resp_data = (uint32_t *)&resp; + parms.resp_size = sizeof(resp); + parms.mailbox = dev->ops->tf_dev_get_mailbox(); + + rc = tfp_send_msg_direct(bp, + &parms); + + params->major = resp.major; + params->minor = resp.minor; + params->update = resp.update; + + dev->ops->tf_dev_map_hcapi_caps(resp.dev_caps_cfg, + ¶ms->dev_ident_caps, + ¶ms->dev_tcam_caps, + ¶ms->dev_tbl_caps, + ¶ms->dev_em_caps); + + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h index 718bc2f3b2..08d20cdd7a 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.h +++ b/drivers/net/bnxt/tf_core/tf_msg.h @@ -738,4 +738,23 @@ int tf_msg_set_if_tbl_entry(struct tf *tfp, int tf_msg_get_if_tbl_entry(struct tf *tfp, struct tf_if_tbl_get_parms *params); +/** + * Send get version request to the firmware. + * + * [in] bp + * Pointer to bnxt handle + * + * [in] dev + * Pointer to the associated device + * + * [in/out] parms + * Pointer to the version info parameter + * + * Returns: + * 0 on Success else internal Truflow error + */ +int +tf_msg_get_version(struct bnxt *bp, + struct tf_dev_info *dev, + struct tf_get_version_parms *parms); #endif /* _TF_MSG_H_ */ From patchwork Fri Oct 1 05:59:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 100202 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 80E39A0C43; Fri, 1 Oct 2021 08:00:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C7AAB4115C; Fri, 1 Oct 2021 07:59:37 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.166.228]) by mails.dpdk.org (Postfix) with ESMTP id 3D1194114F for ; Fri, 1 Oct 2021 07:59:36 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 5197735FB4; Thu, 30 Sep 2021 22:59:34 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 5197735FB4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1633067975; bh=s35DhgMk8unTlsQbjJO4BJv6W+wO6EjxClfOfY0a4wk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fIjZzjon/vWj6xyrDTg7ZfiCkZyxyuopovnFc0fkoWDuDupK/WovahK6wSQOaV3k+ JfyfPIYuf6uqZzmlgwMaRmSQsLwixbbea8Fq3IPX9DcCAyMn4/gEMwPEcxeJS8h2KE 2nPKpsQK9KH5gcyr1/keWKvHmASNO2x5gD+zyj2w= From: Venkat Duvvuru To: dev@dpdk.org Cc: Shahaji Bhosle , Kishore Padmanabha , Venkat Duvvuru Date: Fri, 1 Oct 2021 11:29:09 +0530 Message-Id: <20211001055909.27276-10-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> References: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH 9/9] net/bnxt: increase scaling numbers on Thor X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shahaji Bhosle * Updated defines and data types to allow 256 VFRs. * Increased the encap record cache to support 256 to 4K entries. So vxlan connections can be scaled to 4k entries. Signed-off-by: Shahaji Bhosle Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Kishore Padmanabha Reviewed-by: Randy Schacher --- drivers/net/bnxt/bnxt.h | 6 +++++- drivers/net/bnxt/bnxt_cpr.c | 2 +- drivers/net/bnxt/bnxt_ethdev.c | 18 +++++++++--------- drivers/net/bnxt/bnxt_reps.c | 3 +-- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 2 +- .../generic_templates/ulp_template_db_tbl.c | 8 ++++---- drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 6 +++--- 7 files changed, 24 insertions(+), 21 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 9bf6697006..0209bb5c39 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -240,7 +240,11 @@ struct bnxt_parent_info { struct bnxt_pf_info { #define BNXT_FIRST_PF_FID 1 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) -#define BNXT_MAX_VF_REPS 64 +#define BNXT_MAX_VF_REPS_WH 64 +#define BNXT_MAX_VF_REPS_TH 256 +#define BNXT_MAX_VF_REPS(bp) \ + (BNXT_CHIP_P5(bp) ? BNXT_MAX_VF_REPS_TH : \ + BNXT_MAX_VF_REPS_WH) #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) #define BNXT_FIRST_VF_FID 128 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) diff --git a/drivers/net/bnxt/bnxt_cpr.c b/drivers/net/bnxt/bnxt_cpr.c index 63ff02a198..6bb70d516e 100644 --- a/drivers/net/bnxt/bnxt_cpr.c +++ b/drivers/net/bnxt/bnxt_cpr.c @@ -74,7 +74,7 @@ bnxt_process_default_vnic_change(struct bnxt *bp, BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT; PMD_DRV_LOG(INFO, "async event received vf_id 0x%x\n", vf_fid); - for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS; vf_id++) { + for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS(bp); vf_id++) { eth_dev = bp->rep_info[vf_id].vfr_eth_dev; if (!eth_dev) continue; diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 63d764f968..034f4cdcaa 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1185,7 +1185,7 @@ void bnxt_print_link_info(struct rte_eth_dev *eth_dev) struct rte_eth_link *link = ð_dev->data->dev_link; if (link->link_status) - PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", + PMD_DRV_LOG(DEBUG, "Port %d Link Up - speed %u Mbps - %s\n", eth_dev->data->port_id, (uint32_t)link->link_speed, (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? @@ -6046,7 +6046,7 @@ static int bnxt_init_rep_info(struct bnxt *bp) return 0; bp->rep_info = rte_zmalloc("bnxt_rep_info", - sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, + sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS(bp), 0); if (!bp->rep_info) { PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); @@ -6088,7 +6088,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, { struct rte_eth_dev *vf_rep_eth_dev; char name[RTE_ETH_NAME_MAX_LEN]; - struct bnxt *backing_bp; + struct bnxt *backing_bp = backing_eth_dev->data->dev_private; + uint16_t max_vf_reps = BNXT_MAX_VF_REPS(backing_bp); + uint16_t num_rep; int i, ret = 0; struct rte_kvargs *kvlist = NULL; @@ -6101,9 +6103,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, return -ENOTSUP; } num_rep = eth_da->nb_representor_ports; - if (num_rep > BNXT_MAX_VF_REPS) { + if (num_rep > max_vf_reps) { PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", - num_rep, BNXT_MAX_VF_REPS); + num_rep, max_vf_reps); return -EINVAL; } @@ -6114,8 +6116,6 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, return -EINVAL; } - backing_bp = backing_eth_dev->data->dev_private; - if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { PMD_DRV_LOG(ERR, "Not a PF or trusted VF. No Representor support\n"); @@ -6135,9 +6135,9 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, .parent_dev = backing_eth_dev }; - if (representor.vf_id >= BNXT_MAX_VF_REPS) { + if (representor.vf_id >= max_vf_reps) { PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", - representor.vf_id, BNXT_MAX_VF_REPS); + representor.vf_id, max_vf_reps); continue; } diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c index bdbad53b7d..0feefe156c 100644 --- a/drivers/net/bnxt/bnxt_reps.c +++ b/drivers/net/bnxt/bnxt_reps.c @@ -209,7 +209,6 @@ int bnxt_representor_init(struct rte_eth_dev *eth_dev, void *params) eth_dev->data->dev_link.link_status = link->link_status; eth_dev->data->dev_link.link_autoneg = link->link_autoneg; - PMD_DRV_LOG(INFO, "calling bnxt_print_link_info\n"); bnxt_print_link_info(eth_dev); PMD_DRV_LOG(INFO, @@ -818,7 +817,7 @@ int bnxt_rep_stop_all(struct bnxt *bp) if (!bp->rep_info) return 0; - for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS; vf_id++) { + for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS(bp); vf_id++) { rep_eth_dev = bp->rep_info[vf_id].vfr_eth_dev; if (!rep_eth_dev) continue; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 68f1470c61..960a5a0c93 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -262,7 +262,7 @@ bnxt_ulp_cntxt_ptr2_ulp_flags_get(struct bnxt_ulp_context *ulp_ctx, uint32_t *flags); int32_t -bnxt_ulp_get_df_rule_info(uint8_t port_id, struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_get_df_rule_info(uint16_t port_id, struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_df_rule_info *info); struct bnxt_ulp_vfr_rule_info* diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 5383e2cd70..e43e341927 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu Sep 9 11:11:05 2021 */ +/* date: Thu Sep 16 11:49:55 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -164,12 +164,12 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE", - .result_num_entries = 256, + .name = "EGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE", + .result_num_entries = 4096, .result_num_bytes = 6, .key_num_bytes = 17, .num_buckets = 8, - .hash_tbl_entries = 1024, + .hash_tbl_entries = 16384, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index d8336d164e..01233c0f5e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -441,7 +441,7 @@ void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global) { struct bnxt_ulp_df_rule_info *info; - uint8_t port_id; + uint16_t port_id; if (!BNXT_TRUFLOW_EN(bp) || BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev)) @@ -505,7 +505,7 @@ int32_t bnxt_ulp_create_df_rules(struct bnxt *bp) { struct bnxt_ulp_df_rule_info *info; - uint8_t port_id; + uint16_t port_id; int rc = 0; if (!BNXT_TRUFLOW_EN(bp) || @@ -562,7 +562,7 @@ bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev) struct rte_eth_dev *parent_dev = vfr->parent_dev; struct bnxt *bp = parent_dev->data->dev_private; uint16_t vfr_port_id = vfr_ethdev->data->port_id; - uint8_t port_id; + uint16_t port_id; int rc; if (!bp || !BNXT_TRUFLOW_EN(bp))