From patchwork Tue Oct 19 10:34:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xueming Li X-Patchwork-Id: 102175 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E3A55A0C43; Tue, 19 Oct 2021 12:35:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0DD014112E; Tue, 19 Oct 2021 12:35:37 +0200 (CEST) Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam08on2045.outbound.protection.outlook.com [40.107.102.45]) by mails.dpdk.org (Postfix) with ESMTP id B275A4113F for ; Tue, 19 Oct 2021 12:35:35 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=X+eE72ElxcrLbXPo/y/FOn4OBRAdDYj6nPcZVfgsES6CS/6VNS7n2FGoUrd7sapESQENsAzwgCkKSlGlWG85D2DAGIn9iGWOh9I3RD/yfJ7gdXdG2FTlsH7978RqmH1UuFv0Qgwsa+SxuqhNiF06YgTE7/W1FNubq/Ig4zzgBCryKvEr4L+WFY2kJLhYUsxafd502s4K0WZvalFjq2XZWcRIcDk1YS9wMFtFyVfGdl1PAKPTGRonQPgmgw9DYP2XRCVliCIGVX0jOOFy7b7JEjvx3mr1yIWu4zVYDDMuVWoBFjxYZcG/2IJK/diovAeVWUWXYvLp1dJnVwp/ozQIWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=5L9vFvHiPV8u8qi/MS7ovPawk4kOCN18Zu/1gHQ4gng=; b=FAcV5E8LsUnOG5S/wHez1FrRyz0g/Ca00XVV0ufxXNOZENg1Gg0e4/q3r7IRx/y2v/k3T25GXU6NtiGZB08gnh4IesJfcYADJE44+dUe4o0hK69Of1JBby2HeJz+sGoDh+1H8C5SZjwevGuCya4hRhuAZRM2AYkBAEK5QV/iOH0MGYzeEjfbEzo6w3mmOPgNeqzQVsH1ap2pcKMbGYKq/iZwFDxQURDhOQOzzCDdqoXmg2lVhqHymiX5mAIh90b0ir0iuRsMq9SGUPzEfC0G2diTqFR2k/WD25GrMUyKCnSLlB/iIQnT5He8sTZHoFoHJzkYXKTfIeuDPQJ2+iNEpA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=ashroe.eu smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5L9vFvHiPV8u8qi/MS7ovPawk4kOCN18Zu/1gHQ4gng=; b=Br3au3eCTTFfwQSxL1n9Pyg/3NRFapXi7hso9d7Mvs/7EXTcpTR1/fmtO+JGsDTR0XEhsmL/DQ5oK8YtOB7yYlpN0mROfjHObQp4mraVC8F+GA+kMS28m03rPEBfoGvMTJkzzl6RHnFXXAw558RANP/YuykfM+HkixuwawJP84+y4dGs/4ChRRAmw653v6hmVN1PVTpL4asQw/NMFXeihOzWUvCW6qjV3GVWs3aCBvV/qWPl30tuPn4P33XaQNk9bs4c2HjqHJzefKmxajWAUnNJ5uLwHE4l71qAAxGBR3RZ8j1rGT7upnQMcO2XfYU8Gk7i3tcz6I0eo2o3+Kz3SA== Received: from DM5PR10CA0024.namprd10.prod.outlook.com (2603:10b6:4:2::34) by SA0PR12MB4352.namprd12.prod.outlook.com (2603:10b6:806:9c::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.18; Tue, 19 Oct 2021 10:35:34 +0000 Received: from DM6NAM11FT040.eop-nam11.prod.protection.outlook.com (2603:10b6:4:2:cafe::89) by DM5PR10CA0024.outlook.office365.com (2603:10b6:4:2::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.15 via Frontend Transport; Tue, 19 Oct 2021 10:35:34 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; ashroe.eu; dkim=none (message not signed) header.d=none;ashroe.eu; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT040.mail.protection.outlook.com (10.13.173.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 10:35:33 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct 2021 10:35:28 +0000 From: Xueming Li To: CC: , Viacheslav Ovsiienko , Lior Margalit , Matan Azrad , "Ray Kinsella" Date: Tue, 19 Oct 2021 18:34:54 +0800 Message-ID: <20211019103501.2216840-2-xuemingl@nvidia.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019103501.2216840-1-xuemingl@nvidia.com> References: <20210927083256.337450-1-xuemingl@nvidia.com> <20211019103501.2216840-1-xuemingl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 51d6191c-9518-4cfd-29c9-08d992ec2e53 X-MS-TrafficTypeDiagnostic: SA0PR12MB4352: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2512; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: frxdGf0AvvdLX1qYFJ1+J/0suYJvbjFXZeVMM2UEeZ5jCKd8K8mgvTEVYti9Qj4z+lVT3aMDsBP2DV07RTfBXWqs7Ie4luF8vjlUXgJwZkUayFpsgplmB2TWEpfzS1c0rPqyWLbFGjIToqpgIrwcmsxRfFyfgBxoqXl9UU1BIkep4r9d8nsj6+z1q4kbiGQKApRW5YNAjwLIADtXE/zIizXZ3OGfAcHEkgUIhJtuh2pNixb6rWoRrpNhoUTAebGXMY7gfqIj+0WuObkvYBpSYkvnHzQF2LE3aF0MWW5BzAflwizUcg70IEKkuSqEWZLWjJ3fO8OYjjpn0xfSeANV+FqKB8ZNHL00FgDIwu4s61MJCAOmuVuZagx5Tz1Ji358znZXlRVWrRSJyaJ6aR1Oxj65x3Cuw0Y0i3vxjhZaLUSzq30996juBYZX/Uu3IDgwxO8f4Erw35huQQWM3HEXeAy5HHyjCONVnkTWNB9kq1HNfFZzmrtSNv/JFHusuncV93Iko8EWqq5fqmQlWevf5kslkUUZvwZ/4/UiVmbBmO7CgvVx1KJIyInGp/LpssxXDOWPFpy27Ax3+KttPlig8CpLIAKm1pMxbZXc5xZV6M5UV3urd3nrKqoptKO/aereyPZl5VLiyQ+RlaglZbslWRI9lA0F/Gdpb9NzCqjLNfwKXq5uKtGblRgeVBHUFk5IQLBU69JqeebS1lK0pv6kDg== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(4326008)(70206006)(1076003)(6916009)(83380400001)(55016002)(426003)(36756003)(82310400003)(2616005)(7696005)(16526019)(6666004)(86362001)(2906002)(8936002)(70586007)(54906003)(8676002)(36860700001)(26005)(186003)(47076005)(36906005)(6286002)(336012)(7636003)(356005)(316002)(5660300002)(508600001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2021 10:35:33.5615 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 51d6191c-9518-4cfd-29c9-08d992ec2e53 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4352 Subject: [dpdk-dev] [PATCH v3 1/8] common/mlx5: add netlink API to get RDMA port state X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Introduce netlink API to get rdma port state. Port state is restrieved based on RDMA device name and port index. Signed-off-by: Xueming Li Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/linux/meson.build | 2 + drivers/common/mlx5/linux/mlx5_nl.c | 136 +++++++++++++++++++------- drivers/common/mlx5/linux/mlx5_nl.h | 2 + drivers/common/mlx5/version.map | 1 + 4 files changed, 106 insertions(+), 35 deletions(-) diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build index cbea58f557d..2dcd27b7786 100644 --- a/drivers/common/mlx5/linux/meson.build +++ b/drivers/common/mlx5/linux/meson.build @@ -175,6 +175,8 @@ has_sym_args = [ 'RDMA_NLDEV_ATTR_DEV_NAME' ], [ 'HAVE_RDMA_NLDEV_ATTR_PORT_INDEX', 'rdma/rdma_netlink.h', 'RDMA_NLDEV_ATTR_PORT_INDEX' ], + [ 'HAVE_RDMA_NLDEV_ATTR_PORT_STATE', 'rdma/rdma_netlink.h', + 'RDMA_NLDEV_ATTR_PORT_STATE' ], [ 'HAVE_RDMA_NLDEV_ATTR_NDEV_INDEX', 'rdma/rdma_netlink.h', 'RDMA_NLDEV_ATTR_NDEV_INDEX' ], [ 'HAVE_MLX5_DR_FLOW_DUMP', 'infiniband/mlx5dv.h', diff --git a/drivers/common/mlx5/linux/mlx5_nl.c b/drivers/common/mlx5/linux/mlx5_nl.c index 9120a697fd5..4b762850941 100644 --- a/drivers/common/mlx5/linux/mlx5_nl.c +++ b/drivers/common/mlx5/linux/mlx5_nl.c @@ -78,6 +78,9 @@ #ifndef HAVE_RDMA_NLDEV_ATTR_PORT_INDEX #define RDMA_NLDEV_ATTR_PORT_INDEX 3 #endif +#ifndef HAVE_RDMA_NLDEV_ATTR_PORT_STATE +#define RDMA_NLDEV_ATTR_PORT_STATE 12 +#endif #ifndef HAVE_RDMA_NLDEV_ATTR_NDEV_INDEX #define RDMA_NLDEV_ATTR_NDEV_INDEX 50 #endif @@ -160,14 +163,16 @@ struct mlx5_nl_mac_addr { #define MLX5_NL_CMD_GET_IB_INDEX (1 << 1) #define MLX5_NL_CMD_GET_NET_INDEX (1 << 2) #define MLX5_NL_CMD_GET_PORT_INDEX (1 << 3) +#define MLX5_NL_CMD_GET_PORT_STATE (1 << 4) /** Data structure used by mlx5_nl_cmdget_cb(). */ -struct mlx5_nl_ifindex_data { +struct mlx5_nl_port_info { const char *name; /**< IB device name (in). */ uint32_t flags; /**< found attribute flags (out). */ uint32_t ibindex; /**< IB device index (out). */ uint32_t ifindex; /**< Network interface index (out). */ uint32_t portnum; /**< IB device max port number (out). */ + uint16_t state; /**< IB device port state (out). */ }; uint32_t atomic_sn; @@ -966,8 +971,8 @@ mlx5_nl_allmulti(int nlsk_fd, unsigned int iface_idx, int enable) static int mlx5_nl_cmdget_cb(struct nlmsghdr *nh, void *arg) { - struct mlx5_nl_ifindex_data *data = arg; - struct mlx5_nl_ifindex_data local = { + struct mlx5_nl_port_info *data = arg; + struct mlx5_nl_port_info local = { .flags = 0, }; size_t off = NLMSG_HDRLEN; @@ -1000,6 +1005,10 @@ mlx5_nl_cmdget_cb(struct nlmsghdr *nh, void *arg) local.portnum = *(uint32_t *)payload; local.flags |= MLX5_NL_CMD_GET_PORT_INDEX; break; + case RDMA_NLDEV_ATTR_PORT_STATE: + local.state = *(uint8_t *)payload; + local.flags |= MLX5_NL_CMD_GET_PORT_STATE; + break; default: break; } @@ -1016,6 +1025,7 @@ mlx5_nl_cmdget_cb(struct nlmsghdr *nh, void *arg) data->ibindex = local.ibindex; data->ifindex = local.ifindex; data->portnum = local.portnum; + data->state = local.state; } return 0; error: @@ -1024,7 +1034,7 @@ mlx5_nl_cmdget_cb(struct nlmsghdr *nh, void *arg) } /** - * Get index of network interface associated with some IB device. + * Get port info of network interface associated with some IB device. * * This is the only somewhat safe method to avoid resorting to heuristics * when faced with port representors. Unfortunately it requires at least @@ -1032,27 +1042,20 @@ mlx5_nl_cmdget_cb(struct nlmsghdr *nh, void *arg) * * @param nl * Netlink socket of the RDMA kind (NETLINK_RDMA). - * @param[in] name - * IB device name. * @param[in] pindex * IB device port index, starting from 1 + * @param[out] data + * Pointer to port info. * @return - * A valid (nonzero) interface index on success, 0 otherwise and rte_errno - * is set. + * 0 on success, negative on error and rte_errno is set. */ -unsigned int -mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex) +static int +mlx5_nl_port_info(int nl, uint32_t pindex, struct mlx5_nl_port_info *data) { - struct mlx5_nl_ifindex_data data = { - .name = name, - .flags = 0, - .ibindex = 0, /* Determined during first pass. */ - .ifindex = 0, /* Determined during second pass. */ - }; union { struct nlmsghdr nh; uint8_t buf[NLMSG_HDRLEN + - NLA_HDRLEN + NLA_ALIGN(sizeof(data.ibindex)) + + NLA_HDRLEN + NLA_ALIGN(sizeof(data->ibindex)) + NLA_HDRLEN + NLA_ALIGN(sizeof(pindex))]; } req = { .nh = { @@ -1068,24 +1071,24 @@ mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex) ret = mlx5_nl_send(nl, &req.nh, sn); if (ret < 0) - return 0; - ret = mlx5_nl_recv(nl, sn, mlx5_nl_cmdget_cb, &data); + return ret; + ret = mlx5_nl_recv(nl, sn, mlx5_nl_cmdget_cb, data); if (ret < 0) - return 0; - if (!(data.flags & MLX5_NL_CMD_GET_IB_NAME) || - !(data.flags & MLX5_NL_CMD_GET_IB_INDEX)) + return ret; + if (!(data->flags & MLX5_NL_CMD_GET_IB_NAME) || + !(data->flags & MLX5_NL_CMD_GET_IB_INDEX)) goto error; - data.flags = 0; + data->flags = 0; sn = MLX5_NL_SN_GENERATE; req.nh.nlmsg_type = RDMA_NL_GET_TYPE(RDMA_NL_NLDEV, RDMA_NLDEV_CMD_PORT_GET); req.nh.nlmsg_flags = NLM_F_REQUEST | NLM_F_ACK; req.nh.nlmsg_len = NLMSG_LENGTH(sizeof(req.buf) - NLMSG_HDRLEN); na = (void *)((uintptr_t)req.buf + NLMSG_HDRLEN); - na->nla_len = NLA_HDRLEN + sizeof(data.ibindex); + na->nla_len = NLA_HDRLEN + sizeof(data->ibindex); na->nla_type = RDMA_NLDEV_ATTR_DEV_INDEX; memcpy((void *)((uintptr_t)na + NLA_HDRLEN), - &data.ibindex, sizeof(data.ibindex)); + &data->ibindex, sizeof(data->ibindex)); na = (void *)((uintptr_t)na + NLA_ALIGN(na->nla_len)); na->nla_len = NLA_HDRLEN + sizeof(pindex); na->nla_type = RDMA_NLDEV_ATTR_PORT_INDEX; @@ -1093,19 +1096,82 @@ mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex) &pindex, sizeof(pindex)); ret = mlx5_nl_send(nl, &req.nh, sn); if (ret < 0) - return 0; - ret = mlx5_nl_recv(nl, sn, mlx5_nl_cmdget_cb, &data); + return ret; + ret = mlx5_nl_recv(nl, sn, mlx5_nl_cmdget_cb, data); if (ret < 0) - return 0; - if (!(data.flags & MLX5_NL_CMD_GET_IB_NAME) || - !(data.flags & MLX5_NL_CMD_GET_IB_INDEX) || - !(data.flags & MLX5_NL_CMD_GET_NET_INDEX) || - !data.ifindex) + return ret; + if (!(data->flags & MLX5_NL_CMD_GET_IB_NAME) || + !(data->flags & MLX5_NL_CMD_GET_IB_INDEX) || + !(data->flags & MLX5_NL_CMD_GET_NET_INDEX) || + !data->ifindex) goto error; - return data.ifindex; + return 1; error: rte_errno = ENODEV; - return 0; + return -rte_errno; +} + +/** + * Get index of network interface associated with some IB device. + * + * This is the only somewhat safe method to avoid resorting to heuristics + * when faced with port representors. Unfortunately it requires at least + * Linux 4.17. + * + * @param nl + * Netlink socket of the RDMA kind (NETLINK_RDMA). + * @param[in] name + * IB device name. + * @param[in] pindex + * IB device port index, starting from 1 + * @return + * A valid (nonzero) interface index on success, 0 otherwise and rte_errno + * is set. + */ +unsigned int +mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex) +{ + struct mlx5_nl_port_info data = { + .ifindex = 0, + .name = name, + }; + + if (mlx5_nl_port_info(nl, pindex, &data) < 0) + return 0; + return data.ifindex; +} + +/** + * Get IB device port state. + * + * This is the only somewhat safe method to get info for port number >= 255. + * Unfortunately it requires at least Linux 4.17. + * + * @param nl + * Netlink socket of the RDMA kind (NETLINK_RDMA). + * @param[in] name + * IB device name. + * @param[in] pindex + * IB device port index, starting from 1 + * @return + * Port state (ibv_port_state) on success, negative on error + * and rte_errno is set. + */ +int +mlx5_nl_port_state(int nl, const char *name, uint32_t pindex) +{ + struct mlx5_nl_port_info data = { + .state = 0, + .name = name, + }; + + if (mlx5_nl_port_info(nl, pindex, &data) < 0) + return -rte_errno; + if ((data.flags & MLX5_NL_CMD_GET_PORT_STATE) == 0) { + rte_errno = ENOTSUP; + return -rte_errno; + } + return (int)data.state; } /** @@ -1123,7 +1189,7 @@ mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex) unsigned int mlx5_nl_portnum(int nl, const char *name) { - struct mlx5_nl_ifindex_data data = { + struct mlx5_nl_port_info data = { .flags = 0, .name = name, .ifindex = 0, diff --git a/drivers/common/mlx5/linux/mlx5_nl.h b/drivers/common/mlx5/linux/mlx5_nl.h index 15129ffdc88..396f8f3f20a 100644 --- a/drivers/common/mlx5/linux/mlx5_nl.h +++ b/drivers/common/mlx5/linux/mlx5_nl.h @@ -54,6 +54,8 @@ unsigned int mlx5_nl_portnum(int nl, const char *name); __rte_internal unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex); __rte_internal +int mlx5_nl_port_state(int nl, const char *name, uint32_t pindex); +__rte_internal int mlx5_nl_vf_mac_addr_modify(int nlsk_fd, unsigned int iface_idx, struct rte_ether_addr *mac, int vf_index); __rte_internal diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index d3c5040aac8..2a2c7e51ba5 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -134,6 +134,7 @@ INTERNAL { mlx5_nl_mac_addr_flush; # WINDOWS_NO_EXPORT mlx5_nl_mac_addr_remove; # WINDOWS_NO_EXPORT mlx5_nl_mac_addr_sync; # WINDOWS_NO_EXPORT + mlx5_nl_port_state; # WINDOWS_NO_EXPORT mlx5_nl_portnum; # WINDOWS_NO_EXPORT mlx5_nl_promisc; # WINDOWS_NO_EXPORT mlx5_nl_switch_info; # WINDOWS_NO_EXPORT From patchwork Tue Oct 19 10:34:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xueming Li X-Patchwork-Id: 102176 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4751CA0C43; Tue, 19 Oct 2021 12:35:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 34F4F4113A; Tue, 19 Oct 2021 12:35:51 +0200 (CEST) Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2043.outbound.protection.outlook.com [40.107.243.43]) by mails.dpdk.org (Postfix) with ESMTP id 8868141125 for ; Tue, 19 Oct 2021 12:35:49 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=gZT+p5LAouZzFaByYeewGc0n6o0hopXZv+3tvdwP24X6VnZ9k1dsbawEClg+JKU2P+mjF51/mwnjf6Cpuqd9GbWHWVifSFy1G1N1i6Z42KIWRIlOPUbj2sZ0SHkk2xoBHyyGGBIe5ojZ7UXMM9xGNGAfbMVbe41DuOyQxo9F3xWW4LC1f2NEmF3tn+OjCJ4I9OH/6/i5A0sBbYxs2IFpbC0Iqhx/X0ULS1K3uhB8HwKj0d743GrngWexeWnwDhTDBfQtbK2taupz+Kn3anEaOFwv9KRSeEp3BBBL7bNhELIE9terP9BSTZGjZmk8A834deuqmpBlqIM93gTZNoxHXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=V+R9at4aF29P5QfuGDKd1QrNyBYntfiPsuynovN+wCw=; b=J6hf5ILWnlqP72f9z71o/YYrJnloJk5k+MiZF8kD4digSUXINLREDItox86AbgQQ4KNZpxs2jb2sIuMcg2ktdmLHX2i/lup/S0zb9wIgXhRVpaR02tmEkUVIgAGEXUkgCcHK7M6CLOC3ZizUBBwHZgYPwR43VfxRiR6Y5b50zZSANW9q6Q/cuZ4MlprR8p9IziFzzjY+oyEUZmEmFtj9O+3Bd/Wc95WPfHagYWVDDVnwq5vyFqNbSmg9bex34ZeZwWYtduL+i+drJ12QYagkk5TKz5JmFetDjK5ATVOTAgceDyaaAY2YYmI5NslfAoLZdsDcSgQRFqzaVNhuL6Qcyw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=V+R9at4aF29P5QfuGDKd1QrNyBYntfiPsuynovN+wCw=; b=tO6AO6NE4K6mLkA7bU4ks2PtqqEjZ3zc+ZI2AGo6l0D4h7vlefslsL4K2YaaT2dM3VeMFOr8I0SH5HjfXpGXaXjsBV+bQvw04GhNHutzovJYb51EzFSzZhNk2D/SN5emfa5NJrzue5t1bVUB55LPbnD3GZP4Jn/X+cyom7nIkiBUPeIMcA38mcMZHQpYB8wjjRuFqTO/XoMRi/+tLUEcCXgvTq76u6n6I/n4t+LU++GPAH1hr8iUd+s1jsOtn9fzm2Aojk/m7/oUrWfhB62BvwXtMfJ8M8ysSaRCcCGdul6gdmZ0RinjCdATIrM6mB6m0v5wz4AHrj9ZoDzLRUSUcQ== Received: from DM5PR2201CA0004.namprd22.prod.outlook.com (2603:10b6:4:14::14) by CH2PR12MB4101.namprd12.prod.outlook.com (2603:10b6:610:a8::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.18; Tue, 19 Oct 2021 10:35:48 +0000 Received: from DM6NAM11FT017.eop-nam11.prod.protection.outlook.com (2603:10b6:4:14:cafe::91) by DM5PR2201CA0004.outlook.office365.com (2603:10b6:4:14::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.15 via Frontend Transport; Tue, 19 Oct 2021 10:35:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT017.mail.protection.outlook.com (10.13.172.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 10:35:48 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct 2021 10:35:33 +0000 From: Xueming Li To: CC: , Viacheslav Ovsiienko , Lior Margalit , Matan Azrad Date: Tue, 19 Oct 2021 18:34:55 +0800 Message-ID: <20211019103501.2216840-3-xuemingl@nvidia.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019103501.2216840-1-xuemingl@nvidia.com> References: <20210927083256.337450-1-xuemingl@nvidia.com> <20211019103501.2216840-1-xuemingl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 91e0b0b9-5b8a-4db4-7b9c-08d992ec36ef X-MS-TrafficTypeDiagnostic: CH2PR12MB4101: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2399; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: aYXMpY6/RMDHtjeHn5kxZb8Siu49ny7y9lMsee5n55Gq0SbM0ghkPix6avT+mNK4tUfaiEyHrQuTDrBEr3XQEW6/hu0QZgvfK9J7hD9pU7WW80aabPQ0OaBtvyry9KdGe2PJlXzuxapJIJnPXhWVnUeLeiuZzVtYSXTthsturYupU/M3TUtxkhyHinwJKi7uNLw0WOXdzi6yEGSnf4XAwS9vHKLi4O0IoXhEt2G5Fjiqg1AubPaKRl5F9eDMNoGBRaEd1m39n6D9waocZE3r1SaT+hbPQZSWD++4iPq/i9iYITekD1w/WRn0TIKMt5jRF2IJKVJEmhmifsBVmDDtpVLiF6I3Xra0Uxul+LY/+HO621oRSBZhwB5nmMJiROCFaqEzDqNRX7wCqE8oNL/v2JAXhSq89kwwIEFsI1igGkdmliFXzmuQbhZxC+OBhXn+fSKuoF2/Ii6rBy3iKsZ+LiZKZcQeJAeH39qniWIQ/Sxn1DmcBCLX9Y7PkwQce9S604gojesKXJ0okDaFGQsFw0ycGdXi3GYT5qvJxhYYbtW9vETj7safqcQ2hNfEO8MOUzfTf8thls6EL2FNXrTqzQ5KTfAwJTTgmayrkF+be9oH/vrkqk78azTjN6bkVMh+QHSQRfOdbuZg93NW+A81wkIg8JbDIUKV47KF9/luua3buJHt4V9ugNMZyTRsoqjiEnK9d0WOXSCGScRfDQwld/QAwS1+2LW1ZfCk0w5fuAw= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(5660300002)(426003)(8676002)(7636003)(2906002)(26005)(47076005)(8936002)(186003)(316002)(356005)(6286002)(36906005)(16526019)(82310400003)(36860700001)(7696005)(54906003)(2616005)(508600001)(6916009)(1076003)(86362001)(55016002)(336012)(83380400001)(6666004)(107886003)(36756003)(70586007)(70206006)(4326008)(309714004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2021 10:35:48.0158 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 91e0b0b9-5b8a-4db4-7b9c-08d992ec36ef X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4101 Subject: [dpdk-dev] [PATCH v3 2/8] net/mlx5: use netlink when IB port greater than 255 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" IB spec doesn't allow 255 ports on a single HCA, port number of 256 was cast to u8 value 0 which invalid to ibv_query_port() This patch invokes Netlink api to query port state when port number greater than 255. Signed-off-by: Xueming Li Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/linux/mlx5_os.c | 46 ++++++++++++++++++++++---------- 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 3746057673d..f283a3779cc 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -956,7 +956,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, { const struct mlx5_switch_info *switch_info = &spawn->info; struct mlx5_dev_ctx_shared *sh = NULL; - struct ibv_port_attr port_attr; + struct ibv_port_attr port_attr = { .state = IBV_PORT_NOP }; struct mlx5dv_context dv_attr = { .comp_mask = 0 }; struct rte_eth_dev *eth_dev = NULL; struct mlx5_priv *priv = NULL; @@ -976,6 +976,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, int own_domain_id = 0; uint16_t port_id; struct mlx5_port_info vport_info = { .query_flags = 0 }; + int nl_rdma = -1; int i; /* Determine if this port representor is supposed to be spawned. */ @@ -1170,19 +1171,36 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, " old OFED/rdma-core version or firmware configuration"); #endif config->mpls_en = mpls_en; + nl_rdma = mlx5_nl_init(NETLINK_RDMA); /* Check port status. */ - err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); - if (err) { - DRV_LOG(ERR, "port query failed: %s", strerror(err)); - goto error; - } - if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { - DRV_LOG(ERR, "port is not configured in Ethernet mode"); - err = EINVAL; - goto error; + if (spawn->phys_port <= UINT8_MAX) { + /* Legacy Verbs api only support u8 port number. */ + err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, + &port_attr); + if (err) { + DRV_LOG(ERR, "port query failed: %s", strerror(err)); + goto error; + } + if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { + DRV_LOG(ERR, "port is not configured in Ethernet mode"); + err = EINVAL; + goto error; + } + } else if (nl_rdma >= 0) { + /* IB doesn't allow more than 255 ports, must be Ethernet. */ + err = mlx5_nl_port_state(nl_rdma, + ((struct ibv_device *)spawn->phys_dev)->name, + spawn->phys_port); + if (err < 0) { + DRV_LOG(INFO, "Failed to get netlink port state: %s", + strerror(rte_errno)); + err = -rte_errno; + goto error; + } + port_attr.state = (enum ibv_port_state)err; } if (port_attr.state != IBV_PORT_ACTIVE) - DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", + DRV_LOG(INFO, "port is not active: \"%s\" (%d)", mlx5_glue->port_state_str(port_attr.state), port_attr.state); /* Allocate private eth device data. */ @@ -1199,7 +1217,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, priv->pci_dev = spawn->pci_dev; priv->mtu = RTE_ETHER_MTU; /* Some internal functions rely on Netlink sockets, open them now. */ - priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); + priv->nl_socket_rdma = nl_rdma; priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); priv->representor = !!switch_info->representor; priv->master = !!switch_info->master; @@ -1910,8 +1928,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, mlx5_os_free_shared_dr(priv); if (priv->nl_socket_route >= 0) close(priv->nl_socket_route); - if (priv->nl_socket_rdma >= 0) - close(priv->nl_socket_rdma); if (priv->vmwa_context) mlx5_vlan_vmwa_exit(priv->vmwa_context); if (eth_dev && priv->drop_queue.hrxq) @@ -1935,6 +1951,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, } if (sh) mlx5_free_shared_dev_ctx(sh); + if (nl_rdma >= 0) + close(nl_rdma); MLX5_ASSERT(err > 0); rte_errno = err; return NULL; From patchwork Tue Oct 19 10:34:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xueming Li X-Patchwork-Id: 102177 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A9165A0C43; Tue, 19 Oct 2021 12:35:55 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3DEB44114B; Tue, 19 Oct 2021 12:35:53 +0200 (CEST) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2044.outbound.protection.outlook.com [40.107.223.44]) by mails.dpdk.org (Postfix) with ESMTP id 1608540683 for ; Tue, 19 Oct 2021 12:35:51 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HdBPerpgR2s/QK7jTGfoAN6d27J87DsC2Mkb9DccEYjzS7jvfXZKkLyW2rYEhDSodL5jJ3kb4v8/JW29sL2WuwYQ8zm4sK9NVlhrwl18SZsFg64GLi8K0mqgPG9A1TBQTskY2wm4klLoeiZc48UIFOIIdTlVncCz2e1vERl9TRfen2/y3OZ2XzKKIj5wrJ4WjyjIkhb6TNIp/nq38Iu2grixpByFu+bXdje5i0XmIZfsyeFYowwclp7c5yMr2IZZNR6xO5XtU5bflHORnF6PLyMbrBeIVdhDuyc5+RfEldJ3ewQdpLR3zBRSp7pegcm2vZ4ZW296ujtcbiNe3RbAFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rzBpXYfbqABE5z2Xz93mgxYlzCnCO/iSSInw6GNVaSM=; b=ZMaCfZR2ifkYaq9BiKnwM9rxGyiVx5lIbAGu/32tQLaRL0eeF8Y2bqm6RNkfvAOGJP1Ax3BrBnccBNf2GiMZWndOClVLZ8qNWhYFYctPJzpm+ydqNY6elLT3v9A6nhx9Wn6mjbH0YszPKWj31tw4IAsKObDPedTF3Q/vE280gfVLcQ9HgzEAF1yUt29Z6RygQtsp1EMbXxgl5G5GUQfudbMMPfF++6v5HDQO1mWO0Fhs6LE2pinKrLY5iLCmq5m9Lj69PLsMFNdLa4Qc/v98STK7dDbMEFm14ytS2tMO84ejjywE467PtEHH7TVJfafAvcO6Dtq+N4ZDQsQJGuGHMQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rzBpXYfbqABE5z2Xz93mgxYlzCnCO/iSSInw6GNVaSM=; b=XTP8Rq0A1vEhkPzoiXCww/hCZM8l6MCEEEh01Y1a7O3SQIYf8LvYscAvyfaLvA8h6q3zRoWRjXgVtbgA0TqyL6vXn5ez/e+MefEPKPxhroiVlwChWBTAiB5Exi/36kLcGySNgqdsSkhww8qsomgiCvAlTtD8G17sxAiyJjg/SMXX3rtWNVDaawGmylxMbCNuLLQV1PZVEKiOvGWb8AojTmQLbdcFNPYxHwz47/95RQH6lWZBhrnqXMfo610xo9Az96U//YtrESnbvTjGn+TWAt+A70HDeduJIlh1V8Bis69E7LqvEaUa1bvuQ/YoZVf7gI4NUqIpE+xh46R8jPNMUw== Received: from DM5PR2201CA0002.namprd22.prod.outlook.com (2603:10b6:4:14::12) by SJ0PR12MB5472.namprd12.prod.outlook.com (2603:10b6:a03:3bb::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.16; Tue, 19 Oct 2021 10:35:48 +0000 Received: from DM6NAM11FT017.eop-nam11.prod.protection.outlook.com (2603:10b6:4:14:cafe::b0) by DM5PR2201CA0002.outlook.office365.com (2603:10b6:4:14::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.16 via Frontend Transport; Tue, 19 Oct 2021 10:35:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT017.mail.protection.outlook.com (10.13.172.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 10:35:48 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct 2021 10:35:37 +0000 From: Xueming Li To: CC: , Viacheslav Ovsiienko , Lior Margalit , Matan Azrad Date: Tue, 19 Oct 2021 18:34:56 +0800 Message-ID: <20211019103501.2216840-4-xuemingl@nvidia.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019103501.2216840-1-xuemingl@nvidia.com> References: <20210927083256.337450-1-xuemingl@nvidia.com> <20211019103501.2216840-1-xuemingl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 582deb3b-0608-4f11-4ac3-08d992ec3739 X-MS-TrafficTypeDiagnostic: SJ0PR12MB5472: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2201; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uQZlc23RVRTmbRGD+zDToSZ0n0dUwpM2FT/ndjmnJxXYtAsEz44FbMvKYOB0ih4XHHPvSTJ28htCLYOnYq3O2Qf6GTed5urL6x1jf3k2igkekEnAATMWaI99RhGs5s6NfG/bxqeiv1JQrbS53HANRWzx4SHr9GuN1deDM/skSP5ON0vWZIa/NoPzxdqKs9t+EnjCEwC3E2rB9XRz9KK1mPa2viSqBLevlr/Jjrvi/+qPR/e2EPVqjnIser5xrgapiMghOlZRb6zZKvuVVdFnijCtQBLRC9y+M+zjzsEXd30ZKtD9Ulrg9Bz6Uz4+N4Qk8IJ3ncgr2gB+3bxj66gTBE+V/Xg0gM6B+LQ5hODyQ19jfqrD+2/zhv1fK6BGnVYmtyT1i92e3eYkc0KgP4tWCuL6d9g3YvsaRBmUyo9TBCbjnX9+tKoPXSBlrHeNwGwPN73EFoe3AORzrlGw2OZK7ueL3yQ486++FqBDpr85hZGAbkjkjuRmVmuqhPRe53SAuyiM5amalyzqnUtnI2j3JAFHOOb9rlCD+4uvdq6tqt3odhZWeDq+MDMKKt5/JM6nhLo8jKfZ/LWF63HzQ93CjsKn/jhPy0SYSFHxq5d3UoBjTmsGsu2jCIRfeXeFi+js2/Pa2GpUtyPoQ7cn3Zx4J34ngd7lKVMrRD6y8IlO0Xj072zj1jI5GeBcVAaKXAHYFzPJpR5vGiwXzrfl1YVIFw== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(107886003)(7696005)(16526019)(186003)(4326008)(55016002)(26005)(5660300002)(54906003)(2906002)(70206006)(6286002)(36906005)(316002)(426003)(356005)(8936002)(70586007)(47076005)(36756003)(8676002)(6666004)(86362001)(6916009)(7636003)(508600001)(2616005)(83380400001)(82310400003)(1076003)(336012)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2021 10:35:48.5025 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 582deb3b-0608-4f11-4ac3-08d992ec3739 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5472 Subject: [dpdk-dev] [PATCH v3 3/8] net/mlx5: improve Verbs flow priority discover for scalable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" To detect number flow Verbs flow priorities, PMD try to create Verbs flows in different priority. While Verbs is not designed to support ports larger than 255. When DevX supported by kernel driver, 16 Verbs priorities must be supported, no need to create Verbs flows. Signed-off-by: Xueming Li Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_verbs.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c index b93fd4d2c96..f265e176940 100644 --- a/drivers/net/mlx5/mlx5_flow_verbs.c +++ b/drivers/net/mlx5/mlx5_flow_verbs.c @@ -83,6 +83,11 @@ mlx5_flow_discover_priorities(struct rte_eth_dev *dev) int i; int priority = 0; +#if defined(HAVE_MLX5DV_DR_DEVX_PORT) || defined(HAVE_MLX5DV_DR_DEVX_PORT_V35) + /* If DevX supported, driver must support 16 verbs flow priorities. */ + priority = 16; + goto out; +#endif if (!drop->qp) { rte_errno = ENOTSUP; return -rte_errno; @@ -109,6 +114,9 @@ mlx5_flow_discover_priorities(struct rte_eth_dev *dev) dev->data->port_id, priority); return -rte_errno; } +#if defined(HAVE_MLX5DV_DR_DEVX_PORT) || defined(HAVE_MLX5DV_DR_DEVX_PORT_V35) +out: +#endif DRV_LOG(INFO, "port %u supported flow priorities:" " 0-%d for ingress or egress root table," " 0-%d for non-root table or transfer root table.", From patchwork Tue Oct 19 10:34:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xueming Li X-Patchwork-Id: 102178 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C5E89A0C43; Tue, 19 Oct 2021 12:36:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 50F1F41151; Tue, 19 Oct 2021 12:35:54 +0200 (CEST) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by mails.dpdk.org (Postfix) with ESMTP id 3BA074113F for ; Tue, 19 Oct 2021 12:35:51 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jN+g4mpRthCWjQI8oPL+T12axIV990AWTYLjS+PTuUpyQhUx9gNYJAFOG5zuW12IKqfHVSZSmntlINvCTKuJCdWkgetYspW/n2tBE8vO4f10Df2iTfvfPUSy8cOGiiOPEbXLzO2NOvhd38j73Cca93n+boe22DR7XsKW77RXGdEuQgUF/RtPImLwWA4dVzOvtDw84N8F7o9Dj8dwO+598vzf+2rOedS2/yVQ7c5Jz3/TuRT/SjhvN0WUhQ35d4N/bZlQVyAYKqCEgbgg8QK6NMSmTqDrcp8mP0D6wprS4GzFmbXEcHGkvoSj5eKfVetqJWxZMTeKMxVr3yM3Psc37g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fl7g0E/Q2kj9bO094Z2B+ZROFPYBfoLFIyYIbOLogQQ=; b=VDHDx6RETEefUOBBCGRtR9CNzDiGMdu1vcM8e5vyVIrdWeog/gXveM4pHOXuNEZA85UsPgEiT1pDT4SxN2YFNg1KwL3eFa/qFnacPqXrEbPSoEL4Pc0SE/DxaIHqRNBJc9VMX9Agpon2ckh/F7ovE7O0ID3gLCJdHLXHuk4fG6psDhi+VASjSrDlTjBo/xHdJGp85EYanctWA4z7T3276czITDQJ1Y29kZiabpPrgLABMMVbNORVeK/S7g/T8+Ur5EW37zO+ri7fBn0n/ZVmJDGJhQAc964n/69QfAxKtTS6n10yAQek8PRojmecWwVcbb5X7610rz2ZWYFdbMMJDA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fl7g0E/Q2kj9bO094Z2B+ZROFPYBfoLFIyYIbOLogQQ=; b=FdFyiKNrJ3kjI0l4kvKEPLz+71NPfdcvaBaLcDMr6iPVEJwI60W+9L43uVi9Nip8eQCrvM+v/Fo7F0PG+VBd/NMb8SRZlCZaDRFFNXzSp5aBlwEpJXMcrB3zpE3I6xgg/Fzp78bGHwlCHapHToK4gc0+BiFRdkGjcJaAFtEbAb/TiQ4271RQ90SvDpNCHfIlPzgS0bpsf88XAT7RSqkh4LkiCpxKfTY9Dzozjv3QpCoP4GdMRKcn3fm6JEztXY2pnOe5OFAa4kGnIrxNtIcw46VeYiVqt/ju2woqyJsB9hqQWtx0+Bnpea/xiNn1PNMZTkRrxaTlEiUhQCthBfkzlg== Received: from DM5PR2201CA0002.namprd22.prod.outlook.com (2603:10b6:4:14::12) by MWHPR12MB1293.namprd12.prod.outlook.com (2603:10b6:300:9::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.17; Tue, 19 Oct 2021 10:35:49 +0000 Received: from DM6NAM11FT017.eop-nam11.prod.protection.outlook.com (2603:10b6:4:14:cafe::2e) by DM5PR2201CA0002.outlook.office365.com (2603:10b6:4:14::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.16 via Frontend Transport; Tue, 19 Oct 2021 10:35:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT017.mail.protection.outlook.com (10.13.172.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 10:35:49 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct 2021 10:35:40 +0000 From: Xueming Li To: CC: , Viacheslav Ovsiienko , Lior Margalit , Matan Azrad Date: Tue, 19 Oct 2021 18:34:57 +0800 Message-ID: <20211019103501.2216840-5-xuemingl@nvidia.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019103501.2216840-1-xuemingl@nvidia.com> References: <20210927083256.337450-1-xuemingl@nvidia.com> <20211019103501.2216840-1-xuemingl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d01e16a4-3f2a-4baf-c68f-08d992ec37ca X-MS-TrafficTypeDiagnostic: MWHPR12MB1293: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3631; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: S8xgO4eekRlkWVKzri2OSefCAFCWD9UpGsdX1B5mfSPHol6FeL48zz3w/QI8cUEy4krzV7zRrdyIbCAtXkRDe6fMo8/UDxAefZ5pRvcEkeJjKyzREMZF0Nkk+DH5Q1jM/ZywSbAwQ5a2ucIrMpuRt+LIYUT1HyFDGyxOr8/t0LYdzeRZWBQovFPApqdCR/++BU5lyqGOKkCR8hiXDqvZzCtmlBtNNXFmFLY7G2Uw7uTfYc5oIyQVyVGyuRYnLp6dyjSZNDYLooigJ2jVChW/QgC7a88f388bNG9IVC8nUE45jwEIVNJUXqnoIZJ9WknEVIDzGJ20w/nIDihgFrLGCOyTRYZ5rI8j5sBwsHlwGZeFjo3Ku3dxBzLaXhnO4G68JuGM7YIPctUOKlgk5tNn9OCZoAchYqBEq5bTivFmdFV8LKeHv5Z2sJTu6KY9R07TEHgrzaw0iQV/JA7JlJZOSDtuHL8aPPKkvy1QlbahAVkCgcA3GD8iaBbouKY7xEcSNEnDqjnN6HSZTLj9WnmnUQVmxCTmJ0l8Rwrq/+a3lx8tBBleuxaKePYse8oL7bcV21Rwx/N8XdjGreM0tn3mr59CYJrRUtc7OIY7dc3+hCKPrE8ZJEJ26Q1M5u0WO7RpdVfyV25HzIp+092ApMzH+Hc9KBiQCzPvKWZlhyTxEA3Szkowvbw+DkS/BHQn26eLuzxp3Y359nZt6ETmNfoDvg== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(26005)(356005)(8936002)(70206006)(2616005)(426003)(86362001)(8676002)(1076003)(36756003)(7696005)(336012)(70586007)(47076005)(55016002)(6286002)(82310400003)(6666004)(2906002)(6916009)(5660300002)(36906005)(316002)(7636003)(107886003)(508600001)(54906003)(4326008)(36860700001)(186003)(16526019)(83380400001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2021 10:35:49.4489 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d01e16a4-3f2a-4baf-c68f-08d992ec37ca X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1293 Subject: [dpdk-dev] [PATCH v3 4/8] net/mlx5: support E-Switch manager egress traffic match X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" For egress packet on representor, the vport ID in transport domain is E-Switch manager vport ID since representor shares resources of E-Switch manager. E-Switch manager vport ID and Tx queue internal device index are used to match representor egress packet. This patch adds flow item port ID match on E-Switch manager. E-Switch manager vport ID is 0xfffe on BlueField, 0 otherwise. Signed-off-by: Xueming Li Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow.h | 3 +++ drivers/net/mlx5/mlx5_flow_dv.c | 25 +++++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 5c68d4f7d74..c25af8d9864 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -18,6 +18,9 @@ #include "mlx5.h" +/* E-Switch Manager port, used for rte_flow_item_port_id. */ +#define MLX5_PORT_ESW_MGR UINT32_MAX + /* Private rte flow items. */ enum mlx5_rte_flow_item_type { MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN, diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index c6370cd1d68..f06ce54f7e7 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -92,6 +93,23 @@ static int flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev, uint32_t rix_jump); +static int16_t +flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + + if (priv->pci_dev == NULL) + return 0; + switch (priv->pci_dev->id.device_id) { + case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF: + case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF: + case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF: + return (int16_t)0xfffe; + default: + return 0; + } +} + /** * Initialize flow attributes structure according to flow items' types. * @@ -2224,6 +2242,8 @@ flow_dv_validate_item_port_id(struct rte_eth_dev *dev, return ret; if (!spec) return 0; + if (spec->id == MLX5_PORT_ESW_MGR) + return 0; esw_priv = mlx5_port_to_eswitch_info(spec->id, false); if (!esw_priv) return rte_flow_error_set(error, rte_errno, @@ -9685,6 +9705,11 @@ flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher, struct mlx5_priv *priv; uint16_t mask, id; + if (pid_v && pid_v->id == MLX5_PORT_ESW_MGR) { + flow_dv_translate_item_source_vport(matcher, key, + flow_dv_get_esw_manager_vport_id(dev), 0xffff); + return 0; + } mask = pid_m ? pid_m->id : 0xffff; id = pid_v ? pid_v->id : dev->data->port_id; priv = mlx5_port_to_eswitch_info(id, item == NULL); From patchwork Tue Oct 19 10:34:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xueming Li X-Patchwork-Id: 102179 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DAB88A0C43; Tue, 19 Oct 2021 12:36:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C307D40E2D; Tue, 19 Oct 2021 12:36:18 +0200 (CEST) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2075.outbound.protection.outlook.com [40.107.94.75]) by mails.dpdk.org (Postfix) with ESMTP id 1E74A40683 for ; Tue, 19 Oct 2021 12:36:17 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WkR4NfBls1GoG2p8TU7EfSXigdHAlBybv+3QTjCHdT9A/Y6ZMgIlm6CFYSJBFel3KLN2EU+eVUq3DieO/sQ+aGVC4eYZDO6WIZ0Ph9UfN/oobsnzs2bMzdSQKMokTwT5d2jIQPsOcjWQZ/G9N769U+ZrXh2dTr91mDT5gFAXE3JmROTkM9YzpyOxOdpWozYWPyhqGAAgLOI9+UY+ktYvE7FUF+8rXhHOJvdAV+PS0eTGzZd9/8ARZs6GQPMkEx8BLSAkwKLHGlXj01xD8W0eAYr7sAUcyheQ4in4byRPMhpXjUslms0Y2BcNDYeCloIRZCKSTOUKgkLljnvggHXKZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uXn7gx4x5e4avZzcqMI2avFSIwitxwLtqghREPxRsE0=; b=Rc1nz4DoFxLKYevoWNUudPd6Yn6bhEFzWGGCatwOqPS8upxEnAMNqGD0jOqPcKPMqn/xGoKX3nGkKqKP2o/tZF5orDManxBwZIO2bVI4TDOdvFR3pqW7+Rc0AIMXlcbN+rFVGyjS+9mB24PMyHHxekFS3Fd5Na82ShRhXwIigND232LZnNQnAmC4o8OEFkWZW0+3PMAa9+oG9DWIk6bFrPljWklo4mEmhS/EDTl5IZi+bMgJBZX5+Ki0+Gv9fp8WGTiVbXvv6yfAaQii08RrOimikGJXlhwfPnc3QPLcffQRUe7VHKb7i0IfnE1WBqTHLIQ/vHmJfzzVnmzagGeQ9Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uXn7gx4x5e4avZzcqMI2avFSIwitxwLtqghREPxRsE0=; b=hbNveSNTIhP4gMQUKQkzoLKgOTMUE23xkkZ5jadLpC9xSWv/VAqA1+ZsBv2CPZ0ROWzdgKf/AtHiFLu/WLRYhsgXpJu12b42JpxqlEemHL9a/C+TaKkL7r2VvdaL3PShOMc0e+CspJXvMECqhiljRAiXEr/1W17dkJ+Vdb8nTLgkLVgIVEcMNokZW7sg5ZR6+cw43tcSm7+zeUwyHz5EI6/LbZ2iHqOOGWmRFGi2QD2Y1DAXgcEYlHjRjV1SKSqeSrfkacsqUl16tuzZQaC6xqBYABKpWrY2nSRtdzF4IXIDv5TpHgxYB8m9eXJnwMH5dCeC7VF12o/y7t+9nJqv1A== Received: from DM5PR18CA0070.namprd18.prod.outlook.com (2603:10b6:3:22::32) by CH2PR12MB3702.namprd12.prod.outlook.com (2603:10b6:610:27::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.16; Tue, 19 Oct 2021 10:36:15 +0000 Received: from DM6NAM11FT053.eop-nam11.prod.protection.outlook.com (2603:10b6:3:22:cafe::c9) by DM5PR18CA0070.outlook.office365.com (2603:10b6:3:22::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.16 via Frontend Transport; Tue, 19 Oct 2021 10:36:15 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT053.mail.protection.outlook.com (10.13.173.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 10:36:15 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct 2021 10:36:12 +0000 From: Xueming Li To: CC: , Viacheslav Ovsiienko , Lior Margalit , Matan Azrad Date: Tue, 19 Oct 2021 18:34:58 +0800 Message-ID: <20211019103501.2216840-6-xuemingl@nvidia.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019103501.2216840-1-xuemingl@nvidia.com> References: <20210927083256.337450-1-xuemingl@nvidia.com> <20211019103501.2216840-1-xuemingl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8e103fb3-0934-42af-4d03-08d992ec472a X-MS-TrafficTypeDiagnostic: CH2PR12MB3702: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:227; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5JQsptxMWZk4ZyalwZNuGEkAEXvJ/L79rW9Wyktk+ZPGVgbMfxv7rPTy/6iDSyrYAusL7FlHMRS8+9JOw8aFueZD5LyHy+pWWkSYWeIxLxXNTKxOypJ+0J609qT8iREUtw544R+eKZG1KQOpY0foMIgYZEkr/LUt05hN3Mi9G+w0/090duCybuYv1eten1IQeeNRVba8WAf4DnE83sGiP/k+3HRDJYCKvBMXmNy7FcUKD4hc2g73lTTeGo/QujBsbD2Yjm0ZrT+dwxpAN4Dawhgz63RsMUKOYLNCWlhqXE8dSqOfpLHs/JgQm3qBz9GG0TQWaq53QOwTre/38yRxi3BkQgVKtG2grbm5oZiig/e0bp2duz7Rg/O7N1GOSMFFogICnDGYv+4KmjFXS3/TubMGZbo8dZJqZJK8b2Nk0O3YpCWiitmZC5enseoICqhMgR91F6yBiTnAAtUeUDarKnSbE/VG71JcLbWrADbyZlwRYi7+7trElCUIjWUK7muZoiV1Grommkigdf65m9oHjMwZpehxTup2+cgc1SDEIjWCrTM74/c2JiH0Pwh71/kKFOKE3LEdIAjOJFMcwwT7tvSaIKQH0lHnwuExo4cfr2VxN+pbxqTseG0fLLGUBX0KPlcl9bJcyALr/CPHPu3tqLR9yHh/4fYAt0UAOyaqumW+n35ez16T5+iY1xh1sVIqZKzVleTwtk4hLZIJoIP+TQ== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(16526019)(2906002)(5660300002)(70206006)(356005)(7696005)(6916009)(54906003)(6666004)(82310400003)(6286002)(316002)(7636003)(83380400001)(4326008)(2616005)(508600001)(70586007)(55016002)(336012)(36756003)(36860700001)(107886003)(26005)(86362001)(186003)(1076003)(426003)(8936002)(8676002)(47076005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2021 10:36:15.0809 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8e103fb3-0934-42af-4d03-08d992ec472a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB3702 Subject: [dpdk-dev] [PATCH v3 5/8] net/mlx5: supports flow item of normal Tx queue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Extends txq flow pattern to support both hairpin and regular txq. Signed-off-by: Xueming Li Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_dv.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index f06ce54f7e7..4a17ca64a2e 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -10910,22 +10910,22 @@ flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev, void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters); struct mlx5_txq_ctrl *txq; - uint32_t queue; - + uint32_t queue, mask; queue_m = (const void *)item->mask; - if (!queue_m) - return; queue_v = (const void *)item->spec; if (!queue_v) return; txq = mlx5_txq_get(dev, queue_v->queue); if (!txq) return; - queue = txq->obj->sq->id; - MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue); - MLX5_SET(fte_match_set_misc, misc_v, source_sqn, - queue & queue_m->queue); + if (txq->type == MLX5_TXQ_TYPE_HAIRPIN) + queue = txq->obj->sq->id; + else + queue = txq->obj->sq_obj.sq->id; + mask = queue_m == NULL ? UINT32_MAX : queue_m->queue; + MLX5_SET(fte_match_set_misc, misc_m, source_sqn, mask); + MLX5_SET(fte_match_set_misc, misc_v, source_sqn, queue & mask); mlx5_txq_release(dev, queue_v->queue); } From patchwork Tue Oct 19 10:34:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xueming Li X-Patchwork-Id: 102180 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C3936A0C43; Tue, 19 Oct 2021 12:36:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D352341148; Tue, 19 Oct 2021 12:36:20 +0200 (CEST) Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2051.outbound.protection.outlook.com [40.107.92.51]) by mails.dpdk.org (Postfix) with ESMTP id 69BCB40683 for ; Tue, 19 Oct 2021 12:36:18 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=YmErNTcc6AdgmqeY08bAPE85IW8NWlPW4Bxlb+aRzyzFAOMm6Et/dZ2lXSFLreU0vd+snm42vlHBA/+yj53/dRhwsYNo9X4rxpyw8QVG8q6PDLGJ1lq9txXEfhu3rt1en9RVuZKow6MrNQsZS6cbLgyHgKkzp60n+UGteEw7cGKXaRjC3mTrh7mCS1Lt1MXTCItXbj8DRRMadYiNev4cSPw/d87zYsV6zdLjFqxCVXWKt2LwBKphY6os+T8pchbOqL40y5/HBF+agCmwmAt56sYvdpnb3q0Ik62i7iQuHRGACP4O7EzIAbehEDTLLFIaJZVPCMPQl1SscEERBTclAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=bCyumIfI6Xj/V6dXzfiLRJl8y8nqKCdUPyXhw0+nFBk=; b=jOQAEqoTWlOf3GKNVM9GLCam58G7NKB5aEQsjAZh7gpYH635+IZXLgEapXVPLBZd3fSGZdHo4qmaciGvYWQ7OpHmLbSx0Ef6y1pzCZc88IRpcILLbksQle0aHpNGZDUAHKjRx9OPrgD5obFTBUEoNjlHfrOavpus8zZklixqSzOgnuWOqN0ZxTnan6S0dt3AuBBbCWEJFq9zy+nmKKrETI7oSmTIhWHBWwZN5rAwyD7lzTvyJGC5bN+N1zmc1/ku97YKrVnTji0mNP+0NaSJs/uhiigfk4o3b319VX69fjwR2BLowOd9TTNrO/VRNjXS7xM2wWzOriXpxNf9eay3Qw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bCyumIfI6Xj/V6dXzfiLRJl8y8nqKCdUPyXhw0+nFBk=; b=JjMhsCq/6LdCkhOFijRUmbXhpHevWz4XTOUZjtepXfW22lYWVdLw9RV8hG/aKbK6gdzRpWrYkUa7SryONML8cEX4a6u3TncJ047x1xl50ybx/CTm84p/wRq6zLsYm/AI0paTEe6nLAFbaOfavNL0khuZoTnZ/XY4LQrJ2idgLTt7nFEtCHC//WBeh9mZWzxeWJq1Hc1RRDBDLGxgAVTtVvN5V1d+HFk5Ttz5UGlvCUddnHlEDy3YsXeSpySC361XVAGH6l0Kk8Jt3D8NoRvetA/iJN3d7nL+5WG1vJryIltbFm6bZYG1bs0thgE5UKciGcYkEBkXXKbM3AymWqgTsQ== Received: from DM5PR18CA0064.namprd18.prod.outlook.com (2603:10b6:3:22::26) by DM6PR12MB5552.namprd12.prod.outlook.com (2603:10b6:5:1bd::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.17; Tue, 19 Oct 2021 10:36:17 +0000 Received: from DM6NAM11FT053.eop-nam11.prod.protection.outlook.com (2603:10b6:3:22:cafe::5e) by DM5PR18CA0064.outlook.office365.com (2603:10b6:3:22::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 10:36:17 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT053.mail.protection.outlook.com (10.13.173.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 10:36:16 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct 2021 10:36:14 +0000 From: Xueming Li To: CC: , Viacheslav Ovsiienko , Lior Margalit , Matan Azrad , "Dong Zhou" Date: Tue, 19 Oct 2021 18:34:59 +0800 Message-ID: <20211019103501.2216840-7-xuemingl@nvidia.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019103501.2216840-1-xuemingl@nvidia.com> References: <20210927083256.337450-1-xuemingl@nvidia.com> <20211019103501.2216840-1-xuemingl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2f72fee2-1e6b-4205-447f-08d992ec4822 X-MS-TrafficTypeDiagnostic: DM6PR12MB5552: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UuM435haVqav+JbGWOLTxJ50kcJP9z3ttu0KVxgLTKo9HwGb7wjNv4cg4A1ryg/xGolExmHbplbJFV/09TQrTHwU7z2HzitqbwsEKEGhyy2SAPtKEWE5MpAF/5Fl5VzvD7yXSuvFdldjfhINJmWoH2ZlfYwPrI2yrMzFCXeir0EAUOzFuIAPLzNHRXjWxENN9BSZLNyIqacvGUcNIgK4sgtqF5Yeulnj64BwqKzydZxm0lpPkJ1fCMXHQ7D23xgahxPMzav5mfTl/8q1LBns27kHdj9jQ/sp8yVEgzw8PST6m0IfHRovek3H5wBp8Ey6alMVJPiXD+aLSU8u/nu8Q6DlXF+6zlI9MSogLIVwrBXXUgL33U2280M4/9GHzwdieT9ljnBNKSJkS4o6GFntGWLnisZzah6OYBYVXIlAvlHck3E1G5IMiYUk09WST45z4oIMx54YIJKUsYJkxW5G2Sd9IME4l+pT12kHcXCYdMddagKEx5uLW9k2kDkrpxdjZqAmkdCgWDgBeRfYSPBgqK3ufzLHjHwZEhsD7R3Pdf97rziWlRG+LCKPwYR7rKESWVRmjaG+72G4ykj+Q9G8G702OZ/Qrow7a84fTMRqgHIl6/8pTliWxvqIh17kUaPrT7vDvnDtPrN7SCQxUGVyTTuALTcvm+O1isa6gjHL93PPCQEemBlYltVdWdgbdjnCCkFIeQJMUkB8XQl8tJ36mw== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(8676002)(336012)(54906003)(6286002)(426003)(356005)(8936002)(70586007)(107886003)(1076003)(70206006)(26005)(2616005)(36756003)(5660300002)(47076005)(6916009)(316002)(2906002)(83380400001)(55016002)(16526019)(4326008)(7696005)(86362001)(6666004)(508600001)(7636003)(36860700001)(82310400003)(186003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2021 10:36:16.8618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2f72fee2-1e6b-4205-447f-08d992ec4822 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB5552 Subject: [dpdk-dev] [PATCH v3 6/8] net/mlx5: fix internal root table flow priroity X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When creating internal transfer flow on root table with lowerest priority, the flow was created with max UINT32_MAX priority. It is wrong since the flow is created in kernel and max priority supported is 16. This patch fixes this by adding internal flow check. Fixes: 5f8ae44dd454 ("net/mlx5: enlarge maximal flow priority") Signed-off-by: Xueming Li Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow.c | 7 ++++++- drivers/net/mlx5/mlx5_flow.h | 4 ++-- drivers/net/mlx5/mlx5_flow_dv.c | 3 ++- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index c914a7120cc..b5232cd46ae 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -980,13 +980,15 @@ mlx5_get_lowest_priority(struct rte_eth_dev *dev, * Pointer to device flow rule attributes. * @param[in] subpriority * The priority based on the items. + * @param[in] external + * Flow is user flow. * @return * The matcher priority of the flow. */ uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, - uint32_t subpriority) + uint32_t subpriority, bool external) { uint16_t priority = (uint16_t)attr->priority; struct mlx5_priv *priv = dev->data->dev_private; @@ -995,6 +997,9 @@ mlx5_get_matcher_priority(struct rte_eth_dev *dev, if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) priority = priv->config.flow_prio - 1; return mlx5_os_flow_adjust_priority(dev, priority, subpriority); + } else if (!external && attr->transfer && attr->group == 0 && + attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) { + return (priv->config.flow_prio - 1) * 3; } if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) priority = MLX5_NON_ROOT_FLOW_MAX_PRIO; diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index c25af8d9864..f1a83d537d0 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1431,8 +1431,8 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, uint32_t mlx5_get_lowest_priority(struct rte_eth_dev *dev, const struct rte_flow_attr *attr); uint16_t mlx5_get_matcher_priority(struct rte_eth_dev *dev, - const struct rte_flow_attr *attr, - uint32_t subpriority); + const struct rte_flow_attr *attr, + uint32_t subpriority, bool external); int mlx5_flow_get_reg_id(struct rte_eth_dev *dev, enum mlx5_feature_name feature, uint32_t id, diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 4a17ca64a2e..ffc1fc8a05c 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -13646,7 +13646,8 @@ flow_dv_translate(struct rte_eth_dev *dev, matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf, matcher.mask.size); matcher.priority = mlx5_get_matcher_priority(dev, attr, - matcher.priority); + matcher.priority, + dev_flow->external); /** * When creating meter drop flow in drop table, using original * 5-tuple match, the matcher priority should be lower than From patchwork Tue Oct 19 10:35:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xueming Li X-Patchwork-Id: 102181 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 81A58A0C43; Tue, 19 Oct 2021 12:36:28 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CE1154114D; Tue, 19 Oct 2021 12:36:23 +0200 (CEST) Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2085.outbound.protection.outlook.com [40.107.243.85]) by mails.dpdk.org (Postfix) with ESMTP id 0513941150 for ; Tue, 19 Oct 2021 12:36:22 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=OIY99/6o159kjf9Xw+e2iqZdxQVzVGUKT4rQwrhyJh9WMqYBAft4SlkRu5bNN8wwmp1YyiN4mrMrm4QRrPa79hRsN06re9XLrmhewOGtuxdCgNoPtTXv6rm8t47OzO5sLZNqQL9+3Zvqh/iabvCBdZ4F5hMu1W+sArZdeHzOTx2q2zDgk19UgD2yFymHLSWZhXMpCo7N6M8VIeHImKq46Pyfun9a0TAGk6dcXrCJKpqHdJyVWkGuvm4tA6jIKwf9f9RYsJABIBWvF0YGnZW8/JQWVjopGHoKI7/1R9c17kqV9H5js8FWrwLt7sRRsCvA8AOUN6eSHA6GIew+2hqAKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=NlTa472Dri1NZoJRvq4N44hEsg2TguOMhjy64TZqJ4Y=; b=fLlb4TaRj3YreIZeUI37g21F8y46TDNx7yhBz0H6MD1bjOHi8KtSWGtp6K8jBY9npnaQR71zgza9l4Y2S81l6ZqYsk19a1lKg/ib9dDrISBqBr8ClJo5e2QUij8DQTTjm0qWGt8TbDkKpU/uBIgDGnNTrx0bnixApepGB1slYKE9pUt9j9HDwkK9PoOWu48I2W+9f5SmK4gT0OHiwGlXTwwo8H5B1rKMJ/xtyZg+dpmrgdr4yI2uFOO+Q3q5K5M8Q3L8VoZ0WWARd23JPB1p5iHkliyCkomIGa7a+yeMzPy7Z9T5ao1wyHXmAjMZg/gXjrQY3pUfgxiGsRQWdZ3HDA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NlTa472Dri1NZoJRvq4N44hEsg2TguOMhjy64TZqJ4Y=; b=lsTY1Es1+eNO0PKEwkN/61GJGzQl9+eBPSh4P1wIQ7VKbufGZGFlY+PPDardnEpYToQ3p+/bQ3t3ujLxcB01bX6mHXu4Y6bSzfUhzKxaH3ppcaxYwmce00sES8JeuaywzsMIBo3kCOSIvy3H283VnCP1mz8AnCNq3DD9u/p0aylB+VcIw7OxPk4p8C8GF2uof07gmdXtE0DqbHtrBEl+0OaG1+psbbgb9/9B/17QjlV0JDydV0VtFI+Yiepnok9Y1sWHA7Dubfxum5lxbT2dR3Ipe2K/EyLNnqJ5PqelXAQIxrFmBQDGRbh+5PILhgcwvUayXgpCvNdQZnZhJCAeZA== Received: from DM5PR04CA0070.namprd04.prod.outlook.com (2603:10b6:3:ef::32) by BN8PR12MB3220.namprd12.prod.outlook.com (2603:10b6:408:9e::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.15; Tue, 19 Oct 2021 10:36:20 +0000 Received: from DM6NAM11FT030.eop-nam11.prod.protection.outlook.com (2603:10b6:3:ef:cafe::28) by DM5PR04CA0070.outlook.office365.com (2603:10b6:3:ef::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 10:36:20 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT030.mail.protection.outlook.com (10.13.172.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 10:36:19 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct 2021 10:36:16 +0000 From: Xueming Li To: CC: , Viacheslav Ovsiienko , Lior Margalit , Matan Azrad Date: Tue, 19 Oct 2021 18:35:00 +0800 Message-ID: <20211019103501.2216840-8-xuemingl@nvidia.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019103501.2216840-1-xuemingl@nvidia.com> References: <20210927083256.337450-1-xuemingl@nvidia.com> <20211019103501.2216840-1-xuemingl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: cb2ca142-1ea7-4600-d1be-08d992ec49b8 X-MS-TrafficTypeDiagnostic: BN8PR12MB3220: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3513; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LHdNbXwtnmDABmmdNACJlDAJYYYMdtcNv9tvKKdCNICSBxFWOrR4F89EoIzbq/HyTJ6OHXdSW7gVgEm61tkOlCDBpmJlVhIBqKpOcB10a1t0HnucWMCnJH2XPrZV3x8/bV3TFqwrybpZ0pTcXKR/6oubV1QvlXzjoUpl5mvkB/qjaTbf2ndppoNbSigqZcygOP1uWeObZsdRzyAEnW7zLKjzuNfOkAuf7hRUcLuF8GyJqaaAgj6bAwX6LXSR8hU86Hya22stYYYqy4IpzTr0+xT4x9aMbyxyG4D40qnPDuU+6C2uov9146cmtHencIVC5nslYreOmnYFiSAkoRooudgeLnp9TBTMH+R6/L/+k2Kx294BxaHS6MPfN9zLsK41cNLQ8FIimBD4Aegq/whfW8+im8Q18Ps5N1yn8g8I8dgfOWIqQzINzhLNdu9BkO5flmbhecYvOcloV3l+3kBIIC0EXP8dIsCy7y8QF2B8K2xhiwO7KJ0oZh6OtOkbm9YUnXBhAp2vTfKSCeTecbD3JzfVAkMZDi6YzqKyqLGnejxyW/ba7u6u/nBSgYnVH7a+AEbaCByxXgAoqMY0DfUgLGtkLdzJ/4R7iicOF9UJetOAnnDAqoPF22c6dkxpRVtqf1N+CmA6LgPtgXfMWcjrDrBj+yjcG4mRijul/uDJ2BmjbO6G609pK04wFb2F30lmxRc+FaZyzH/1SzwLNk5Gyg== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(426003)(36756003)(55016002)(6666004)(186003)(83380400001)(107886003)(8676002)(6286002)(70206006)(70586007)(16526019)(336012)(508600001)(36860700001)(82310400003)(2616005)(4326008)(316002)(54906003)(1076003)(5660300002)(47076005)(356005)(2906002)(86362001)(8936002)(7636003)(7696005)(6916009)(26005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2021 10:36:19.4223 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cb2ca142-1ea7-4600-d1be-08d992ec49b8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT030.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3220 Subject: [dpdk-dev] [PATCH v3 7/8] net/mlx5: enable DevX Tx queue creation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Verbs API does not support Infiniband device port number larger 255 by design. To support more representors on a single Infiniband device DevX API should be engaged. While creating Send Queue (SQ) object with Verbs API, the PMD assigned IB device port attribute and kernel created the default miss flows in FDB domain, to redirect egress traffic from the queue being created to representor appropriate peer (wire, HPF, VF or SF). With DevX API there is no IB-device port attribute (it is merely kernel one, DevX operates in PRM terms) and PMD must create default miss flows in FDB explicitly. PMD did not provide this and using DevX API for E-Switch configurations was disabled. The default miss FDB flow matches E-Switch manager vport (to make sure the source is some representor) and SQn (Send Queue number - device internal queue index). The root flow table managed by kernel/firmware and it does not support vport redirect action, we have to split the default miss flow into two ones: - flow with lowest priority in the root table that matches E-Switch manager vport ID and jump to group 1. - flow in group 1 that matches E-Switch manager vport ID and SQn and forwards packet to peer vport Signed-off-by: Xueming Li Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/linux/mlx5_os.c | 62 +------------------------- drivers/net/mlx5/mlx5.h | 2 + drivers/net/mlx5/mlx5_devx.c | 10 ++--- drivers/net/mlx5/mlx5_devx.h | 2 + drivers/net/mlx5/mlx5_flow.c | 74 ++++++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5_trigger.c | 11 ++++- 6 files changed, 94 insertions(+), 67 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index f283a3779cc..93ee9318ebc 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -697,56 +697,6 @@ mlx5_init_once(void) return ret; } -/** - * Create the Tx queue DevX/Verbs object. - * - * @param dev - * Pointer to Ethernet device. - * @param idx - * Queue index in DPDK Tx queue array. - * - * @return - * 0 on success, a negative errno value otherwise and rte_errno is set. - */ -static int -mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) -{ - struct mlx5_priv *priv = dev->data->dev_private; - struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; - struct mlx5_txq_ctrl *txq_ctrl = - container_of(txq_data, struct mlx5_txq_ctrl, txq); - - if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) - return mlx5_txq_devx_obj_new(dev, idx); -#ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET - if (!priv->config.dv_esw_en) - return mlx5_txq_devx_obj_new(dev, idx); -#endif - return mlx5_txq_ibv_obj_new(dev, idx); -} - -/** - * Release an Tx DevX/verbs queue object. - * - * @param txq_obj - * DevX/Verbs Tx queue object. - */ -static void -mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) -{ - if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { - mlx5_txq_devx_obj_release(txq_obj); - return; - } -#ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET - if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { - mlx5_txq_devx_obj_release(txq_obj); - return; - } -#endif - mlx5_txq_ibv_obj_release(txq_obj); -} - /** * DV flow counter mode detect and config. * @@ -1812,16 +1762,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, ibv_obj_ops.drop_action_create; priv->obj_ops.drop_action_destroy = ibv_obj_ops.drop_action_destroy; -#ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET - priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; -#else - if (config->dv_esw_en) - priv->obj_ops.txq_obj_modify = - ibv_obj_ops.txq_obj_modify; -#endif - /* Use specific wrappers for Tx object. */ - priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; - priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; mlx5_queue_counter_id_prepare(eth_dev); priv->obj_ops.lb_dummy_queue_create = mlx5_rxq_ibv_obj_dummy_lb_create; @@ -1832,7 +1772,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, } if (config->tx_pp && (priv->config.dv_esw_en || - priv->obj_ops.txq_obj_new != mlx5_os_txq_obj_new)) { + priv->obj_ops.txq_obj_new != mlx5_txq_devx_obj_new)) { /* * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support * packet pacing and already checked above. diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 3581414b789..570f827375a 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1699,6 +1699,8 @@ int mlx5_ctrl_flow(struct rte_eth_dev *dev, struct rte_flow_item_eth *eth_mask); int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); +uint32_t mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, + uint32_t txq); void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, uint64_t async_id, int status); void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh); diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index a1db53577a2..a49602cb957 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -102,9 +102,9 @@ mlx5_devx_modify_rq(struct mlx5_rxq_obj *rxq_obj, uint8_t type) * @return * 0 on success, a negative errno value otherwise and rte_errno is set. */ -static int -mlx5_devx_modify_sq(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type, - uint8_t dev_port) +int +mlx5_txq_devx_modify(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type, + uint8_t dev_port) { struct mlx5_devx_modify_sq_attr msq_attr = { 0 }; int ret; @@ -1118,7 +1118,7 @@ mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx) *txq_data->qp_db = 0; txq_data->qp_num_8s = txq_obj->sq_obj.sq->id << 8; /* Change Send Queue state to Ready-to-Send. */ - ret = mlx5_devx_modify_sq(txq_obj, MLX5_TXQ_MOD_RST2RDY, 0); + ret = mlx5_txq_devx_modify(txq_obj, MLX5_TXQ_MOD_RST2RDY, 0); if (ret) { rte_errno = errno; DRV_LOG(ERR, @@ -1187,7 +1187,7 @@ struct mlx5_obj_ops devx_obj_ops = { .drop_action_create = mlx5_devx_drop_action_create, .drop_action_destroy = mlx5_devx_drop_action_destroy, .txq_obj_new = mlx5_txq_devx_obj_new, - .txq_obj_modify = mlx5_devx_modify_sq, + .txq_obj_modify = mlx5_txq_devx_modify, .txq_obj_release = mlx5_txq_devx_obj_release, .lb_dummy_queue_create = NULL, .lb_dummy_queue_release = NULL, diff --git a/drivers/net/mlx5/mlx5_devx.h b/drivers/net/mlx5/mlx5_devx.h index bc8a8d6b73c..a95207a6b9a 100644 --- a/drivers/net/mlx5/mlx5_devx.h +++ b/drivers/net/mlx5/mlx5_devx.h @@ -8,6 +8,8 @@ #include "mlx5.h" int mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx); +int mlx5_txq_devx_modify(struct mlx5_txq_obj *obj, + enum mlx5_txq_modify_type type, uint8_t dev_port); void mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj); extern struct mlx5_obj_ops devx_obj_ops; diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index b5232cd46ae..1528f8c6b51 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -6573,6 +6573,80 @@ mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev) actions, false, &error); } +/** + * Create a dedicated flow rule on e-switch table 1, matches ESW manager + * and sq number, directs all packets to peer vport. + * + * @param dev + * Pointer to Ethernet device. + * @param txq + * Txq index. + * + * @return + * Flow ID on success, 0 otherwise and rte_errno is set. + */ +uint32_t +mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t txq) +{ + struct rte_flow_attr attr = { + .group = 0, + .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, + .ingress = 1, + .egress = 0, + .transfer = 1, + }; + struct rte_flow_item_port_id port_spec = { + .id = MLX5_PORT_ESW_MGR, + }; + struct mlx5_rte_flow_item_tx_queue txq_spec = { + .queue = txq, + }; + struct rte_flow_item pattern[] = { + { + .type = RTE_FLOW_ITEM_TYPE_PORT_ID, + .spec = &port_spec, + }, + { + .type = (enum rte_flow_item_type) + MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, + .spec = &txq_spec, + }, + { + .type = RTE_FLOW_ITEM_TYPE_END, + }, + }; + struct rte_flow_action_jump jump = { + .group = 1, + }; + struct rte_flow_action_port_id port = { + .id = dev->data->port_id, + }; + struct rte_flow_action actions[] = { + { + .type = RTE_FLOW_ACTION_TYPE_JUMP, + .conf = &jump, + }, + { + .type = RTE_FLOW_ACTION_TYPE_END, + }, + }; + struct rte_flow_error error; + + /* + * Creates group 0, highest priority jump flow. + * Matches txq to bypass kernel packets. + */ + if (flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, actions, + false, &error) == 0) + return 0; + /* Create group 1, lowest priority redirect flow for txq. */ + attr.group = 1; + actions[0].conf = &port; + actions[0].type = RTE_FLOW_ACTION_TYPE_PORT_ID; + return flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, + actions, false, &error); +} + /** * Validate a flow supported by the NIC. * diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index 54173bfacb2..42d8bb31128 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -1255,9 +1255,18 @@ mlx5_traffic_enable(struct rte_eth_dev *dev) goto error; } } + if ((priv->representor || priv->master) && + priv->config.dv_esw_en) { + if (mlx5_flow_create_devx_sq_miss_flow(dev, i) == 0) { + DRV_LOG(ERR, + "Port %u Tx queue %u SQ create representor devx default miss rule failed.", + dev->data->port_id, i); + goto error; + } + } mlx5_txq_release(dev, i); } - if (priv->config.dv_esw_en && !priv->config.vf && !priv->config.sf) { + if ((priv->master || priv->representor) && priv->config.dv_esw_en) { if (mlx5_flow_create_esw_table_zero_flow(dev)) priv->fdb_def_rule = 1; else From patchwork Tue Oct 19 10:35:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xueming Li X-Patchwork-Id: 102182 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B12EEA0C43; Tue, 19 Oct 2021 12:36:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 19BF440683; Tue, 19 Oct 2021 12:36:26 +0200 (CEST) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2087.outbound.protection.outlook.com [40.107.237.87]) by mails.dpdk.org (Postfix) with ESMTP id 4C66F41152 for ; Tue, 19 Oct 2021 12:36:23 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TYeOp5/OyW3cVsg7UNiSi0rkLtS8wiU15nRe4jpmkaUwPXZ5IQAoCSm03Su4ADpvzBYLbsWxSKRQF51qeYs7a0vqsjrAHNwxCBfAQFhDgvw/wSqYfalh0xJ4qoVu09yXag42ePOf+7umzQV96Yl8O7wUvWMuST8SPWAzZIJeTiYGiI8OWzFzovnQ6sQ+D20l9dB9cy1/eJIDBtYog9XdgxeC1vsxLMLbiO1NlBs6Qxb2j/MWopSO+3QChkQ7C5sDrZJ0Y8bEmuaDbzB0Py5Y32zmsSJRD7NpSlA3kn938eJAzcfiNiYBBOD4qaQmZ7Ps+dBT5b/8vIjs+pfg3wTZ7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0AP+V9J8aNkqbY1QT8RsrgotZDZKP1MEEsCgjUuYrM0=; b=Wkm5EzPLlAo6OklGzO/KKkzLXUpVEHsZ/kVAJipbd7Fd03OPrITa2tKPFwPYUxSi0yfYRIZuoLRTCIGVYtAeziJhyIhCLwoAMqWIiVZzpNu6Hj4j/Wojo0JQGg7e7PWUePcWfhMs36bi4Q4/eW8hTv+3KYrR8tuWrkkgAHd4CX1iiOhon3ilWIbWqGOf1bVjaTEqsRLJYTAfNuTu5byr8fmsRoLheS6SCS0JnRYi/qISJ30ILSi9w5fcbhu4QvUrM6UZjR1IQc6tnVlj4wuVg+jCgt8bO6vMvwnj17Svn7IHMfh+XC2oLPYiEMZb12v72WZoruZBreEmTwAsf3v+EA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0AP+V9J8aNkqbY1QT8RsrgotZDZKP1MEEsCgjUuYrM0=; b=owJu6V+kuj+uMvLawq1rPWBDcyBu0RkpxYjcU5OwkEzBa/InVUetKzP+yS6M75WwI9p1OOiC9z7EeSAdsCERO3h/v3v+UhUkJyktNLzIMl0HCg10pUz4tZ+wOAmfI8Sz643x76ty7LK2Z+p8v0DJTw1Q/R5I0Xmx6Rq/7YqL+5ctXkRXYa+gyEztc5d7ShJsDApdtcuxd3DH9a/0JUKRdxiQBGICz2NZAfbYsbUMkhFNlnB6ZKFf7frRp01s8jLaqSER4+PKLu/LjLbUhrFPa6U6QVZ/XccA/4ZUbLulmaczf3p+5K1aN7wXggq1ZMxuk1BBW56y4Cet27hj1a74LA== Received: from DM5PR04CA0066.namprd04.prod.outlook.com (2603:10b6:3:ef::28) by PH0PR12MB5452.namprd12.prod.outlook.com (2603:10b6:510:d7::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.16; Tue, 19 Oct 2021 10:36:21 +0000 Received: from DM6NAM11FT030.eop-nam11.prod.protection.outlook.com (2603:10b6:3:ef:cafe::19) by DM5PR04CA0066.outlook.office365.com (2603:10b6:3:ef::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 10:36:21 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT030.mail.protection.outlook.com (10.13.172.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 10:36:21 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct 2021 10:36:18 +0000 From: Xueming Li To: CC: , Viacheslav Ovsiienko , Lior Margalit , Matan Azrad Date: Tue, 19 Oct 2021 18:35:01 +0800 Message-ID: <20211019103501.2216840-9-xuemingl@nvidia.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211019103501.2216840-1-xuemingl@nvidia.com> References: <20210927083256.337450-1-xuemingl@nvidia.com> <20211019103501.2216840-1-xuemingl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5a24072d-6960-46dc-b429-08d992ec4a9f X-MS-TrafficTypeDiagnostic: PH0PR12MB5452: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:346; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 14g4nrcsjRVXlHTwwXT7fxOfvxxBr4LFAt+nJmLXlh5LE0o16bRJOy1x7fh6eInyGZVE/SfYGuZ73cqwdnulZrc4/2I9i0YZF+PEC3oPEIOAz/obOSyaMVaIwpRNUGaRdGLuMaBziAdqJRszKQ3gzu7abvBNqspOeggXdCCXZBz4Z/oHMSWgE+5dFSL7yRPkWJWuKe6te+bAnu/xnM5U2Y0KjMIIyTABOuWUMnrdENKY3tSx8x6MZ16g4QscrbjeuwBFGYAuIZ2rSo9s/h4iKU/aCMYPCW7oZpp+BQTFIAlGY0ZGqQfBY/gDxNKzKUZzm4mTIH0k8T58ZL/Cw2SYcpD37IgB2vPg+euuzOT/RH3A74u6X7/aUODLpSLZ9nCt4vFW9acYSAaTlCQwaudOlJVeZXiERl2i9JDbQv1lJy9WhOiB43BkCqFN7gpRrcvb4JO9yp4JAfAQxnN8yxV5mkxxKZFH6aM9ronl6T5xPPJufEPKGMa+W6KJmfyOHSlAYOM0ehkSDGgfsh/JdGCPTuxideM21UGm4M8sJIe5s7S+y6s6EI8vXMCJBHCvrwTms3at1tX2aw6NzaeYXnMpxrJgjRr/DDWz5mApIGKP+NksPAf/HWObTMjxWLmug2BUwoZbFJyuSwMCkhzID1h8AJ5br+FJzsJtuhY5LYTRzfnIhnDCVYtcIyGosqlDMBB6uBfuKazSjuFGjPMd/COlDQ== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(82310400003)(356005)(47076005)(83380400001)(508600001)(36756003)(7636003)(54906003)(316002)(36860700001)(70206006)(8676002)(4326008)(6916009)(107886003)(70586007)(86362001)(2616005)(8936002)(6666004)(26005)(55016002)(6286002)(16526019)(2906002)(426003)(336012)(5660300002)(7696005)(186003)(1076003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2021 10:36:21.0184 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a24072d-6960-46dc-b429-08d992ec4a9f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT030.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5452 Subject: [dpdk-dev] [PATCH v3 8/8] net/mlx5: check DevX to support more Verbs ports X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Verbs API doesn't support device port number larger than 255 by design. To support more VF or SubFunction port representors, forces DevX API check when max Verbs device link ports larger than 255. Signed-off-by: Xueming Li Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/linux/mlx5_os.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 93ee9318ebc..39a9722d869 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1299,12 +1299,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, config->dv_flow_en = 0; } #endif - if (spawn->max_port > UINT8_MAX) { - /* Verbs can't support ports larger than 255 by design. */ - DRV_LOG(ERR, "can't support IB ports > UINT8_MAX"); - err = EINVAL; - goto error; - } config->ind_table_max_size = sh->device_attr.max_rwq_indirection_table_size; /* @@ -1767,6 +1761,11 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, mlx5_rxq_ibv_obj_dummy_lb_create; priv->obj_ops.lb_dummy_queue_release = mlx5_rxq_ibv_obj_dummy_lb_release; + } else if (spawn->max_port > UINT8_MAX) { + /* Verbs can't support ports larger than 255 by design. */ + DRV_LOG(ERR, "must enable DV and ESW when RDMA link ports > 255"); + err = ENOTSUP; + goto error; } else { priv->obj_ops = ibv_obj_ops; }