From patchwork Tue Oct 26 04:12:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Radha Chintakuntla X-Patchwork-Id: 102832 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E6A43A0C47; Tue, 26 Oct 2021 06:13:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F1859410F8; Tue, 26 Oct 2021 06:13:27 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 188B740A4B for ; Tue, 26 Oct 2021 06:13:25 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19PLKxk3012626; Mon, 25 Oct 2021 21:13:24 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0220; bh=mgmQrHpE4yhyHQZFEDO7yAl7BREt7l9CBSLo4oIl5kU=; b=Gq0vGDjmnzPQZX9rkqDsFkmMW8tNxvJBfwE2VSeaEuQGuN2uUow6jJRsN+awyT/84wE2 DT7fdZmByRXWgrtRhsXG/9/6KkSTyoek3QJzN3gFJmflZ5i2cK0IS1ZvdOfy+eeLClws bwNpWJhTtKUjYeYzzyki161r+PwX0wGG7q5RfVKRraKciNKMuLrjl7DnTJovu0l8SYx5 vAPZwmY1c0n7MkYQyGpQYQgbalogYZ+2+PhuQI3HSlou1H0/AKjfSDNZvrM6FpjyfpXd BJR/+0aC/ePowXLA2VzTrTFKYTVvzf21xghfXaAptZ/r68PKsehEpH/ZybV6mazW6jLF 5A== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3bx4dx1971-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 25 Oct 2021 21:13:24 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 25 Oct 2021 21:13:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 25 Oct 2021 21:13:21 -0700 Received: from rchintakuntla-lnx3.caveonetworks.com (unknown [10.111.140.81]) by maili.marvell.com (Postfix) with ESMTP id 9583E3F705A; Mon, 25 Oct 2021 21:13:21 -0700 (PDT) From: Radha Mohan Chintakuntla To: , , , , , , , CC: , Radha Mohan Chintakuntla Date: Mon, 25 Oct 2021 21:12:57 -0700 Message-ID: <20211026041300.28924-1-radhac@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Proofpoint-GUID: cBB9UTr7QOEgpFZ59odnWKG21ElfOfKt X-Proofpoint-ORIG-GUID: cBB9UTr7QOEgpFZ59odnWKG21ElfOfKt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-25_08,2021-10-25_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH 1/4] common/cnxk: add DPI DMA support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add base support as ROC(Rest of Chip) API which will be used by PMD dmadev driver. This patch adds routines to init, fini, configure the DPI DMA device found in Marvell's CN9k or CN10k SoC familes. Signed-off-by: Radha Mohan Chintakuntla --- drivers/common/cnxk/hw/dpi.h | 136 ++++++++++++++++++++ drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_api.h | 4 + drivers/common/cnxk/roc_dpi.c | 193 +++++++++++++++++++++++++++++ drivers/common/cnxk/roc_dpi.h | 44 +++++++ drivers/common/cnxk/roc_dpi_priv.h | 40 ++++++ drivers/common/cnxk/roc_platform.h | 1 + drivers/common/cnxk/roc_priv.h | 3 + drivers/common/cnxk/version.map | 5 + 9 files changed, 427 insertions(+) create mode 100644 drivers/common/cnxk/hw/dpi.h create mode 100644 drivers/common/cnxk/roc_dpi.c create mode 100644 drivers/common/cnxk/roc_dpi.h create mode 100644 drivers/common/cnxk/roc_dpi_priv.h diff --git a/drivers/common/cnxk/hw/dpi.h b/drivers/common/cnxk/hw/dpi.h new file mode 100644 index 0000000000..aa1e66aa11 --- /dev/null +++ b/drivers/common/cnxk/hw/dpi.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ +/** + * DPI device HW definitions. + */ +#ifndef __DEV_DPI_HW_H__ +#define __DEV_DPI_HW_H__ + +#include + +/** @cond __INTERNAL_DOCUMENTATION__ */ + +/* DPI VF register offsets from VF_BAR0 */ +#define DPI_VDMA_EN (0x0) +#define DPI_VDMA_REQQ_CTL (0x8) +#define DPI_VDMA_DBELL (0x10) +#define DPI_VDMA_SADDR (0x18) +#define DPI_VDMA_COUNTS (0x20) +#define DPI_VDMA_NADDR (0x28) +#define DPI_VDMA_IWBUSY (0x30) +#define DPI_VDMA_CNT (0x38) +#define DPI_VF_INT (0x100) +#define DPI_VF_INT_W1S (0x108) +#define DPI_VF_INT_ENA_W1C (0x110) +#define DPI_VF_INT_ENA_W1S (0x118) + +/** + * Enumeration dpi_hdr_xtype_e + * + * DPI Transfer Type Enumeration + * Enumerates the pointer type in DPI_DMA_INSTR_HDR_S[XTYPE]. + */ +#define DPI_XTYPE_OUTBOUND (0) +#define DPI_XTYPE_INBOUND (1) +#define DPI_XTYPE_INTERNAL_ONLY (2) +#define DPI_XTYPE_EXTERNAL_ONLY (3) +#define DPI_HDR_XTYPE_MASK 0x3 +#define DPI_HDR_PT_MASK 0x3 +#define DPI_HDR_TT_MASK 0x3 +#define DPI_HDR_GRP_MASK 0x3FF +#define DPI_HDR_FUNC_MASK 0xFFFF + +/* Big endian data bit position in DMA local pointer */ +#define DPI_LPTR_BED_BIT_POS (60) + +#define DPI_MIN_CMD_SIZE 8 +#define DPI_MAX_CMD_SIZE 64 + +/** + * Structure dpi_instr_hdr_s for CN9K + * + * DPI DMA Instruction Header Format + */ +union dpi_instr_hdr_s { + uint64_t u[4]; + struct dpi_dma_instr_hdr_s_s { + uint64_t tag : 32; + uint64_t tt : 2; + uint64_t grp : 10; + uint64_t reserved_44_47 : 4; + uint64_t nfst : 4; + uint64_t reserved_52_53 : 2; + uint64_t nlst : 4; + uint64_t reserved_58_63 : 6; + /* Word 0 - End */ + uint64_t aura : 20; + uint64_t func : 16; + uint64_t pt : 2; + uint64_t reserved_102 : 1; + uint64_t pvfe : 1; + uint64_t fl : 1; + uint64_t ii : 1; + uint64_t fi : 1; + uint64_t ca : 1; + uint64_t csel : 1; + uint64_t reserved_109_111 : 3; + uint64_t xtype : 2; + uint64_t reserved_114_119 : 6; + uint64_t fport : 2; + uint64_t reserved_122_123 : 2; + uint64_t lport : 2; + uint64_t reserved_126_127 : 2; + /* Word 1 - End */ + uint64_t ptr : 64; + /* Word 2 - End */ + uint64_t reserved_192_255 : 64; + /* Word 3 - End */ + } s; +}; + +/** + * Structure dpi_cn10k_instr_hdr_s for CN10K + * + * DPI DMA Instruction Header Format + */ +union dpi_cn10k_instr_hdr_s { + uint64_t u[4]; + struct dpi_cn10k_dma_instr_hdr_s_s { + uint64_t nfst : 4; + uint64_t reserved_4_5 : 2; + uint64_t nlst : 4; + uint64_t reserved_10_11 : 2; + uint64_t pvfe : 1; + uint64_t reserved_13 : 1; + uint64_t func : 16; + uint64_t aura : 20; + uint64_t xtype : 2; + uint64_t reserved_52_53 : 2; + uint64_t pt : 2; + uint64_t fport : 2; + uint64_t reserved_58_59 : 2; + uint64_t lport : 2; + uint64_t reserved_62_63 : 2; + /* Word 0 - End */ + uint64_t ptr : 64; + /* Word 1 - End */ + uint64_t tag : 32; + uint64_t tt : 2; + uint64_t grp : 10; + uint64_t reserved_172_173 : 2; + uint64_t fl : 1; + uint64_t ii : 1; + uint64_t fi : 1; + uint64_t ca : 1; + uint64_t csel : 1; + uint64_t reserved_179_191 : 3; + /* Word 2 - End */ + uint64_t reserved_192_255 : 64; + /* Word 3 - End */ + } s; +}; + +/** @endcond */ + +#endif /*__DEV_DPI_HW_H__*/ diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index d9871a6b45..d0aeb6b68c 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -19,6 +19,7 @@ sources = files( 'roc_cpt.c', 'roc_cpt_debug.c', 'roc_dev.c', + 'roc_dpi.c', 'roc_hash.c', 'roc_idev.c', 'roc_irq.c', diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h index b8f3667c6c..359d31327a 100644 --- a/drivers/common/cnxk/roc_api.h +++ b/drivers/common/cnxk/roc_api.h @@ -33,6 +33,7 @@ /* HW structure definition */ #include "hw/cpt.h" +#include "hw/dpi.h" #include "hw/nix.h" #include "hw/npa.h" #include "hw/npc.h" @@ -86,6 +87,9 @@ #include "roc_ie_ot.h" #include "roc_se.h" +/* DPI */ +#include "roc_dpi.h" + /* HASH computation */ #include "roc_hash.h" diff --git a/drivers/common/cnxk/roc_dpi.c b/drivers/common/cnxk/roc_dpi.c new file mode 100644 index 0000000000..a9613d82f1 --- /dev/null +++ b/drivers/common/cnxk/roc_dpi.c @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "roc_api.h" +#include "roc_priv.h" +#include +#include +#include +#include + +#define DPI_PF_MBOX_SYSFS_ENTRY "dpi_device_config" + +static inline int +send_msg_to_pf(struct plt_pci_addr *pci_addr, const char *value, int size) +{ + char buf[255] = {0}; + int res, fd; + + res = snprintf( + buf, sizeof(buf), "/sys/bus/pci/devices/" PCI_PRI_FMT "/%s", + pci_addr->domain, pci_addr->bus, DPI_PF_DBDF_DEVICE & 0x7, + DPI_PF_DBDF_FUNCTION & 0x7, DPI_PF_MBOX_SYSFS_ENTRY); + + if ((res < 0) || ((size_t)res > sizeof(buf))) + return -ERANGE; + + fd = open(buf, O_WRONLY); + if (fd < 0) + return -EACCES; + + res = write(fd, value, size); + close(fd); + if (res < 0) + return -EACCES; + + return 0; +} + +int +roc_dpi_queue_start(struct roc_dpi *dpi) +{ + plt_write64(0x1, dpi->rbase + DPI_VDMA_EN); + return 0; +} + +int +roc_dpi_queue_stop(struct roc_dpi *dpi) +{ + plt_write64(0x0, dpi->rbase + DPI_VDMA_EN); + return 0; +} + +int +roc_dpi_queue_configure(struct roc_dpi *roc_dpi) +{ + struct plt_pci_device *pci_dev; + const struct plt_memzone *dpi_mz; + dpi_mbox_msg_t mbox_msg; + struct npa_pool_s pool; + struct npa_aura_s aura; + int rc, count, buflen; + uint64_t aura_handle; + plt_iova_t iova; + char name[32]; + + if (!roc_dpi) { + plt_err("roc_dpi is NULL"); + return -EINVAL; + } + + pci_dev = roc_dpi->pci_dev; + memset(&pool, 0, sizeof(struct npa_pool_s)); + pool.nat_align = 1; + + memset(&aura, 0, sizeof(aura)); + rc = roc_npa_pool_create(&aura_handle, DPI_CMD_QUEUE_SIZE, + DPI_CMD_QUEUE_BUFS, &aura, &pool); + if (rc) { + plt_err("Failed to create NPA pool, err %d\n", rc); + return rc; + } + + snprintf(name, sizeof(name), "dpimem%d", roc_dpi->vfid); + buflen = DPI_CMD_QUEUE_SIZE * DPI_CMD_QUEUE_BUFS; + dpi_mz = plt_memzone_reserve_aligned(name, buflen, 0, + DPI_CMD_QUEUE_SIZE); + if (dpi_mz == NULL) { + plt_err("dpi memzone reserve failed"); + rc = -ENOMEM; + goto err1; + } + + roc_dpi->mz = dpi_mz; + iova = dpi_mz->iova; + for (count = 0; count < DPI_CMD_QUEUE_BUFS; count++) { + roc_npa_aura_op_free(aura_handle, 0, iova); + iova += DPI_CMD_QUEUE_SIZE; + } + + roc_dpi->chunk_base = (void *)roc_npa_aura_op_alloc(aura_handle, 0); + if (!roc_dpi->chunk_base) { + plt_err("Failed to alloc buffer from NPA aura"); + rc = -ENOMEM; + goto err2; + } + + roc_dpi->chunk_next = (void *)roc_npa_aura_op_alloc(aura_handle, 0); + if (!roc_dpi->chunk_next) { + plt_err("Failed to alloc buffer from NPA aura"); + rc = -ENOMEM; + goto err2; + } + + roc_dpi->aura_handle = aura_handle; + /* subtract 2 as they have already been alloc'ed above */ + roc_dpi->pool_size_m1 = (DPI_CMD_QUEUE_SIZE >> 3) - 2; + + plt_write64(0x0, roc_dpi->rbase + DPI_VDMA_REQQ_CTL); + plt_write64(((uint64_t)(roc_dpi->chunk_base) >> 7) << 7, + roc_dpi->rbase + DPI_VDMA_SADDR); + mbox_msg.u[0] = 0; + mbox_msg.u[1] = 0; + /* DPI PF driver expects vfid starts from index 0 */ + mbox_msg.s.vfid = roc_dpi->vfid; + mbox_msg.s.cmd = DPI_QUEUE_OPEN; + mbox_msg.s.csize = DPI_CMD_QUEUE_SIZE; + mbox_msg.s.aura = roc_npa_aura_handle_to_aura(aura_handle); + mbox_msg.s.sso_pf_func = idev_sso_pffunc_get(); + mbox_msg.s.npa_pf_func = idev_npa_pffunc_get(); + + rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg, + sizeof(dpi_mbox_msg_t)); + if (rc < 0) { + plt_err("Failed to send mbox message %d to DPI PF, err %d", + mbox_msg.s.cmd, rc); + goto err2; + } + + return rc; + +err2: + roc_npa_pool_destroy(aura_handle); +err1: + plt_memzone_free(dpi_mz); + return rc; +} + +int +roc_dpi_dev_init(struct roc_dpi *roc_dpi) +{ + struct plt_pci_device *pci_dev = roc_dpi->pci_dev; + uint16_t vfid; + + roc_dpi->rbase = pci_dev->mem_resource[0].addr; + vfid = ((pci_dev->addr.devid & 0x1F) << 3) | + (pci_dev->addr.function & 0x7); + vfid -= 1; + roc_dpi->vfid = vfid; + plt_spinlock_init(&roc_dpi->chunk_lock); + + return 0; +} + +int +roc_dpi_dev_fini(struct roc_dpi *roc_dpi) +{ + struct plt_pci_device *pci_dev = roc_dpi->pci_dev; + dpi_mbox_msg_t mbox_msg; + uint64_t reg; + int rc; + + /* Wait for SADDR to become idle */ + reg = plt_read64(roc_dpi->rbase + DPI_VDMA_SADDR); + while (!(reg & BIT_ULL(63))) + reg = plt_read64(roc_dpi->rbase + DPI_VDMA_SADDR); + + mbox_msg.u[0] = 0; + mbox_msg.u[1] = 0; + mbox_msg.s.vfid = roc_dpi->vfid; + mbox_msg.s.cmd = DPI_QUEUE_CLOSE; + + rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg, + sizeof(dpi_mbox_msg_t)); + if (rc < 0) + plt_err("Failed to send mbox message %d to DPI PF, err %d", + mbox_msg.s.cmd, rc); + + roc_npa_pool_destroy(roc_dpi->aura_handle); + plt_memzone_free(roc_dpi->mz); + + return rc; +} diff --git a/drivers/common/cnxk/roc_dpi.h b/drivers/common/cnxk/roc_dpi.h new file mode 100644 index 0000000000..c2e6d997ea --- /dev/null +++ b/drivers/common/cnxk/roc_dpi.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _ROC_DPI_H_ +#define _ROC_DPI_H_ + +struct roc_dpi_args { + uint8_t num_ssegs; + uint8_t num_dsegs; + uint8_t comp_type; + uint8_t direction; + uint8_t sdevice; + uint8_t ddevice; + uint8_t swap; + uint8_t use_lock : 1; + uint8_t tt : 7; + uint16_t func; + uint16_t grp; + uint32_t tag; + uint64_t comp_ptr; +}; + +struct roc_dpi { + struct plt_pci_device *pci_dev; + const struct plt_memzone *mz; + uint8_t *rbase; + uint16_t vfid; + uint16_t pool_size_m1; + uint16_t chunk_head; + uint64_t *chunk_base; + uint64_t *chunk_next; + uint64_t aura_handle; + plt_spinlock_t chunk_lock; +} __plt_cache_aligned; + +int __roc_api roc_dpi_dev_init(struct roc_dpi *roc_dpi); +int __roc_api roc_dpi_dev_fini(struct roc_dpi *roc_dpi); + +int __roc_api roc_dpi_queue_configure(struct roc_dpi *dpi); +int __roc_api roc_dpi_queue_start(struct roc_dpi *dpi); +int __roc_api roc_dpi_queue_stop(struct roc_dpi *dpi); + +#endif diff --git a/drivers/common/cnxk/roc_dpi_priv.h b/drivers/common/cnxk/roc_dpi_priv.h new file mode 100644 index 0000000000..92953fbcfc --- /dev/null +++ b/drivers/common/cnxk/roc_dpi_priv.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _ROC_DPI_PRIV_H_ +#define _ROC_DPI_PRIV_H_ + +#define DPI_MAX_VFS 8 + +/* DPI PF DBDF information macros */ +#define DPI_PF_DBDF_DEVICE 0 +#define DPI_PF_DBDF_FUNCTION 0 + +#define DPI_QUEUE_OPEN 0x1 +#define DPI_QUEUE_CLOSE 0x2 +#define DPI_REG_DUMP 0x3 +#define DPI_GET_REG_CFG 0x4 + +#define DPI_CMD_QUEUE_SIZE 4096 +#define DPI_CMD_QUEUE_BUFS 1024 + +typedef union dpi_mbox_msg_t { + uint64_t u[2]; + struct dpi_mbox_message_s { + /* VF ID to configure */ + uint64_t vfid : 4; + /* Command code */ + uint64_t cmd : 4; + /* Command buffer size in 8-byte words */ + uint64_t csize : 14; + /* aura of the command buffer */ + uint64_t aura : 20; + /* SSO PF function */ + uint64_t sso_pf_func : 16; + /* NPA PF function */ + uint64_t npa_pf_func : 16; + } s; +} dpi_mbox_msg_t; + +#endif diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index 5da23fe5f8..61d4781209 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -69,6 +69,7 @@ #define __roc_api __rte_internal #define plt_iova_t rte_iova_t +#define plt_pci_addr rte_pci_addr #define plt_pci_device rte_pci_device #define plt_pci_read_config rte_pci_read_config #define plt_pci_find_ext_capability rte_pci_find_ext_capability diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h index f72bbd568f..782b90cf8d 100644 --- a/drivers/common/cnxk/roc_priv.h +++ b/drivers/common/cnxk/roc_priv.h @@ -41,4 +41,7 @@ /* NIX Inline dev */ #include "roc_nix_inl_priv.h" +/* DPI */ +#include "roc_dpi_priv.h" + #endif /* _ROC_PRIV_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 8d4d42f476..3edc42cfd6 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -68,6 +68,11 @@ INTERNAL { roc_cpt_lmtline_init; roc_cpt_parse_hdr_dump; roc_cpt_rxc_time_cfg; + roc_dpi_dev_init; + roc_dpi_dev_fini; + roc_dpi_queue_configure; + roc_dpi_queue_start; + roc_dpi_queue_stop; roc_error_msg_get; roc_hash_sha1_gen; roc_hash_sha256_gen; From patchwork Tue Oct 26 04:12:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Radha Chintakuntla X-Patchwork-Id: 102831 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9CF4CA0C47; Tue, 26 Oct 2021 06:13:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 153FD40A4B; Tue, 26 Oct 2021 06:13:27 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id D61324003E for ; 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Mon, 25 Oct 2021 21:13:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 25 Oct 2021 21:13:21 -0700 Received: from rchintakuntla-lnx3.caveonetworks.com (unknown [10.111.140.81]) by maili.marvell.com (Postfix) with ESMTP id CFDA53F708F; Mon, 25 Oct 2021 21:13:21 -0700 (PDT) From: Radha Mohan Chintakuntla To: , , , , , , , CC: , Radha Mohan Chintakuntla Date: Mon, 25 Oct 2021 21:12:58 -0700 Message-ID: <20211026041300.28924-2-radhac@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211026041300.28924-1-radhac@marvell.com> References: <20211026041300.28924-1-radhac@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: FDFYxveDF_BJWknFxnvr9LA8m2SBp6Sr X-Proofpoint-ORIG-GUID: FDFYxveDF_BJWknFxnvr9LA8m2SBp6Sr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-25_08,2021-10-25_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH 2/4] dma/cnxk: create and initialize dmadev on pci probe X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch creates and initializes a dmadev device on pci probe. Signed-off-by: Radha Mohan Chintakuntla --- MAINTAINERS | 7 +- doc/guides/dmadevs/cnxk.rst | 53 +++++++++++++++ doc/guides/dmadevs/index.rst | 1 + drivers/dma/cnxk/cnxk_dmadev.c | 119 +++++++++++++++++++++++++++++++++ drivers/dma/cnxk/cnxk_dmadev.h | 11 +++ drivers/dma/cnxk/meson.build | 7 ++ drivers/dma/meson.build | 1 + 7 files changed, 198 insertions(+), 1 deletion(-) create mode 100644 doc/guides/dmadevs/cnxk.rst create mode 100644 drivers/dma/cnxk/cnxk_dmadev.c create mode 100644 drivers/dma/cnxk/cnxk_dmadev.h create mode 100644 drivers/dma/cnxk/meson.build diff --git a/MAINTAINERS b/MAINTAINERS index be2c9b6815..cdc2d98a6b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1186,7 +1186,6 @@ F: drivers/compress/zlib/ F: doc/guides/compressdevs/zlib.rst F: doc/guides/compressdevs/features/zlib.ini - DMAdev Drivers -------------- @@ -1202,6 +1201,12 @@ M: Conor Walsh F: drivers/dma/ioat/ F: doc/guides/dmadevs/ioat.rst +Marvell CNXK DPI DMA +M: Radha Mohan Chintakuntla +M: Veerasenareddy Burru +F: drivers/dma/cnxk/ +F: doc/guides/dmadevs/cnxk.rst + RegEx Drivers ------------- diff --git a/doc/guides/dmadevs/cnxk.rst b/doc/guides/dmadevs/cnxk.rst new file mode 100644 index 0000000000..8ae7c1f8cd --- /dev/null +++ b/doc/guides/dmadevs/cnxk.rst @@ -0,0 +1,53 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2021 Marvell International Ltd. + +.. include:: + +CNXK DMA Device Driver +====================== + +The ``cnxk`` dmadev driver provides a poll-mode driver (PMD) for Marvell DPI DMA +Hardware Accelerator block found in OCTEONTX2 and OCTEONTX3 family of SoCs. Each +DMA queue is exposed as a VF function when SRIOV is enabled. + +The block supports following modes of DMA transfers + +#. Internal - DMA within SoC DRAM to DRAM + +#. Inbound - Host DRAM to SoC DRAM when SoC is in PCIe Endpoint + +#. Outbound - SoC DRAM to Host DRAM when SoC is in PCIe Endpoint + +Device Setup +------------- +The ``dpdk-devbind.py`` script, included with DPDK, can be used to show the +presence of supported hardware. Running ``dpdk-devbind.py --status-dev dma`` +will show all the CNXK DMA devices. + +Devices using VFIO drivers +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The HW devices to be used will need to be bound to a user-space IO driver for use. +The ``dpdk-devbind.py`` script can be used to view the state of the devices +and to bind them to a suitable DPDK-supported driver, such as ``vfio-pci``. +For example:: + + $ dpdk-devbind.py -b vfio-pci 0000:05:00.1 + +Device Probing and Initialization +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To use the devices from an application, the dmadev API can be used. +CNXK DMA device configuration requirements: + +* Only one ``vchan`` is supported per device. +* CNXK DMA devices do not support silent mode. + +Once configured, the device can then be made ready for use by calling the + ``rte_dma_start()`` API. + +Performing Data Copies +~~~~~~~~~~~~~~~~~~~~~~~ + +Refer to the :ref:`Enqueue / Dequeue APIs ` section of the dmadev library +documentation for details on operation enqueue and submission API usage. diff --git a/doc/guides/dmadevs/index.rst b/doc/guides/dmadevs/index.rst index 20476039a5..227fa00c68 100644 --- a/doc/guides/dmadevs/index.rst +++ b/doc/guides/dmadevs/index.rst @@ -11,5 +11,6 @@ an application through DMA API. :maxdepth: 2 :numbered: + cnxk idxd ioat diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c new file mode 100644 index 0000000000..620766743d --- /dev/null +++ b/drivers/dma/cnxk/cnxk_dmadev.c @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2021 Marvell International Ltd. + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static int +cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + struct cnxk_dpi_vf_s *dpivf = NULL; + char name[RTE_DEV_NAME_MAX_LEN]; + struct rte_dma_dev *dmadev; + struct roc_dpi *rdpi = NULL; + int rc; + + if (!pci_dev->mem_resource[0].addr) + return -ENODEV; + + rc = roc_plt_init(); + if (rc) { + plt_err("Failed to initialize platform model, rc=%d", rc); + return rc; + } + memset(name, 0, sizeof(name)); + rte_pci_device_name(&pci_dev->addr, name, sizeof(name)); + + dmadev = rte_dma_pmd_allocate(name, pci_dev->device.numa_node, + sizeof(*dpivf)); + if (dmadev == NULL) { + plt_err("dma device allocation failed for %s", name); + return -ENOMEM; + } + + dpivf = dmadev->data->dev_private; + + dmadev->device = &pci_dev->device; + dmadev->fp_obj->dev_private = dpivf; + + rdpi = &dpivf->rdpi; + + rdpi->pci_dev = pci_dev; + rc = roc_dpi_dev_init(rdpi); + if (rc < 0) + goto err_out_free; + + return 0; + +err_out_free: + if (dmadev) + rte_dma_pmd_release(name); + + return rc; +} + +static int +cnxk_dmadev_remove(struct rte_pci_device *pci_dev) +{ + char name[RTE_DEV_NAME_MAX_LEN]; + struct rte_dma_dev *dmadev; + struct cnxk_dpi_vf_s *dpivf; + int dev_id; + + memset(name, 0, sizeof(name)); + rte_pci_device_name(&pci_dev->addr, name, sizeof(name)); + + dev_id = rte_dma_get_dev_id_by_name(name); + if (dev_id < 0) { + plt_err("Invalid device ID"); + return -EINVAL; + } + + dmadev = &rte_dma_devices[dev_id]; + if (!dmadev) { + plt_err("dmadev with name %s not found\n", name); + return -ENODEV; + } + + dpivf = dmadev->fp_obj->dev_private; + roc_dpi_queue_stop(&dpivf->rdpi); + roc_dpi_dev_fini(&dpivf->rdpi); + + return rte_dma_pmd_release(name); +} + +static const struct rte_pci_id cnxk_dma_pci_map[] = { + { + RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, + PCI_DEVID_CNXK_DPI_VF) + }, + { + .vendor_id = 0, + }, +}; + +static struct rte_pci_driver cnxk_dmadev = { + .id_table = cnxk_dma_pci_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA, + .probe = cnxk_dmadev_probe, + .remove = cnxk_dmadev_remove, +}; + +RTE_PMD_REGISTER_PCI(cnxk_dmadev_pci_driver, cnxk_dmadev); +RTE_PMD_REGISTER_PCI_TABLE(cnxk_dmadev_pci_driver, cnxk_dma_pci_map); +RTE_PMD_REGISTER_KMOD_DEP(cnxk_dmadev_pci_driver, "vfio-pci"); diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h new file mode 100644 index 0000000000..9e0bb7b2ce --- /dev/null +++ b/drivers/dma/cnxk/cnxk_dmadev.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell International Ltd. + */ +#ifndef _CNXK_DMADEV_H_ +#define _CNXK_DMADEV_H_ + +struct cnxk_dpi_vf_s { + struct roc_dpi rdpi; +}; + +#endif diff --git a/drivers/dma/cnxk/meson.build b/drivers/dma/cnxk/meson.build new file mode 100644 index 0000000000..9489d6e6dc --- /dev/null +++ b/drivers/dma/cnxk/meson.build @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(C) 2021 Marvell International Ltd. +# + +deps += ['bus_pci', 'common_cnxk', 'dmadev'] +sources = files('cnxk_dmadev.c') +headers = files('cnxk_dmadev.h') diff --git a/drivers/dma/meson.build b/drivers/dma/meson.build index a69418ce9b..c562c8b429 100644 --- a/drivers/dma/meson.build +++ b/drivers/dma/meson.build @@ -2,6 +2,7 @@ # Copyright 2021 HiSilicon Limited drivers = [ + 'cnxk', 'idxd', 'ioat', 'skeleton', From patchwork Tue Oct 26 04:12:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Radha Chintakuntla X-Patchwork-Id: 102834 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1C006A0C47; Tue, 26 Oct 2021 06:13:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DA3B241173; Tue, 26 Oct 2021 06:13:29 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 847C740A4B for ; Tue, 26 Oct 2021 06:13:25 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19PLKxk5012626; Mon, 25 Oct 2021 21:13:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; 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Mon, 25 Oct 2021 21:13:22 -0700 (PDT) From: Radha Mohan Chintakuntla To: , , , , , , , CC: , Radha Mohan Chintakuntla Date: Mon, 25 Oct 2021 21:12:59 -0700 Message-ID: <20211026041300.28924-3-radhac@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211026041300.28924-1-radhac@marvell.com> References: <20211026041300.28924-1-radhac@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: c6yF7zaCDraoPPMrjjnTBF0nATeH5Tzi X-Proofpoint-ORIG-GUID: c6yF7zaCDraoPPMrjjnTBF0nATeH5Tzi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-25_08,2021-10-25_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH 3/4] dma/cnxk: add dma channel operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add functions for the dmadev vchan setup and DMA operations. Signed-off-by: Radha Mohan Chintakuntla --- drivers/dma/cnxk/cnxk_dmadev.c | 322 +++++++++++++++++++++++++++++++++ drivers/dma/cnxk/cnxk_dmadev.h | 53 ++++++ drivers/dma/cnxk/version.map | 3 + 3 files changed, 378 insertions(+) create mode 100644 drivers/dma/cnxk/version.map diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c index 620766743d..8434579aa2 100644 --- a/drivers/dma/cnxk/cnxk_dmadev.c +++ b/drivers/dma/cnxk/cnxk_dmadev.c @@ -18,6 +18,322 @@ #include #include +static int +cnxk_dmadev_info_get(const struct rte_dma_dev *dev, + struct rte_dma_info *dev_info, uint32_t size) +{ + RTE_SET_USED(dev); + RTE_SET_USED(size); + + dev_info->max_vchans = 1; + dev_info->nb_vchans = 1; + dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM | + RTE_DMA_CAPA_MEM_TO_DEV | RTE_DMA_CAPA_DEV_TO_MEM | + RTE_DMA_CAPA_OPS_COPY; + dev_info->max_desc = DPI_MAX_DESC; + dev_info->min_desc = 1; + dev_info->max_sges = DPI_MAX_POINTER; + + return 0; +} + +static int +cnxk_dmadev_configure(struct rte_dma_dev *dev, + const struct rte_dma_conf *conf, uint32_t conf_sz) +{ + struct cnxk_dpi_vf_s *dpivf = NULL; + int rc = 0; + + RTE_SET_USED(conf); + RTE_SET_USED(conf); + RTE_SET_USED(conf_sz); + RTE_SET_USED(conf_sz); + dpivf = dev->fp_obj->dev_private; + rc = roc_dpi_queue_configure(&dpivf->rdpi); + if (rc < 0) + plt_err("DMA queue configure failed err = %d", rc); + + return rc; +} + +static int +cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan, + const struct rte_dma_vchan_conf *conf, + uint32_t conf_sz) +{ + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private; + struct cnxk_dpi_compl_s *comp_data; + int i; + + RTE_SET_USED(vchan); + RTE_SET_USED(conf_sz); + + switch (conf->direction) { + case RTE_DMA_DIR_DEV_TO_MEM: + dpivf->conf.direction = DPI_XTYPE_INBOUND; + dpivf->conf.src_port = conf->src_port.pcie.coreid; + dpivf->conf.dst_port = 0; + break; + case RTE_DMA_DIR_MEM_TO_DEV: + dpivf->conf.direction = DPI_XTYPE_OUTBOUND; + dpivf->conf.src_port = 0; + dpivf->conf.dst_port = conf->dst_port.pcie.coreid; + break; + case RTE_DMA_DIR_MEM_TO_MEM: + dpivf->conf.direction = DPI_XTYPE_INTERNAL_ONLY; + dpivf->conf.src_port = 0; + dpivf->conf.dst_port = 0; + break; + case RTE_DMA_DIR_DEV_TO_DEV: + dpivf->conf.direction = DPI_XTYPE_EXTERNAL_ONLY; + dpivf->conf.src_port = conf->src_port.pcie.coreid; + dpivf->conf.dst_port = conf->src_port.pcie.coreid; + }; + + for (i = 0; i < conf->nb_desc; i++) { + comp_data = rte_zmalloc(NULL, sizeof(*comp_data), 0); + dpivf->conf.c_desc.compl_ptr[i] = comp_data; + }; + dpivf->conf.c_desc.max_cnt = DPI_MAX_DESC; + dpivf->conf.c_desc.head = 0; + dpivf->conf.c_desc.tail = 0; + + return 0; +} + +static int +cnxk_dmadev_start(struct rte_dma_dev *dev) +{ + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private; + + roc_dpi_queue_start(&dpivf->rdpi); + + return 0; +} + +static int +cnxk_dmadev_stop(struct rte_dma_dev *dev) +{ + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private; + + roc_dpi_queue_stop(&dpivf->rdpi); + + return 0; +} + +static int +cnxk_dmadev_close(struct rte_dma_dev *dev) +{ + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private; + + roc_dpi_queue_stop(&dpivf->rdpi); + roc_dpi_dev_fini(&dpivf->rdpi); + + return 0; +} + +static inline int +__dpi_queue_write(struct roc_dpi *dpi, uint64_t *cmds, int cmd_count) +{ + uint64_t *ptr = dpi->chunk_base; + + if ((cmd_count < DPI_MIN_CMD_SIZE) || (cmd_count > DPI_MAX_CMD_SIZE) || + cmds == NULL) + return -EINVAL; + + /* + * Normally there is plenty of room in the current buffer for the + * command + */ + if (dpi->chunk_head + cmd_count < dpi->pool_size_m1) { + ptr += dpi->chunk_head; + dpi->chunk_head += cmd_count; + while (cmd_count--) + *ptr++ = *cmds++; + } else { + int count; + uint64_t *new_buff = dpi->chunk_next; + + dpi->chunk_next = + (void *)roc_npa_aura_op_alloc(dpi->aura_handle, 0); + if (!dpi->chunk_next) { + plt_err("Failed to alloc next buffer from NPA"); + return -ENOMEM; + } + + /* + * Figure out how many cmd words will fit in this buffer. + * One location will be needed for the next buffer pointer. + */ + count = dpi->pool_size_m1 - dpi->chunk_head; + ptr += dpi->chunk_head; + cmd_count -= count; + while (count--) + *ptr++ = *cmds++; + + /* + * chunk next ptr is 2 DWORDS + * second DWORD is reserved. + */ + *ptr++ = (uint64_t)new_buff; + *ptr = 0; + + /* + * The current buffer is full and has a link to the next + * buffers. Time to write the rest of the commands into the new + * buffer. + */ + dpi->chunk_base = new_buff; + dpi->chunk_head = cmd_count; + ptr = new_buff; + while (cmd_count--) + *ptr++ = *cmds++; + + /* queue index may be greater than pool size */ + if (dpi->chunk_head >= dpi->pool_size_m1) { + new_buff = dpi->chunk_next; + dpi->chunk_next = + (void *)roc_npa_aura_op_alloc(dpi->aura_handle, + 0); + if (!dpi->chunk_next) { + plt_err("Failed to alloc next buffer from NPA"); + return -ENOMEM; + } + /* Write next buffer address */ + *ptr = (uint64_t)new_buff; + dpi->chunk_base = new_buff; + dpi->chunk_head = 0; + } + } + + return 0; +} + +static int +cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src, + rte_iova_t dst, uint32_t length, uint64_t flags) +{ + uint64_t cmd[DPI_MAX_CMD_SIZE] = {0}; + union dpi_instr_hdr_s *header = (union dpi_instr_hdr_s *)&cmd[0]; + rte_iova_t fptr, lptr; + struct cnxk_dpi_vf_s *dpivf = dev_private; + struct cnxk_dpi_compl_s *comp_ptr; + int num_words = 0; + int rc; + + RTE_SET_USED(vchan); + + header->s.xtype = dpivf->conf.direction; + header->s.pt = DPI_HDR_PT_ZBW_CA; + comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail]; + comp_ptr->cdata = DPI_REQ_CDATA; + header->s.ptr = (uint64_t)comp_ptr; + STRM_INC(dpivf->conf.c_desc); + + /* pvfe should be set for inbound and outbound only */ + if (header->s.xtype <= 1) + header->s.pvfe = 1; + num_words += 4; + + header->s.nfst = 1; + header->s.nlst = 1; + /* + * For inbound case, src pointers are last pointers. + * For all other cases, src pointers are first pointers. + */ + if (header->s.xtype == DPI_XTYPE_INBOUND) { + fptr = dst; + lptr = src; + header->s.fport = dpivf->conf.dst_port & 0x3; + header->s.lport = dpivf->conf.src_port & 0x3; + } else { + fptr = src; + lptr = dst; + header->s.fport = dpivf->conf.src_port & 0x3; + header->s.lport = dpivf->conf.dst_port & 0x3; + } + + cmd[num_words++] = length; + cmd[num_words++] = fptr; + cmd[num_words++] = length; + cmd[num_words++] = lptr; + + rc = __dpi_queue_write(&dpivf->rdpi, cmd, num_words); + if (!rc) { + if (flags & RTE_DMA_OP_FLAG_SUBMIT) { + rte_wmb(); + plt_write64(num_words, + dpivf->rdpi.rbase + DPI_VDMA_DBELL); + } + dpivf->num_words = num_words; + } + + return rc; +} + +static uint16_t +cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls, + uint16_t *last_idx, bool *has_error) +{ + struct cnxk_dpi_vf_s *dpivf = dev_private; + int cnt; + + RTE_SET_USED(vchan); + RTE_SET_USED(last_idx); + RTE_SET_USED(has_error); + for (cnt = 0; cnt < nb_cpls; cnt++) { + struct cnxk_dpi_compl_s *comp_ptr = + dpivf->conf.c_desc.compl_ptr[cnt]; + + if (comp_ptr->cdata) + break; + } + + dpivf->conf.c_desc.tail = cnt; + + return cnt; +} + +static uint16_t +cnxk_dmadev_completed_status(void *dev_private, uint16_t vchan, + const uint16_t nb_cpls, uint16_t *last_idx, + enum rte_dma_status_code *status) +{ + struct cnxk_dpi_vf_s *dpivf = dev_private; + int cnt; + + RTE_SET_USED(vchan); + RTE_SET_USED(last_idx); + for (cnt = 0; cnt < nb_cpls; cnt++) { + struct cnxk_dpi_compl_s *comp_ptr = + dpivf->conf.c_desc.compl_ptr[cnt]; + status[cnt] = comp_ptr->cdata; + } + + dpivf->conf.c_desc.tail = 0; + return cnt; +} + +static int +cnxk_dmadev_submit(void *dev_private, uint16_t vchan __rte_unused) +{ + struct cnxk_dpi_vf_s *dpivf = dev_private; + + rte_wmb(); + plt_write64(dpivf->num_words, dpivf->rdpi.rbase + DPI_VDMA_DBELL); + + return 0; +} + +static const struct rte_dma_dev_ops cnxk_dmadev_ops = { + .dev_info_get = cnxk_dmadev_info_get, + .dev_configure = cnxk_dmadev_configure, + .dev_start = cnxk_dmadev_start, + .dev_stop = cnxk_dmadev_stop, + .vchan_setup = cnxk_dmadev_vchan_setup, + .dev_close = cnxk_dmadev_close, +}; + static int cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev) @@ -50,6 +366,12 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused, dmadev->device = &pci_dev->device; dmadev->fp_obj->dev_private = dpivf; + dmadev->dev_ops = &cnxk_dmadev_ops; + + dmadev->fp_obj->copy = cnxk_dmadev_copy; + dmadev->fp_obj->submit = cnxk_dmadev_submit; + dmadev->fp_obj->completed = cnxk_dmadev_completed; + dmadev->fp_obj->completed_status = cnxk_dmadev_completed_status; rdpi = &dpivf->rdpi; diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h index 9e0bb7b2ce..ce301a5945 100644 --- a/drivers/dma/cnxk/cnxk_dmadev.h +++ b/drivers/dma/cnxk/cnxk_dmadev.h @@ -4,8 +4,61 @@ #ifndef _CNXK_DMADEV_H_ #define _CNXK_DMADEV_H_ +#define DPI_MAX_POINTER 15 +#define DPI_QUEUE_STOP 0x0 +#define DPI_QUEUE_START 0x1 +#define STRM_INC(s) ((s).tail = ((s).tail + 1) % (s).max_cnt) +#define DPI_MAX_DESC DPI_MAX_POINTER + +/* DPI Transfer Type, pointer type in DPI_DMA_INSTR_HDR_S[XTYPE] */ +#define DPI_XTYPE_OUTBOUND (0) +#define DPI_XTYPE_INBOUND (1) +#define DPI_XTYPE_INTERNAL_ONLY (2) +#define DPI_XTYPE_EXTERNAL_ONLY (3) +#define DPI_XTYPE_MASK 0x3 +#define DPI_HDR_PT_ZBW_CA 0x0 +#define DPI_HDR_PT_ZBW_NC 0x1 +#define DPI_HDR_PT_WQP 0x2 +#define DPI_HDR_PT_WQP_NOSTATUS 0x0 +#define DPI_HDR_PT_WQP_STATUSCA 0x1 +#define DPI_HDR_PT_WQP_STATUSNC 0x3 +#define DPI_HDR_PT_CNT 0x3 +#define DPI_HDR_PT_MASK 0x3 +#define DPI_W0_TT_MASK 0x3 +#define DPI_W0_GRP_MASK 0x3FF + +/* Set Completion data to 0xFF when request submitted, + * upon successful request completion engine reset to completion status + */ +#define DPI_REQ_CDATA 0xFF + +#define DPI_MIN_CMD_SIZE 8 +#define DPI_MAX_CMD_SIZE 64 + +struct cnxk_dpi_compl_s { + uint64_t cdata; + void *cb_data; +}; + +struct cnxk_dpi_cdesc_data_s { + struct cnxk_dpi_compl_s *compl_ptr[DPI_MAX_DESC]; + uint16_t max_cnt; + uint16_t head; + uint16_t tail; +}; + +struct cnxk_dpi_queue_conf { + uint8_t direction; + uint8_t src_port; + uint8_t dst_port; + uint64_t comp_ptr; + struct cnxk_dpi_cdesc_data_s c_desc; +}; + struct cnxk_dpi_vf_s { struct roc_dpi rdpi; + struct cnxk_dpi_queue_conf conf; + uint32_t num_words; }; #endif diff --git a/drivers/dma/cnxk/version.map b/drivers/dma/cnxk/version.map new file mode 100644 index 0000000000..4a76d1d52d --- /dev/null +++ b/drivers/dma/cnxk/version.map @@ -0,0 +1,3 @@ +DPDK_21 { + local: *; +}; From patchwork Tue Oct 26 04:13:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Radha Chintakuntla X-Patchwork-Id: 102833 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BDB89A0C47; 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Mon, 25 Oct 2021 21:13:24 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 25 Oct 2021 21:13:22 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 25 Oct 2021 21:13:22 -0700 Received: from rchintakuntla-lnx3.caveonetworks.com (unknown [10.111.140.81]) by maili.marvell.com (Postfix) with ESMTP id 495F63F7095; Mon, 25 Oct 2021 21:13:22 -0700 (PDT) From: Radha Mohan Chintakuntla To: , , , , , , , CC: , Radha Mohan Chintakuntla Date: Mon, 25 Oct 2021 21:13:00 -0700 Message-ID: <20211026041300.28924-4-radhac@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211026041300.28924-1-radhac@marvell.com> References: <20211026041300.28924-1-radhac@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: VzZqqq5zKHODq1TaOEC0Lmn58_gr81G_ X-Proofpoint-ORIG-GUID: VzZqqq5zKHODq1TaOEC0Lmn58_gr81G_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-25_08,2021-10-25_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH 4/4] dma/cnxk: add copy_sg function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add the copy_sg function that will do the multiple DMA transfers of different sizes and different source/destination as well. Signed-off-by: Radha Mohan Chintakuntla --- drivers/dma/cnxk/cnxk_dmadev.c | 80 +++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c index 8434579aa2..f15ea16c5f 100644 --- a/drivers/dma/cnxk/cnxk_dmadev.c +++ b/drivers/dma/cnxk/cnxk_dmadev.c @@ -29,7 +29,7 @@ cnxk_dmadev_info_get(const struct rte_dma_dev *dev, dev_info->nb_vchans = 1; dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM | RTE_DMA_CAPA_MEM_TO_DEV | RTE_DMA_CAPA_DEV_TO_MEM | - RTE_DMA_CAPA_OPS_COPY; + RTE_DMA_CAPA_OPS_COPY | RTE_DMA_CAPA_OPS_COPY_SG; dev_info->max_desc = DPI_MAX_DESC; dev_info->min_desc = 1; dev_info->max_sges = DPI_MAX_POINTER; @@ -294,6 +294,83 @@ cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls, return cnt; } +static int +cnxk_dmadev_copy_sg(void *dev_private, uint16_t vchan, + const struct rte_dma_sge *src, + const struct rte_dma_sge *dst, + uint16_t nb_src, uint16_t nb_dst, uint64_t flags) +{ + uint64_t cmd[DPI_MAX_CMD_SIZE] = {0}; + union dpi_instr_hdr_s *header = (union dpi_instr_hdr_s *)&cmd[0]; + struct cnxk_dpi_vf_s *dpivf = dev_private; + const struct rte_dma_sge *fptr, *lptr; + struct cnxk_dpi_compl_s *comp_ptr; + int num_words = 0; + int i, rc; + + RTE_SET_USED(vchan); + + header->s.xtype = dpivf->conf.direction; + header->s.pt = DPI_HDR_PT_ZBW_CA; + header->s.grp = 0; + header->s.tag = 0; + header->s.tt = 0; + header->s.func = 0; + comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail]; + comp_ptr->cdata = DPI_REQ_CDATA; + header->s.ptr = (uint64_t)comp_ptr; + STRM_INC(dpivf->conf.c_desc); + + /* pvfs should be set for inbound and outbound only */ + if (header->s.xtype <= 1) + header->s.pvfe = 1; + num_words += 4; + + /* + * For inbound case, src pointers are last pointers. + * For all other cases, src pointers are first pointers. + */ + if (header->s.xtype == DPI_XTYPE_INBOUND) { + header->s.nfst = nb_dst & 0xf; + header->s.nlst = nb_src & 0xf; + fptr = &dst[0]; + lptr = &src[0]; + header->s.fport = dpivf->conf.dst_port & 0x3; + header->s.lport = dpivf->conf.src_port & 0x3; + } else { + header->s.nfst = nb_src & 0xf; + header->s.nlst = nb_dst & 0xf; + fptr = &src[0]; + lptr = &dst[0]; + header->s.fport = dpivf->conf.src_port & 0x3; + header->s.lport = dpivf->conf.dst_port & 0x3; + } + + for (i = 0; i < header->s.nfst; i++) { + cmd[num_words++] = (uint64_t)fptr->length; + cmd[num_words++] = fptr->addr; + fptr++; + } + + for (i = 0; i < header->s.nlst; i++) { + cmd[num_words++] = (uint64_t)lptr->length; + cmd[num_words++] = lptr->addr; + lptr++; + } + + rc = __dpi_queue_write(&dpivf->rdpi, cmd, num_words); + if (!rc) { + if (flags & RTE_DMA_OP_FLAG_SUBMIT) { + rte_wmb(); + plt_write64(num_words, + dpivf->rdpi.rbase + DPI_VDMA_DBELL); + } + dpivf->num_words = num_words; + } + + return rc; +} + static uint16_t cnxk_dmadev_completed_status(void *dev_private, uint16_t vchan, const uint16_t nb_cpls, uint16_t *last_idx, @@ -369,6 +446,7 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused, dmadev->dev_ops = &cnxk_dmadev_ops; dmadev->fp_obj->copy = cnxk_dmadev_copy; + dmadev->fp_obj->copy_sg = cnxk_dmadev_copy_sg; dmadev->fp_obj->submit = cnxk_dmadev_submit; dmadev->fp_obj->completed = cnxk_dmadev_completed; dmadev->fp_obj->completed_status = cnxk_dmadev_completed_status;