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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT059.mail.protection.outlook.com (10.13.174.160) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4628.16 via Frontend Transport; Tue, 26 Oct 2021 15:14:12 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 26 Oct 2021 15:14:10 +0000 From: Alexander Kozyrev To: CC: , , , Date: Tue, 26 Oct 2021 18:13:57 +0300 Message-ID: <20211026151357.1349968-1-akozyrev@nvidia.com> X-Mailer: git-send-email 2.18.2 MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f5a74828-2acb-4c82-8b24-08d99893443e X-MS-TrafficTypeDiagnostic: DM6PR12MB3402: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(70586007)(8676002)(508600001)(5660300002)(70206006)(6666004)(6916009)(82310400003)(54906003)(47076005)(8936002)(1076003)(83380400001)(316002)(2616005)(107886003)(4326008)(6286002)(426003)(450100002)(36860700001)(2906002)(356005)(336012)(55016002)(7636003)(26005)(36756003)(186003)(86362001)(7696005)(16526019); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Oct 2021 15:14:12.1040 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f5a74828-2acb-4c82-8b24-08d99893443e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3402 Subject: [dpdk-dev] [PATCH] net/mlx5: fix Tx meta width for modify field flow rule X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Register C is used for the metadata within NIC Rx domain. And its width can vary from 0 to 32 bits depending on its kernel usage. But it is not the case within NIC Tx domain, register A is always 32 bits there. Fix metadata width detection for the modify_field flow API within NIC Tx domain. Fixes: 6d5735c1cb ("net/mlx5: fix meta register conversion for extensive mode") Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_dv.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 9cba22ca2d..1585888538 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1408,9 +1408,13 @@ flow_dv_convert_action_modify_ipv6_dscp } static int -mlx5_flow_item_field_width(struct mlx5_priv *priv, - enum rte_flow_field_id field, int inherit) +mlx5_flow_item_field_width(struct rte_eth_dev *dev, + enum rte_flow_field_id field, int inherit, + const struct rte_flow_attr *attr, + struct rte_flow_error *error) { + struct mlx5_priv *priv = dev->data->dev_private; + switch (field) { case RTE_FLOW_FIELD_START: return 32; @@ -1457,7 +1461,8 @@ mlx5_flow_item_field_width(struct mlx5_priv *priv, case RTE_FLOW_FIELD_MARK: return __builtin_popcount(priv->sh->dv_mark_mask); case RTE_FLOW_FIELD_META: - return __builtin_popcount(priv->sh->dv_meta_mask); + return (flow_dv_get_metadata_reg(dev, attr, error) == REG_C_0) ? + __builtin_popcount(priv->sh->dv_meta_mask) : 32; case RTE_FLOW_FIELD_POINTER: case RTE_FLOW_FIELD_VALUE: return inherit < 0 ? 0 : inherit; @@ -4833,10 +4838,12 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, struct mlx5_dev_config *config = &priv->config; const struct rte_flow_action_modify_field *action_modify_field = action->conf; - uint32_t dst_width = mlx5_flow_item_field_width(priv, - action_modify_field->dst.field, -1); - uint32_t src_width = mlx5_flow_item_field_width(priv, - action_modify_field->src.field, dst_width); + uint32_t dst_width = mlx5_flow_item_field_width(dev, + action_modify_field->dst.field, + -1, attr, error); + uint32_t src_width = mlx5_flow_item_field_width(dev, + action_modify_field->src.field, + dst_width, attr, error); ret = flow_dv_validate_action_modify_hdr(action_flags, action, error); if (ret)