From patchwork Tue Nov 2 15:54:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 103511 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 737EDA0C4E; Tue, 2 Nov 2021 16:54:32 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6148F41177; Tue, 2 Nov 2021 16:54:32 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 9D01941139 for ; Tue, 2 Nov 2021 16:54:31 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1A2CjiIM030527; Tue, 2 Nov 2021 08:54:27 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0220; bh=WwL/+rEhsDHznWd4QVpkCJGTgH5P/+LTIswaFp52/KM=; b=CMeWEFTw5rq1o3D3OLUA7ZnJwMXjleYForIn/TWj6UZftPc75dvbbW7CpSTqJKPK8QGi FUmOvtkpn/DRz+t9MBqCnvA++tjWqZSfwuLeI5PHRLZcodsh6+Vlmo3yqW2sybbQs/bV IOszJk2SKesQWobgejN1aqTu3/q1HWitMzhx//4YTp+r7qLtJqeF5DNNsAtiitNgkuUq AvJ7KlO/bFzRfGhhn1WkQfk9ps5bfqR3O3rPeBr5z16DVxEEMn+wyULz4+47D1ddWItz 9H9PhtYFL6fSEQ6JY09XlFmdtuZqkSwLOLNyjPKQNd12HH3OEKyEPkFj4sLcSToSuXeW xg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3c35mbh5m9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 02 Nov 2021 08:54:26 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 2 Nov 2021 08:54:25 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 2 Nov 2021 08:54:25 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 27C645B6932; Tue, 2 Nov 2021 08:54:22 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Srujana Challa Date: Tue, 2 Nov 2021 21:24:12 +0530 Message-ID: <20211102155421.486-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 MIME-Version: 1.0 X-Proofpoint-GUID: jBopS7VWNgJv9hcHxSGeHEi2o6wi6Wz0 X-Proofpoint-ORIG-GUID: jBopS7VWNgJv9hcHxSGeHEi2o6wi6Wz0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-02_08,2021-11-02_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 1/9] common/cnxk: add code to write CPT CTX through microcode op X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Srujana Challa Adds APIs to write CPT CTX through microcode op(SET_CTX/WRITE_SA). Signed-off-by: Srujana Challa --- drivers/common/cnxk/hw/cpt.h | 2 - drivers/common/cnxk/roc_cpt.c | 83 +++++++++++++++++++++++++-- drivers/common/cnxk/roc_cpt.h | 8 ++- drivers/common/cnxk/roc_ie_ot.h | 5 ++ drivers/common/cnxk/roc_nix_inl.c | 102 +++++++++++++++++++++++++++++++--- drivers/common/cnxk/roc_nix_inl.h | 4 ++ drivers/common/cnxk/roc_nix_inl_dev.c | 10 +++- drivers/common/cnxk/version.map | 5 ++ 8 files changed, 204 insertions(+), 15 deletions(-) diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h index 4d9df59..919f842 100644 --- a/drivers/common/cnxk/hw/cpt.h +++ b/drivers/common/cnxk/hw/cpt.h @@ -64,8 +64,6 @@ union cpt_lf_ctx_flush { struct { uint64_t cptr : 46; uint64_t inval : 1; - uint64_t res : 1; - uint64_t pf_func : 16; } s; }; diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index f0e52ae..49d8bf2 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -677,7 +677,7 @@ roc_cpt_dev_init(struct roc_cpt *roc_cpt) } int -roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, uint64_t cptr) +roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, void *cptr, bool inval) { union cpt_lf_ctx_flush reg; @@ -685,15 +685,32 @@ roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, uint64_t cptr) return -ENOTSUP; reg.u = 0; - reg.s.pf_func = lf->pf_func; - reg.s.inval = 1; - reg.s.cptr = cptr; + reg.s.inval = inval; + reg.s.cptr = (uintptr_t)cptr >> 7; plt_write64(reg.u, lf->rbase + CPT_LF_CTX_FLUSH); return 0; } +int +roc_cpt_lf_ctx_reload(struct roc_cpt_lf *lf, void *cptr) +{ + union cpt_lf_ctx_reload reg; + + if (lf == NULL) { + plt_err("Could not trigger CTX reload"); + return -ENOTSUP; + } + + reg.u = 0; + reg.s.cptr = (uintptr_t)cptr >> 7; + + plt_write64(reg.u, lf->rbase + CPT_LF_CTX_RELOAD); + + return 0; +} + void cpt_lf_fini(struct roc_cpt_lf *lf) { @@ -890,3 +907,61 @@ roc_cpt_lmtline_init(struct roc_cpt *roc_cpt, struct roc_cpt_lmtline *lmtline, return 0; } + +int +roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, + uint16_t sa_len) +{ + uintptr_t lmt_base = lf->lmt_base; + uint64_t lmt_arg, io_addr; + struct cpt_inst_s *inst; + union cpt_res_s *res; + uint16_t lmt_id; + uint64_t *dptr; + int i; + + ROC_LMT_CPT_BASE_ID_GET(lmt_base, lmt_id); + inst = (struct cpt_inst_s *)lmt_base; + + memset(inst, 0, sizeof(struct cpt_inst_s)); + + res = plt_zmalloc(sizeof(*res), ROC_CPT_RES_ALIGN); + if (res == NULL) { + plt_err("Couldn't allocate memory for result address"); + return -ENOMEM; + } + dptr = plt_zmalloc(sa_len, 0); + if (!dptr) { + plt_err("Couldn't allocate memory for SA dptr"); + plt_free(res); + return -ENOMEM; + } + for (i = 0; i < (sa_len / 8); i++) + dptr[i] = plt_cpu_to_be_64(((uint64_t *)sa_dptr)[i]); + + /* Fill CPT_INST_S for WRITE_SA microcode op */ + res->cn10k.compcode = CPT_COMP_NOT_DONE; + inst->res_addr = (uint64_t)res; + inst->dptr = (uint64_t)dptr; + inst->w4.s.param2 = sa_len >> 3; + inst->w4.s.dlen = sa_len; + inst->w4.s.opcode_major = ROC_IE_OT_MAJOR_OP_WRITE_SA; + inst->w4.s.opcode_minor = ROC_IE_OT_MINOR_OP_WRITE_SA; + inst->w7.s.cptr = (uint64_t)sa_cptr; + inst->w7.s.ctx_val = 1; + inst->w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE_IE; + + lmt_arg = ROC_CN10K_CPT_LMT_ARG | (uint64_t)lmt_id; + io_addr = lf->io_addr | ROC_CN10K_CPT_INST_DW_M1 << 4; + + roc_lmt_submit_steorl(lmt_arg, io_addr); + plt_wmb(); + + /* Wait until CPT instruction completes */ + while (res->cn10k.compcode == CPT_COMP_NOT_DONE) + plt_delay_ms(1); + + plt_free(res); + + return 0; +} diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index e84f168..12e6b81 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -85,6 +85,8 @@ (((ROC_CPT_CCM_ICV_LEN - 2) / 2) << 3) | (ROC_CPT_CCM_MSG_LEN - 1)) #define ROC_CPT_CCM_SALT_LEN 3 +#define ROC_CPT_RES_ALIGN 16 + enum { ROC_CPT_REVISION_ID_83XX = 0, ROC_CPT_REVISION_ID_96XX_B0 = 1, @@ -161,7 +163,9 @@ int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf); void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt); int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf); void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf); -int __roc_api roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, uint64_t cptr); +int __roc_api roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, void *cptr, + bool inval); +int __roc_api roc_cpt_lf_ctx_reload(struct roc_cpt_lf *lf, void *cptr); int __roc_api roc_cpt_inline_ipsec_cfg(struct dev *dev, uint8_t slot, struct roc_nix *nix); int __roc_api roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, @@ -174,5 +178,7 @@ int __roc_api roc_cpt_lmtline_init(struct roc_cpt *roc_cpt, struct roc_cpt_lmtline *lmtline, int lf_id); void __roc_api roc_cpt_parse_hdr_dump(const struct cpt_parse_hdr_s *cpth); +int __roc_api roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, + void *sa_cptr, uint16_t sa_len); #endif /* _ROC_CPT_H_ */ diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h index e8415cf..5b61902 100644 --- a/drivers/common/cnxk/roc_ie_ot.h +++ b/drivers/common/cnxk/roc_ie_ot.h @@ -12,6 +12,11 @@ #define ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x28UL #define ROC_IE_OT_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x29UL +#define ROC_IE_OT_MAJOR_OP_WRITE_SA 0x01UL +#define ROC_IE_OT_MINOR_OP_WRITE_SA 0x09UL + +#define ROC_IE_OT_CTX_ILEN 2 + enum roc_ie_ot_ucc_ipsec { ROC_IE_OT_UCC_SUCCESS = 0x00, ROC_IE_OT_UCC_ERR_SA_INVAL = 0xb0, diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 1d962e3..3955d9b 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -23,7 +23,8 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix) struct nix *nix = roc_nix_to_nix_priv(roc_nix); struct roc_nix_ipsec_cfg cfg; size_t inb_sa_sz; - int rc; + int rc, i; + void *sa; /* CN9K SA size is different */ if (roc_model_is_cn9k()) @@ -39,6 +40,12 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix) plt_err("Failed to allocate memory for Inbound SA"); return -ENOMEM; } + if (roc_model_is_cn10k()) { + for (i = 0; i < ipsec_in_max_spi; i++) { + sa = ((uint8_t *)nix->inb_sa_base) + (i * inb_sa_sz); + roc_nix_inl_inb_sa_init(sa); + } + } memset(&cfg, 0, sizeof(cfg)); cfg.sa_size = inb_sa_sz; @@ -271,6 +278,7 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix) void *sa_base; size_t sa_sz; int i, j, rc; + void *sa; if (idev == NULL) return -ENOTSUP; @@ -368,6 +376,12 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix) plt_err("Outbound SA base alloc failed"); goto lf_fini; } + if (roc_model_is_cn10k()) { + for (i = 0; i < roc_nix->ipsec_out_max_sa; i++) { + sa = ((uint8_t *)sa_base) + (i * sa_sz); + roc_nix_inl_outb_sa_init(sa); + } + } nix->outb_sa_base = sa_base; nix->outb_sa_sz = sa_sz; @@ -717,6 +731,8 @@ roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb, { struct nix *nix = roc_nix_to_nix_priv(roc_nix); struct roc_cpt_lf *outb_lf = nix->cpt_lf_base; + struct idev_cfg *idev = idev_get_cfg(); + struct nix_inl_dev *inl_dev = NULL; union cpt_lf_ctx_reload reload; union cpt_lf_ctx_flush flush; uintptr_t rbase; @@ -727,13 +743,15 @@ roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb, return 0; } - if (!inb && !outb_lf) - return -EINVAL; + if (inb && nix->inb_inl_dev) { + outb_lf = NULL; + if (idev) + inl_dev = idev->nix_inl_dev; + if (inl_dev) + outb_lf = &inl_dev->cpt_lf; + } - /* Performing op via outbound lf is enough - * when inline dev is not in use. - */ - if (outb_lf && !nix->inb_inl_dev) { + if (outb_lf) { rbase = outb_lf->rbase; flush.u = 0; @@ -755,11 +773,81 @@ roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb, } return 0; } + plt_err("Could not get CPT LF for SA sync"); + return -ENOTSUP; +} + +int +roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr, + bool inb, uint16_t sa_len) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct roc_cpt_lf *outb_lf = nix->cpt_lf_base; + struct idev_cfg *idev = idev_get_cfg(); + struct nix_inl_dev *inl_dev = NULL; + union cpt_lf_ctx_flush flush; + uintptr_t rbase; + int rc; + + /* Nothing much to do on cn9k */ + if (roc_model_is_cn9k()) { + plt_atomic_thread_fence(__ATOMIC_ACQ_REL); + return 0; + } + + if (inb && nix->inb_inl_dev) { + outb_lf = NULL; + if (idev) + inl_dev = idev->nix_inl_dev; + if (inl_dev && inl_dev->attach_cptlf) + outb_lf = &inl_dev->cpt_lf; + } + + if (outb_lf) { + rbase = outb_lf->rbase; + flush.u = 0; + + rc = roc_cpt_ctx_write(outb_lf, sa_dptr, sa_cptr, sa_len); + if (rc) + return rc; + /* Trigger CTX flush to write dirty data back to DRAM */ + flush.s.cptr = ((uintptr_t)sa_cptr) >> 7; + plt_write64(flush.u, rbase + CPT_LF_CTX_FLUSH); + return 0; + } + plt_nix_dbg("Could not get CPT LF for CTX write"); return -ENOTSUP; } void +roc_nix_inl_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa) +{ + size_t offset; + + memset(sa, 0, sizeof(struct roc_ot_ipsec_inb_sa)); + + offset = offsetof(struct roc_ot_ipsec_inb_sa, ctx); + sa->w0.s.hw_ctx_off = offset / ROC_CTX_UNIT_8B; + sa->w0.s.ctx_push_size = sa->w0.s.hw_ctx_off + 1; + sa->w0.s.ctx_size = ROC_IE_OT_CTX_ILEN; + sa->w0.s.aop_valid = 1; +} + +void +roc_nix_inl_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa) +{ + size_t offset; + + memset(sa, 0, sizeof(struct roc_ot_ipsec_outb_sa)); + + offset = offsetof(struct roc_ot_ipsec_outb_sa, ctx); + sa->w0.s.ctx_push_size = (offset / ROC_CTX_UNIT_8B); + sa->w0.s.ctx_size = ROC_IE_OT_CTX_ILEN; + sa->w0.s.aop_valid = 1; +} + +void roc_nix_inl_dev_lock(void) { struct idev_cfg *idev = idev_get_cfg(); diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index ae5e022..abbeac6 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -166,5 +166,9 @@ enum roc_nix_inl_sa_sync_op { int __roc_api roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb, enum roc_nix_inl_sa_sync_op op); +int __roc_api roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, + void *sa_cptr, bool inb, uint16_t sa_len); +void __roc_api roc_nix_inl_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa); +void __roc_api roc_nix_inl_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa); #endif /* _ROC_NIX_INL_H_ */ diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index 495dd19..33a59f6 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -334,7 +334,8 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev) struct nix_lf_alloc_rsp *rsp; struct nix_lf_alloc_req *req; size_t inb_sa_sz; - int rc = -ENOSPC; + int i, rc = -ENOSPC; + void *sa; /* Alloc NIX LF needed for single RQ */ req = mbox_alloc_msg_nix_lf_alloc(mbox); @@ -391,6 +392,13 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev) goto unregister_irqs; } + if (roc_model_is_cn10k()) { + for (i = 0; i < ipsec_in_max_spi; i++) { + sa = ((uint8_t *)inl_dev->inb_sa_base) + + (i * inb_sa_sz); + roc_nix_inl_inb_sa_init(sa); + } + } /* Setup device specific inb SA table */ rc = nix_inl_nix_ipsec_cfg(inl_dev, true); if (rc) { diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index bf47b33..c2333a5 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -62,12 +62,14 @@ INTERNAL { roc_cpt_iq_disable; roc_cpt_iq_enable; roc_cpt_lf_ctx_flush; + roc_cpt_lf_ctx_reload; roc_cpt_lf_init; roc_cpt_lf_fini; roc_cpt_lfs_print; roc_cpt_lmtline_init; roc_cpt_parse_hdr_dump; roc_cpt_rxc_time_cfg; + roc_cpt_ctx_write; roc_error_msg_get; roc_hash_sha1_gen; roc_hash_sha256_gen; @@ -144,6 +146,9 @@ INTERNAL { roc_nix_inl_outb_sso_pffunc_get; roc_nix_inl_outb_is_enabled; roc_nix_inl_sa_sync; + roc_nix_inl_ctx_write; + roc_nix_inl_inb_sa_init; + roc_nix_inl_outb_sa_init; roc_nix_is_lbk; roc_nix_is_pf; roc_nix_is_sdp; From patchwork Tue Nov 2 15:54:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 103512 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 361D3A0C4E; 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Tue, 02 Nov 2021 08:54:30 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 2 Nov 2021 08:54:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 2 Nov 2021 08:54:29 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id AEF195B6932; Tue, 2 Nov 2021 08:54:26 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Srujana Challa Date: Tue, 2 Nov 2021 21:24:13 +0530 Message-ID: <20211102155421.486-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20211102155421.486-1-ndabilpuram@marvell.com> References: <20211102155421.486-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: MyWAY8Qb_-CvU-ieXCUWosEiWyi7KGra X-Proofpoint-ORIG-GUID: MyWAY8Qb_-CvU-ieXCUWosEiWyi7KGra X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-02_08,2021-11-02_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 2/9] common/cnxk: add CPT CTX sync mailbox API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Srujana Challa Add CPT CTX sync mailbox API and flush IPsec inbound entries at application exit. Signed-off-by: Srujana Challa --- drivers/common/cnxk/roc_mbox.h | 1 + drivers/common/cnxk/roc_nix.c | 14 ++++++++++++++ drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_inl.c | 3 +++ drivers/common/cnxk/roc_nix_inl_dev.c | 16 ++++++++++++++++ drivers/common/cnxk/version.map | 1 + 6 files changed, 36 insertions(+) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 22f6ebc..5dcb445 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -143,6 +143,7 @@ struct mbox_msghdr { M(CPT_STATS, 0xA05, cpt_sts_get, cpt_sts_req, cpt_sts_rsp) \ M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ msg_rsp) \ + M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \ cpt_rx_inline_lf_cfg_msg, msg_rsp) \ M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg) \ diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index 64156ce..949be80 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -109,6 +109,20 @@ roc_nix_lf_inl_ipsec_cfg(struct roc_nix *roc_nix, struct roc_nix_ipsec_cfg *cfg, } int +roc_nix_cpt_ctx_cache_sync(struct roc_nix *roc_nix) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct mbox *mbox = (&nix->dev)->mbox; + struct msg_req *req; + + req = mbox_alloc_msg_cpt_ctx_cache_sync(mbox); + if (req == NULL) + return -ENOSPC; + + return mbox_process(mbox); +} + +int roc_nix_max_pkt_len(struct roc_nix *roc_nix) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 343bb2f..d83a9b5 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -437,6 +437,7 @@ int __roc_api roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, int __roc_api roc_nix_lf_free(struct roc_nix *roc_nix); int __roc_api roc_nix_lf_inl_ipsec_cfg(struct roc_nix *roc_nix, struct roc_nix_ipsec_cfg *cfg, bool enb); +int __roc_api roc_nix_cpt_ctx_cache_sync(struct roc_nix *roc_nix); /* Debug */ int __roc_api roc_nix_lf_get_reg_count(struct roc_nix *roc_nix); diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 3955d9b..f0fc690 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -258,6 +258,9 @@ roc_nix_inl_inb_fini(struct roc_nix *roc_nix) nix->inl_inb_ena = false; + /* Flush Inbound CTX cache entries */ + roc_nix_cpt_ctx_cache_sync(roc_nix); + /* Disable Inbound SA */ return nix_inl_sa_tbl_release(roc_nix); } diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index 33a59f6..a0fe6ec 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -97,6 +97,19 @@ nix_inl_selftest(void) } static int +nix_inl_cpt_ctx_cache_sync(struct nix_inl_dev *inl_dev) +{ + struct mbox *mbox = (&inl_dev->dev)->mbox; + struct msg_req *req; + + req = mbox_alloc_msg_cpt_ctx_cache_sync(mbox); + if (req == NULL) + return -ENOSPC; + + return mbox_process(mbox); +} + +static int nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena) { struct nix_inline_ipsec_lf_cfg *lf_cfg; @@ -628,6 +641,9 @@ roc_nix_inl_dev_fini(struct roc_nix_inl_dev *roc_inl_dev) inl_dev = idev->nix_inl_dev; pci_dev = inl_dev->pci_dev; + /* Flush Inbound CTX cache entries */ + nix_inl_cpt_ctx_cache_sync(inl_dev); + /* Release SSO */ rc = nix_inl_sso_release(inl_dev); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index c2333a5..a90e5fc 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -149,6 +149,7 @@ INTERNAL { roc_nix_inl_ctx_write; roc_nix_inl_inb_sa_init; roc_nix_inl_outb_sa_init; + roc_nix_cpt_ctx_cache_sync; roc_nix_is_lbk; roc_nix_is_pf; roc_nix_is_sdp; From patchwork Tue Nov 2 15:54:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 103513 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A5D72A0C4E; Tue, 2 Nov 2021 16:54:45 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 63EE7411ED; Tue, 2 Nov 2021 16:54:35 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 70015411CB for ; Tue, 2 Nov 2021 16:54:34 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1A2CjgHS030466 for ; Tue, 2 Nov 2021 08:54:33 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=8PZbupBtoRf8HZhIBQJcFzXi9dmbWMcdfjbZguFy5YE=; b=EqjXj3TNObN8W6DMdYvhj0wtpquKjW1ta1hzqHIH32OIQXYPpcaqgf0hVT4xMP3X2Ojb u+XcJuaWuZjt+TF/SYeL6xfbfgu1ngt27CQ4vJFleWzmH3rIaIq0xEG/ggk0fssDTMcD Gck8052dHsXks9GcZqEmvuyAmLlDhTE160t4IfPUcAsgnHJ0juE+RFvG83r+4E1rr/1E j5+9VMBqPwySUh6LH+AHYXQxl9TgKNxVPgb+t/quygrEFu+ocomrS1WkEArmLZjbR9Qs Sknc1iiHZlGMgvoi8NTTNn85vBERkNIOE2CNN8y4tXVPcXdF8jtKb+2hlJg5ZWdEP3rk bA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3c35mbh5n1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 02 Nov 2021 08:54:33 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 2 Nov 2021 08:54:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 2 Nov 2021 08:54:31 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 39A3B5B6952; Tue, 2 Nov 2021 08:54:29 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Date: Tue, 2 Nov 2021 21:24:14 +0530 Message-ID: <20211102155421.486-3-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20211102155421.486-1-ndabilpuram@marvell.com> References: <20211102155421.486-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: kwz2FBIJ5faJgASkREvXS0D8IFehbVdu X-Proofpoint-ORIG-GUID: kwz2FBIJ5faJgASkREvXS0D8IFehbVdu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-02_08,2021-11-02_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 3/9] common/cnxk: support flow control on LBK X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Support flow control enable/disable on LBK VF's as HW supports backpressure on LBK links. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_nix.c | 6 ++++++ drivers/common/cnxk/roc_nix_fc.c | 27 ++++++++++++++++++++------- 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index 949be80..fbfc550 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -414,6 +414,12 @@ roc_nix_dev_init(struct roc_nix *roc_nix) nix->reta_sz = reta_sz; nix->mtu = ROC_NIX_DEFAULT_HW_FRS; + /* Always start with full FC for LBK */ + if (nix->lbk_link) { + nix->rx_pause = 1; + nix->tx_pause = 1; + } + /* Register error and ras interrupts */ rc = nix_register_irqs(nix); if (rc) diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index 7eac7d0..ef46842 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -157,7 +157,7 @@ nix_fc_cq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) int roc_nix_fc_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) { - if (roc_nix_is_vf_or_sdp(roc_nix)) + if (roc_nix_is_vf_or_sdp(roc_nix) && !roc_nix_is_lbk(roc_nix)) return 0; if (fc_cfg->cq_cfg_valid) @@ -169,7 +169,7 @@ roc_nix_fc_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) int roc_nix_fc_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) { - if (roc_nix_is_vf_or_sdp(roc_nix)) + if (roc_nix_is_vf_or_sdp(roc_nix) && !roc_nix_is_lbk(roc_nix)) return 0; if (fc_cfg->cq_cfg_valid) @@ -188,8 +188,17 @@ roc_nix_fc_mode_get(struct roc_nix *roc_nix) enum roc_nix_fc_mode mode; int rc = -ENOSPC; - if (roc_nix_is_lbk(roc_nix)) - return ROC_NIX_FC_NONE; + /* Flow control on LBK link is always available */ + if (roc_nix_is_lbk(roc_nix)) { + if (nix->tx_pause && nix->rx_pause) + return ROC_NIX_FC_FULL; + else if (nix->rx_pause) + return ROC_NIX_FC_RX; + else if (nix->tx_pause) + return ROC_NIX_FC_TX; + else + return ROC_NIX_FC_NONE; + } req = mbox_alloc_msg_cgx_cfg_pause_frm(mbox); if (req == NULL) @@ -226,12 +235,16 @@ roc_nix_fc_mode_set(struct roc_nix *roc_nix, enum roc_nix_fc_mode mode) uint8_t tx_pause, rx_pause; int rc = -ENOSPC; - if (roc_nix_is_lbk(roc_nix)) - return NIX_ERR_OP_NOTSUP; - rx_pause = (mode == ROC_NIX_FC_FULL) || (mode == ROC_NIX_FC_RX); tx_pause = (mode == ROC_NIX_FC_FULL) || (mode == ROC_NIX_FC_TX); + /* Nothing much to do for LBK links */ + if (roc_nix_is_lbk(roc_nix)) { + nix->rx_pause = rx_pause; + nix->tx_pause = tx_pause; + return 0; + } + req = mbox_alloc_msg_cgx_cfg_pause_frm(mbox); if (req == NULL) return rc; From patchwork Tue Nov 2 15:54:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 103514 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EB713A0C4E; Tue, 2 Nov 2021 16:54:52 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6C4454113F; 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Tue, 02 Nov 2021 08:54:37 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 2 Nov 2021 08:54:35 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 2 Nov 2021 08:54:34 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 592175B6946; Tue, 2 Nov 2021 08:54:33 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Date: Tue, 2 Nov 2021 21:24:15 +0530 Message-ID: <20211102155421.486-4-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20211102155421.486-1-ndabilpuram@marvell.com> References: <20211102155421.486-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 1ppNWKBcPyXFgXZmB-xjXqJTXpHd_ExE X-Proofpoint-ORIG-GUID: 1ppNWKBcPyXFgXZmB-xjXqJTXpHd_ExE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-02_08,2021-11-02_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 4/9] common/cnxk: enable tm to listen on Rx pause frames X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Enable tm topology to listen on backpressure received when Rx pause frame is enabled. Only one TM node in Tl3/TL2 per channel can listen on backpressure on that channel. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_nix.c | 3 + drivers/common/cnxk/roc_nix.h | 9 +- drivers/common/cnxk/roc_nix_fc.c | 20 +++-- drivers/common/cnxk/roc_nix_priv.h | 3 + drivers/common/cnxk/roc_nix_tm.c | 157 +++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_nix_tm_ops.c | 9 ++ drivers/common/cnxk/roc_nix_tm_utils.c | 8 ++ drivers/net/cnxk/cnxk_ethdev.c | 2 +- drivers/net/cnxk/cnxk_ethdev_ops.c | 2 +- 9 files changed, 204 insertions(+), 9 deletions(-) diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index fbfc550..c96b266 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -418,6 +418,9 @@ roc_nix_dev_init(struct roc_nix *roc_nix) if (nix->lbk_link) { nix->rx_pause = 1; nix->tx_pause = 1; + } else if (!roc_nix_is_vf_or_sdp(roc_nix)) { + /* Get the current state of flow control */ + roc_nix_fc_mode_get(roc_nix); } /* Register error and ras interrupts */ diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index d83a9b5..8f36ce7 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -153,7 +153,10 @@ struct roc_nix_vlan_config { }; struct roc_nix_fc_cfg { - bool cq_cfg_valid; +#define ROC_NIX_FC_RXCHAN_CFG 0 +#define ROC_NIX_FC_CQ_CFG 1 +#define ROC_NIX_FC_TM_CFG 2 + uint8_t type; union { struct { bool enable; @@ -164,6 +167,10 @@ struct roc_nix_fc_cfg { uint16_t cq_drop; bool enable; } cq_cfg; + + struct { + bool enable; + } tm_cfg; }; }; diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index ef46842..6453258 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -24,7 +24,7 @@ nix_fc_rxchan_bpid_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) else fc_cfg->rxchan_cfg.enable = false; - fc_cfg->cq_cfg_valid = false; + fc_cfg->type = ROC_NIX_FC_RXCHAN_CFG; return 0; } @@ -103,7 +103,7 @@ nix_fc_cq_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) fc_cfg->cq_cfg.cq_drop = rsp->cq.bp; fc_cfg->cq_cfg.enable = rsp->cq.bp_ena; - fc_cfg->cq_cfg_valid = true; + fc_cfg->type = ROC_NIX_FC_CQ_CFG; exit: return rc; @@ -160,10 +160,14 @@ roc_nix_fc_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) if (roc_nix_is_vf_or_sdp(roc_nix) && !roc_nix_is_lbk(roc_nix)) return 0; - if (fc_cfg->cq_cfg_valid) + if (fc_cfg->type == ROC_NIX_FC_CQ_CFG) return nix_fc_cq_config_get(roc_nix, fc_cfg); - else + else if (fc_cfg->type == ROC_NIX_FC_RXCHAN_CFG) return nix_fc_rxchan_bpid_get(roc_nix, fc_cfg); + else if (fc_cfg->type == ROC_NIX_FC_TM_CFG) + return nix_tm_bp_config_get(roc_nix, &fc_cfg->tm_cfg.enable); + + return -EINVAL; } int @@ -172,11 +176,15 @@ roc_nix_fc_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) if (roc_nix_is_vf_or_sdp(roc_nix) && !roc_nix_is_lbk(roc_nix)) return 0; - if (fc_cfg->cq_cfg_valid) + if (fc_cfg->type == ROC_NIX_FC_CQ_CFG) return nix_fc_cq_config_set(roc_nix, fc_cfg); - else + else if (fc_cfg->type == ROC_NIX_FC_RXCHAN_CFG) return nix_fc_rxchan_bpid_set(roc_nix, fc_cfg->rxchan_cfg.enable); + else if (fc_cfg->type == ROC_NIX_FC_TM_CFG) + return nix_tm_bp_config_set(roc_nix, fc_cfg->tm_cfg.enable); + + return -EINVAL; } enum roc_nix_fc_mode diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 9805d4a..60a00a3 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -74,6 +74,7 @@ struct nix_tm_node { uint32_t red_algo : 2; uint32_t pkt_mode : 1; uint32_t pkt_mode_set : 1; + uint32_t bp_capa : 1; bool child_realloc; struct nix_tm_node *parent; @@ -373,6 +374,8 @@ int nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, int nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg, bool ena); int nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable); +int nix_tm_bp_config_get(struct roc_nix *roc_nix, bool *is_enabled); +int nix_tm_bp_config_set(struct roc_nix *roc_nix, bool enable); /* * TM priv utils. diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c index 08d6e86..b3d8ebd 100644 --- a/drivers/common/cnxk/roc_nix_tm.c +++ b/drivers/common/cnxk/roc_nix_tm.c @@ -98,16 +98,32 @@ int nix_tm_txsch_reg_config(struct nix *nix, enum roc_nix_tm_tree tree) { struct nix_tm_node_list *list; + bool is_pf_or_lbk = false; struct nix_tm_node *node; + bool skip_bp = false; uint32_t hw_lvl; int rc = 0; list = nix_tm_node_list(nix, tree); + if ((!dev_is_vf(&nix->dev) || nix->lbk_link) && !nix->sdp_link) + is_pf_or_lbk = true; + for (hw_lvl = 0; hw_lvl <= nix->tm_root_lvl; hw_lvl++) { TAILQ_FOREACH(node, list, node) { if (node->hw_lvl != hw_lvl) continue; + + /* Only one TL3/TL2 Link config should have BP enable + * set per channel only for PF or lbk vf. + */ + node->bp_capa = 0; + if (is_pf_or_lbk && !skip_bp && + node->hw_lvl == nix->tm_link_cfg_lvl) { + node->bp_capa = 1; + skip_bp = true; + } + rc = nix_tm_node_reg_conf(nix, node); if (rc) goto exit; @@ -301,6 +317,130 @@ nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node) } int +nix_tm_bp_config_set(struct roc_nix *roc_nix, bool enable) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + enum roc_nix_tm_tree tree = nix->tm_tree; + struct mbox *mbox = (&nix->dev)->mbox; + struct nix_txschq_config *req = NULL; + struct nix_tm_node_list *list; + struct nix_tm_node *node; + uint8_t k = 0; + uint16_t link; + int rc = 0; + + list = nix_tm_node_list(nix, tree); + link = nix->tx_link; + + TAILQ_FOREACH(node, list, node) { + if (node->hw_lvl != nix->tm_link_cfg_lvl) + continue; + + if (!(node->flags & NIX_TM_NODE_HWRES) || !node->bp_capa) + continue; + + if (!req) { + req = mbox_alloc_msg_nix_txschq_cfg(mbox); + req->lvl = nix->tm_link_cfg_lvl; + k = 0; + } + + req->reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(node->hw_id, link); + req->regval[k] = enable ? BIT_ULL(13) : 0; + req->regval_mask[k] = ~BIT_ULL(13); + k++; + + if (k >= MAX_REGS_PER_MBOX_MSG) { + req->num_regs = k; + rc = mbox_process(mbox); + if (rc) + goto err; + req = NULL; + } + } + + if (req) { + req->num_regs = k; + rc = mbox_process(mbox); + if (rc) + goto err; + } + + return 0; +err: + plt_err("Failed to %s bp on link %u, rc=%d(%s)", + enable ? "enable" : "disable", link, rc, roc_error_msg_get(rc)); + return rc; +} + +int +nix_tm_bp_config_get(struct roc_nix *roc_nix, bool *is_enabled) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct nix_txschq_config *req = NULL, *rsp; + enum roc_nix_tm_tree tree = nix->tm_tree; + struct mbox *mbox = (&nix->dev)->mbox; + struct nix_tm_node_list *list; + struct nix_tm_node *node; + bool found = false; + uint8_t enable = 1; + uint8_t k = 0, i; + uint16_t link; + int rc = 0; + + list = nix_tm_node_list(nix, tree); + link = nix->tx_link; + + TAILQ_FOREACH(node, list, node) { + if (node->hw_lvl != nix->tm_link_cfg_lvl) + continue; + + if (!(node->flags & NIX_TM_NODE_HWRES) || !node->bp_capa) + continue; + + found = true; + if (!req) { + req = mbox_alloc_msg_nix_txschq_cfg(mbox); + req->read = 1; + req->lvl = nix->tm_link_cfg_lvl; + k = 0; + } + + req->reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(node->hw_id, link); + k++; + + if (k >= MAX_REGS_PER_MBOX_MSG) { + req->num_regs = k; + rc = mbox_process_msg(mbox, (void **)&rsp); + if (rc || rsp->num_regs != k) + goto err; + req = NULL; + + /* Report it as enabled only if enabled or all */ + for (i = 0; i < k; i++) + enable &= !!(rsp->regval[i] & BIT_ULL(13)); + } + } + + if (req) { + req->num_regs = k; + rc = mbox_process(mbox); + if (rc) + goto err; + /* Report it as enabled only if enabled or all */ + for (i = 0; i < k; i++) + enable &= !!(rsp->regval[i] & BIT_ULL(13)); + } + + *is_enabled = found ? !!enable : false; + return 0; +err: + plt_err("Failed to get bp status on link %u, rc=%d(%s)", link, rc, + roc_error_msg_get(rc)); + return rc; +} + +int nix_tm_smq_xoff(struct nix *nix, struct nix_tm_node *node, bool enable) { struct mbox *mbox = (&nix->dev)->mbox; @@ -461,6 +601,13 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq) } } + /* Disable backpressure */ + rc = nix_tm_bp_config_set(roc_nix, false); + if (rc) { + plt_err("Failed to disable backpressure for flush, rc=%d", rc); + return rc; + } + /* Disable smq xoff for case it was enabled earlier */ rc = nix_tm_smq_xoff(nix, node->parent, false); if (rc) { @@ -580,6 +727,16 @@ nix_tm_sq_flush_post(struct roc_nix_sq *sq) } } + if (!nix->rx_pause) + return 0; + + /* Restore backpressure */ + rc = nix_tm_bp_config_set(roc_nix, true); + if (rc) { + plt_err("Failed to restore backpressure, rc=%d", rc); + return rc; + } + return 0; } diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c index eee80d5..6a417c0 100644 --- a/drivers/common/cnxk/roc_nix_tm_ops.c +++ b/drivers/common/cnxk/roc_nix_tm_ops.c @@ -452,6 +452,15 @@ roc_nix_tm_hierarchy_disable(struct roc_nix *roc_nix) } } + /* Disable backpressure, it will be enabled back if needed on + * hierarchy enable + */ + rc = nix_tm_bp_config_set(roc_nix, false); + if (rc) { + plt_err("Failed to disable backpressure for flush, rc=%d", rc); + goto cleanup; + } + /* Flush all tx queues */ for (i = 0; i < sq_cnt; i++) { sq = nix->sqs[i]; diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index a135454..543adf9 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -522,6 +522,10 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node, nix->tm_link_cfg_lvl == NIX_TXSCH_LVL_TL3) { reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link); regval[k] = BIT_ULL(12) | relchan; + /* Enable BP if node is BP capable and rx_pause is set + */ + if (nix->rx_pause && node->bp_capa) + regval[k] |= BIT_ULL(13); k++; } @@ -541,6 +545,10 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node, nix->tm_link_cfg_lvl == NIX_TXSCH_LVL_TL2) { reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link); regval[k] = BIT_ULL(12) | relchan; + /* Enable BP if node is BP capable and rx_pause is set + */ + if (nix->rx_pause && node->bp_capa) + regval[k] |= BIT_ULL(13); k++; } diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index db54468..e9bebfe 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1199,7 +1199,7 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) } /* Init flow control configuration */ - fc_cfg.cq_cfg_valid = false; + fc_cfg.type = ROC_NIX_FC_RXCHAN_CFG; fc_cfg.rxchan_cfg.enable = true; rc = roc_nix_fc_config_set(nix, &fc_cfg); if (rc) { diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c index 6746430..baa474f 100644 --- a/drivers/net/cnxk/cnxk_ethdev_ops.c +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -227,7 +227,7 @@ nix_fc_cq_config_set(struct cnxk_eth_dev *dev, uint16_t qid, bool enable) memset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg)); cq = &dev->cqs[qid]; - fc_cfg.cq_cfg_valid = true; + fc_cfg.type = ROC_NIX_FC_CQ_CFG; fc_cfg.cq_cfg.enable = enable; fc_cfg.cq_cfg.rq = qid; fc_cfg.cq_cfg.cq_drop = cq->drop_thresh; From patchwork Tue Nov 2 15:54:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 103515 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3F49AA0C4E; Tue, 2 Nov 2021 16:55:04 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C402F41C3B; Tue, 2 Nov 2021 16:54:42 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B41F741C3B for ; Tue, 2 Nov 2021 16:54:40 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1A2Cjkq9030570 for ; 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Tue, 2 Nov 2021 08:54:38 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 68E5F5B6932; Tue, 2 Nov 2021 08:54:36 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Date: Tue, 2 Nov 2021 21:24:16 +0530 Message-ID: <20211102155421.486-5-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20211102155421.486-1-ndabilpuram@marvell.com> References: <20211102155421.486-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: uTdxxGF46WBs38r9zQP8fQtYArru7zLc X-Proofpoint-ORIG-GUID: uTdxxGF46WBs38r9zQP8fQtYArru7zLc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-02_08,2021-11-02_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 5/9] common/cnxk: enable bp on CPT with inline inbound X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Enable backpressure on CPT with inline inbound enabled. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_mbox.h | 4 ++++ drivers/common/cnxk/roc_nix_fc.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 5dcb445..bf5495d 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -239,6 +239,10 @@ struct mbox_msghdr { M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, \ nix_bandprof_alloc_req, nix_bandprof_alloc_rsp) \ M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ + msg_rsp) \ + M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req, \ + nix_bp_cfg_rsp) \ + M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \ msg_rsp) /* Messages initiated by AF (range 0xC00 - 0xDFF) */ diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index 6453258..ca29cd2 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -70,6 +70,34 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable) nix->chan_cnt = 0; } + if (roc_model_is_cn9k()) + goto exit; + + /* Enable backpressure on CPT if inline inb is enabled */ + if (enable && roc_nix_inl_inb_is_enabled(roc_nix)) { + req = mbox_alloc_msg_nix_cpt_bp_enable(mbox); + if (req == NULL) + return rc; + req->chan_base = 0; + req->chan_cnt = 1; + req->bpid_per_chan = 0; + + rc = mbox_process_msg(mbox, (void *)&rsp); + if (rc) + goto exit; + } else { + req = mbox_alloc_msg_nix_cpt_bp_disable(mbox); + if (req == NULL) + return rc; + req->chan_base = 0; + req->chan_cnt = 1; + req->bpid_per_chan = 0; + + rc = mbox_process_msg(mbox, (void *)&rsp); + if (rc) + goto exit; + } + exit: return rc; } From patchwork Tue Nov 2 15:54:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 103516 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 12985A0C4E; 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Tue, 02 Nov 2021 08:54:43 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 2 Nov 2021 08:54:41 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 2 Nov 2021 08:54:41 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id CC4E55B6932; Tue, 2 Nov 2021 08:54:39 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Tue, 2 Nov 2021 21:24:17 +0530 Message-ID: <20211102155421.486-6-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20211102155421.486-1-ndabilpuram@marvell.com> References: <20211102155421.486-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: qMLgPldH8dd2hwq9kQBZ9NlEMQ6MHaF3 X-Proofpoint-ORIG-GUID: qMLgPldH8dd2hwq9kQBZ9NlEMQ6MHaF3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-02_08,2021-11-02_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 6/9] common/cnxk: support changing drop re flag after lf alloc X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add API to toggle drop_re flag after nix_lf_alloc() so that it can be used to toggle it runtime. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_mbox.h | 1 + drivers/common/cnxk/roc_nix.c | 1 + drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_ops.c | 39 ++++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_nix_priv.h | 1 + drivers/common/cnxk/version.map | 1 + 6 files changed, 44 insertions(+) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index bf5495d..a7e7776 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -1075,6 +1075,7 @@ struct nix_rx_cfg { struct mbox_msghdr hdr; #define NIX_RX_OL3_VERIFY BIT(0) #define NIX_RX_OL4_VERIFY BIT(1) +#define NIX_RX_DROP_RE BIT(2) uint8_t __io len_verify; /* Outer L3/L4 len check */ #define NIX_RX_CSUM_OL4_VERIFY BIT(0) uint8_t __io csum_verify; /* Outer L4 checksum verification */ diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index c96b266..151d8c3 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -173,6 +173,7 @@ roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, uint32_t nb_txq, if (rc) goto fail; + nix->rx_cfg = rx_cfg; nix->sqb_size = rsp->sqb_size; nix->tx_chan_base = rsp->tx_chan_base; nix->rx_chan_base = rsp->rx_chan_base; diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 8f36ce7..82d74de 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -445,6 +445,7 @@ int __roc_api roc_nix_lf_free(struct roc_nix *roc_nix); int __roc_api roc_nix_lf_inl_ipsec_cfg(struct roc_nix *roc_nix, struct roc_nix_ipsec_cfg *cfg, bool enb); int __roc_api roc_nix_cpt_ctx_cache_sync(struct roc_nix *roc_nix); +int __roc_api roc_nix_rx_drop_re_set(struct roc_nix *roc_nix, bool ena); /* Debug */ int __roc_api roc_nix_lf_get_reg_count(struct roc_nix *roc_nix); diff --git a/drivers/common/cnxk/roc_nix_ops.c b/drivers/common/cnxk/roc_nix_ops.c index 0e28302..04a78cf 100644 --- a/drivers/common/cnxk/roc_nix_ops.c +++ b/drivers/common/cnxk/roc_nix_ops.c @@ -450,3 +450,42 @@ roc_nix_eeprom_info_get(struct roc_nix *roc_nix, mbox_memcpy(info->buf, rsp->fwdata.sfp_eeprom.buf, SFP_EEPROM_SIZE); return 0; } + +int +roc_nix_rx_drop_re_set(struct roc_nix *roc_nix, bool ena) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct mbox *mbox = get_mbox(roc_nix); + struct nix_rx_cfg *req; + int rc = -EIO; + + /* No-op if no change */ + if (ena == !!(nix->rx_cfg & ROC_NIX_LF_RX_CFG_DROP_RE)) + return 0; + + req = mbox_alloc_msg_nix_set_rx_cfg(mbox); + if (req == NULL) + return rc; + + if (ena) + req->len_verify |= NIX_RX_DROP_RE; + /* Keep other flags intact */ + if (nix->rx_cfg & ROC_NIX_LF_RX_CFG_LEN_OL3) + req->len_verify |= NIX_RX_OL3_VERIFY; + + if (nix->rx_cfg & ROC_NIX_LF_RX_CFG_LEN_OL4) + req->len_verify |= NIX_RX_OL4_VERIFY; + + if (nix->rx_cfg & ROC_NIX_LF_RX_CFG_CSUM_OL4) + req->csum_verify |= NIX_RX_CSUM_OL4_VERIFY; + + rc = mbox_process(mbox); + if (rc) + return rc; + + if (ena) + nix->rx_cfg |= ROC_NIX_LF_RX_CFG_DROP_RE; + else + nix->rx_cfg &= ~ROC_NIX_LF_RX_CFG_DROP_RE; + return 0; +} diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 60a00a3..04575af 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -139,6 +139,7 @@ struct nix { uint16_t msixoff; uint8_t rx_pause; uint8_t tx_pause; + uint64_t rx_cfg; struct dev dev; uint16_t cints; uint16_t qints; diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index a90e5fc..a139f0d 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -211,6 +211,7 @@ INTERNAL { roc_nix_rss_key_set; roc_nix_rss_reta_get; roc_nix_rss_reta_set; + roc_nix_rx_drop_re_set; roc_nix_rx_queue_intr_disable; roc_nix_rx_queue_intr_enable; roc_nix_sq_dump; From patchwork Tue Nov 2 15:54:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 103517 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 38ACDA0C4E; Tue, 2 Nov 2021 16:55:21 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 10B3B426D4; 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Tue, 02 Nov 2021 08:54:47 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 2 Nov 2021 08:54:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 2 Nov 2021 08:54:45 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 3EA995B6932; Tue, 2 Nov 2021 08:54:43 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Srujana Challa Date: Tue, 2 Nov 2021 21:24:18 +0530 Message-ID: <20211102155421.486-7-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20211102155421.486-1-ndabilpuram@marvell.com> References: <20211102155421.486-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 8XSPWq_rexm3Wg_g2x5V8rjMV5Yb-6d5 X-Proofpoint-ORIG-GUID: 8XSPWq_rexm3Wg_g2x5V8rjMV5Yb-6d5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-02_08,2021-11-02_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 7/9] net/cnxk: write CPT CTX through microcode op X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Srujana Challa Adds support to write CPT CTX through microcode op(SET_CTX/WRITE_SA) for cn10k inline mode. Signed-off-by: Srujana Challa --- drivers/net/cnxk/cn10k_ethdev_sec.c | 59 +++++++++++++++++++++---------------- drivers/net/cnxk/cnxk_ethdev.c | 49 +++++++++++++++++++++++++----- drivers/net/cnxk/cnxk_ethdev.h | 6 ++++ drivers/net/cnxk/cnxk_ethdev_sec.c | 1 + 4 files changed, 83 insertions(+), 32 deletions(-) diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 82dc636..235c168 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -277,8 +277,8 @@ cn10k_eth_sec_session_create(void *device, roc_nix_inl_dev_lock(); if (inbound) { + struct roc_ot_ipsec_inb_sa *inb_sa, *inb_sa_dptr; struct cn10k_inb_priv_data *inb_priv; - struct roc_ot_ipsec_inb_sa *inb_sa; uintptr_t sa; PLT_STATIC_ASSERT(sizeof(struct cn10k_inb_priv_data) < @@ -307,10 +307,11 @@ cn10k_eth_sec_session_create(void *device, goto mempool_put; } - memset(inb_sa, 0, sizeof(struct roc_ot_ipsec_inb_sa)); + inb_sa_dptr = (struct roc_ot_ipsec_inb_sa *)dev->inb.sa_dptr; + memset(inb_sa_dptr, 0, sizeof(struct roc_ot_ipsec_inb_sa)); /* Fill inbound sa params */ - rc = cnxk_ot_ipsec_inb_sa_fill(inb_sa, ipsec, crypto); + rc = cnxk_ot_ipsec_inb_sa_fill(inb_sa_dptr, ipsec, crypto); if (rc) { plt_err("Failed to init inbound sa, rc=%d", rc); goto mempool_put; @@ -323,7 +324,7 @@ cn10k_eth_sec_session_create(void *device, inb_priv->userdata = conf->userdata; /* Save SA index/SPI in cookie for now */ - inb_sa->w1.s.cookie = rte_cpu_to_be_32(ipsec->spi); + inb_sa_dptr->w1.s.cookie = rte_cpu_to_be_32(ipsec->spi); /* Prepare session priv */ sess_priv.inb_sa = 1; @@ -339,9 +340,15 @@ cn10k_eth_sec_session_create(void *device, TAILQ_INSERT_TAIL(&dev->inb.list, eth_sec, entry); dev->inb.nb_sess++; + /* Sync session in context cache */ + rc = roc_nix_inl_ctx_write(&dev->nix, inb_sa_dptr, eth_sec->sa, + eth_sec->inb, + sizeof(struct roc_ot_ipsec_inb_sa)); + if (rc) + goto mempool_put; } else { + struct roc_ot_ipsec_outb_sa *outb_sa, *outb_sa_dptr; struct cn10k_outb_priv_data *outb_priv; - struct roc_ot_ipsec_outb_sa *outb_sa; struct cnxk_ipsec_outb_rlens *rlens; uint64_t sa_base = dev->outb.sa_base; uint32_t sa_idx; @@ -358,10 +365,11 @@ cn10k_eth_sec_session_create(void *device, outb_priv = roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(outb_sa); rlens = &outb_priv->rlens; - memset(outb_sa, 0, sizeof(struct roc_ot_ipsec_outb_sa)); + outb_sa_dptr = (struct roc_ot_ipsec_outb_sa *)dev->outb.sa_dptr; + memset(outb_sa_dptr, 0, sizeof(struct roc_ot_ipsec_outb_sa)); /* Fill outbound sa params */ - rc = cnxk_ot_ipsec_outb_sa_fill(outb_sa, ipsec, crypto); + rc = cnxk_ot_ipsec_outb_sa_fill(outb_sa_dptr, ipsec, crypto); if (rc) { plt_err("Failed to init outbound sa, rc=%d", rc); rc |= cnxk_eth_outb_sa_idx_put(dev, sa_idx); @@ -381,8 +389,8 @@ cn10k_eth_sec_session_create(void *device, sess_priv.roundup_byte = rlens->roundup_byte; sess_priv.roundup_len = rlens->roundup_len; sess_priv.partial_len = rlens->partial_len; - sess_priv.mode = outb_sa->w2.s.ipsec_mode; - sess_priv.outer_ip_ver = outb_sa->w2.s.outer_ip_ver; + sess_priv.mode = outb_sa_dptr->w2.s.ipsec_mode; + sess_priv.outer_ip_ver = outb_sa_dptr->w2.s.outer_ip_ver; /* Pointer from eth_sec -> outb_sa */ eth_sec->sa = outb_sa; @@ -392,12 +400,13 @@ cn10k_eth_sec_session_create(void *device, TAILQ_INSERT_TAIL(&dev->outb.list, eth_sec, entry); dev->outb.nb_sess++; + /* Sync session in context cache */ + rc = roc_nix_inl_ctx_write(&dev->nix, outb_sa_dptr, eth_sec->sa, + eth_sec->inb, + sizeof(struct roc_ot_ipsec_outb_sa)); + if (rc) + goto mempool_put; } - - /* Sync session in context cache */ - roc_nix_inl_sa_sync(&dev->nix, eth_sec->sa, eth_sec->inb, - ROC_NIX_INL_SA_OP_RELOAD); - if (inbound && inl_dev) roc_nix_inl_dev_unlock(); @@ -422,10 +431,9 @@ cn10k_eth_sec_session_destroy(void *device, struct rte_security_session *sess) { struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device; struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); - struct roc_ot_ipsec_inb_sa *inb_sa; - struct roc_ot_ipsec_outb_sa *outb_sa; struct cnxk_eth_sec_sess *eth_sec; struct rte_mempool *mp; + void *sa_dptr; eth_sec = cnxk_eth_sec_sess_get_by_sess(dev, sess); if (!eth_sec) @@ -435,27 +443,28 @@ cn10k_eth_sec_session_destroy(void *device, struct rte_security_session *sess) roc_nix_inl_dev_lock(); if (eth_sec->inb) { - inb_sa = eth_sec->sa; /* Disable SA */ - inb_sa->w2.s.valid = 0; + sa_dptr = dev->inb.sa_dptr; + roc_nix_inl_inb_sa_init(sa_dptr); + roc_nix_inl_ctx_write(&dev->nix, sa_dptr, eth_sec->sa, + eth_sec->inb, + sizeof(struct roc_ot_ipsec_inb_sa)); TAILQ_REMOVE(&dev->inb.list, eth_sec, entry); dev->inb.nb_sess--; } else { - outb_sa = eth_sec->sa; /* Disable SA */ - outb_sa->w2.s.valid = 0; + sa_dptr = dev->outb.sa_dptr; + roc_nix_inl_outb_sa_init(sa_dptr); + roc_nix_inl_ctx_write(&dev->nix, sa_dptr, eth_sec->sa, + eth_sec->inb, + sizeof(struct roc_ot_ipsec_outb_sa)); /* Release Outbound SA index */ cnxk_eth_outb_sa_idx_put(dev, eth_sec->sa_idx); TAILQ_REMOVE(&dev->outb.list, eth_sec, entry); dev->outb.nb_sess--; } - - /* Sync session in context cache */ - roc_nix_inl_sa_sync(&dev->nix, eth_sec->sa, eth_sec->inb, - ROC_NIX_INL_SA_OP_RELOAD); - if (eth_sec->inl_dev) roc_nix_inl_dev_unlock(); diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index e9bebfe..5059fca 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -78,6 +78,17 @@ nix_security_setup(struct cnxk_eth_dev *dev) * Will be overridden when event mode rq's are setup. */ cnxk_nix_inb_mode_set(dev, true); + + /* Allocate memory to be used as dptr for CPT ucode + * WRITE_SA op. + */ + dev->inb.sa_dptr = + plt_zmalloc(ROC_NIX_INL_OT_IPSEC_INB_HW_SZ, 0); + if (!dev->inb.sa_dptr) { + plt_err("Couldn't allocate memory for SA dptr"); + rc = -ENOMEM; + goto cleanup; + } } if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY || @@ -95,14 +106,25 @@ nix_security_setup(struct cnxk_eth_dev *dev) if (rc) { plt_err("Failed to initialize nix inline outb, rc=%d", rc); - goto cleanup; + goto sa_dptr_free; } dev->outb.lf_base = roc_nix_inl_outb_lf_base_get(nix); - /* Skip the rest if RTE_ETH_TX_OFFLOAD_SECURITY is not enabled */ + /* Skip the rest if DEV_TX_OFFLOAD_SECURITY is not enabled */ if (!(dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)) - goto done; + return 0; + + /* Allocate memory to be used as dptr for CPT ucode + * WRITE_SA op. + */ + dev->outb.sa_dptr = + plt_zmalloc(ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ, 0); + if (!dev->outb.sa_dptr) { + plt_err("Couldn't allocate memory for SA dptr"); + rc = -ENOMEM; + goto sa_dptr_free; + } rc = -ENOMEM; /* Allocate a bitmap to alloc and free sa indexes */ @@ -112,7 +134,7 @@ nix_security_setup(struct cnxk_eth_dev *dev) plt_err("Outbound SA bmap alloc failed"); rc |= roc_nix_inl_outb_fini(nix); - goto cleanup; + goto sa_dptr_free; } rc = -EIO; @@ -122,7 +144,7 @@ nix_security_setup(struct cnxk_eth_dev *dev) rc |= roc_nix_inl_outb_fini(nix); plt_free(mem); - goto cleanup; + goto sa_dptr_free; } for (i = 0; i < dev->outb.max_sa; i++) @@ -132,9 +154,13 @@ nix_security_setup(struct cnxk_eth_dev *dev) dev->outb.sa_bmap_mem = mem; dev->outb.sa_bmap = bmap; } - -done: return 0; + +sa_dptr_free: + if (dev->inb.sa_dptr) + plt_free(dev->inb.sa_dptr); + if (dev->outb.sa_dptr) + plt_free(dev->outb.sa_dptr); cleanup: if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) rc |= roc_nix_inl_inb_fini(nix); @@ -196,6 +222,11 @@ nix_security_release(struct cnxk_eth_dev *dev) if (rc) plt_err("Failed to cleanup nix inline inb, rc=%d", rc); ret |= rc; + + if (dev->inb.sa_dptr) { + plt_free(dev->inb.sa_dptr); + dev->inb.sa_dptr = NULL; + } } /* Cleanup Inline outbound */ @@ -216,6 +247,10 @@ nix_security_release(struct cnxk_eth_dev *dev) plt_free(dev->outb.sa_bmap_mem); dev->outb.sa_bmap = NULL; dev->outb.sa_bmap_mem = NULL; + if (dev->outb.sa_dptr) { + plt_free(dev->outb.sa_dptr); + dev->outb.sa_dptr = NULL; + } } dev->inb.inl_dev = false; diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 7e4939f..93879c8 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -268,6 +268,9 @@ struct cnxk_eth_dev_sec_inb { /* List of sessions */ struct cnxk_eth_sec_sess_list list; + + /* DPTR for WRITE_SA microcode op */ + void *sa_dptr; }; /* Outbound security data */ @@ -298,6 +301,9 @@ struct cnxk_eth_dev_sec_outb { /* List of sessions */ struct cnxk_eth_sec_sess_list list; + + /* DPTR for WRITE_SA microcode op */ + void *sa_dptr; }; struct cnxk_eth_dev { diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c index ae3e49c..3fef056 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec.c @@ -277,6 +277,7 @@ cnxk_nix_inl_dev_probe(struct rte_pci_driver *pci_drv, goto free_mem; } + inl_dev->attach_cptlf = true; rc = roc_nix_inl_dev_init(inl_dev); if (rc) { plt_err("Failed to init nix inl device, rc=%d(%s)", rc, From patchwork Tue Nov 2 15:54:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 103518 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1FF8CA0C4E; Tue, 2 Nov 2021 16:55:29 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1929E426D7; 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Tue, 02 Nov 2021 08:54:49 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 2 Nov 2021 08:54:48 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 2 Nov 2021 08:54:48 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 72D135B6932; Tue, 2 Nov 2021 08:54:46 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Date: Tue, 2 Nov 2021 21:24:19 +0530 Message-ID: <20211102155421.486-8-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20211102155421.486-1-ndabilpuram@marvell.com> References: <20211102155421.486-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: sk6DDXBqVY9IAu8YHI0XWp_Mgw1wEjYm X-Proofpoint-ORIG-GUID: sk6DDXBqVY9IAu8YHI0XWp_Mgw1wEjYm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-02_08,2021-11-02_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 8/9] net/cnxk: allow fc on lbk and enable tm bp on Rx pause X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Allow flow control on LBK VF's and enable TM to listen on backpressure when Rx pause is enabled. Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cnxk_ethdev.c | 12 ++++++------ drivers/net/cnxk/cnxk_ethdev_ops.c | 14 +++++++++++++- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 5059fca..a62ded6 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -332,7 +332,7 @@ nix_update_flow_ctrl_config(struct rte_eth_dev *eth_dev) struct cnxk_fc_cfg *fc = &dev->fc_cfg; struct rte_eth_fc_conf fc_cfg = {0}; - if (roc_nix_is_vf_or_sdp(&dev->nix)) + if (roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) return 0; fc_cfg.mode = fc->mode; @@ -1233,6 +1233,11 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) goto cq_fini; } + /* Setup Inline security support */ + rc = nix_security_setup(dev); + if (rc) + goto cq_fini; + /* Init flow control configuration */ fc_cfg.type = ROC_NIX_FC_RXCHAN_CFG; fc_cfg.rxchan_cfg.enable = true; @@ -1249,11 +1254,6 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) goto cq_fini; } - /* Setup Inline security support */ - rc = nix_security_setup(dev); - if (rc) - goto cq_fini; - /* * Restore queue config when reconfigure followed by * reconfigure and no queue configure invoked from application case. diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c index baa474f..7b3ee75 100644 --- a/drivers/net/cnxk/cnxk_ethdev_ops.c +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -250,7 +250,7 @@ cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev, uint8_t rx_pause, tx_pause; int rc, i; - if (roc_nix_is_vf_or_sdp(nix)) { + if (roc_nix_is_vf_or_sdp(nix) && !roc_nix_is_lbk(nix)) { plt_err("Flow control configuration is not allowed on VFs"); return -ENOTSUP; } @@ -287,6 +287,18 @@ cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev, } } + /* Check if RX pause frame is enabled or not */ + if (fc->rx_pause ^ rx_pause) { + struct roc_nix_fc_cfg fc_cfg; + + memset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg)); + fc_cfg.type = ROC_NIX_FC_TM_CFG; + fc_cfg.tm_cfg.enable = !!rx_pause; + rc = roc_nix_fc_config_set(nix, &fc_cfg); + if (rc) + return rc; + } + rc = roc_nix_fc_mode_set(nix, mode_map[fc_conf->mode]); if (rc) return rc; From patchwork Tue Nov 2 15:54:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 103519 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9AC77A0C4E; Tue, 2 Nov 2021 16:55:38 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 76501426DD; Tue, 2 Nov 2021 16:54:56 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3D1A9426DD for ; Tue, 2 Nov 2021 16:54:54 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1A2CjgHb030466 for ; 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Tue, 2 Nov 2021 08:54:51 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 9788A5B6948; Tue, 2 Nov 2021 08:54:49 -0700 (PDT) From: Nithin Dabilpuram To: , Pavan Nikhilesh , "Shijith Thotton" , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Date: Tue, 2 Nov 2021 21:24:20 +0530 Message-ID: <20211102155421.486-9-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20211102155421.486-1-ndabilpuram@marvell.com> References: <20211102155421.486-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 5aW20mrpaPhhB_6jasY786j0z9M1Hx6j X-Proofpoint-ORIG-GUID: 5aW20mrpaPhhB_6jasY786j0z9M1Hx6j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-02_08,2021-11-02_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 9/9] event/cnxk: disable drop re on vector enable for cn10k a0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Disable drop_re i.e dropping packets with receive errors on vector enable for few cn10k revisions due to HW errata. Signed-off-by: Nithin Dabilpuram --- drivers/event/cnxk/cnxk_eventdev_adptr.c | 8 ++++++++ drivers/net/cnxk/cn10k_ethdev.c | 11 ++++++++--- drivers/net/cnxk/cnxk_ethdev.h | 1 + 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c index b9a5df0..fdcd68c 100644 --- a/drivers/event/cnxk/cnxk_eventdev_adptr.c +++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c @@ -242,6 +242,10 @@ cnxk_sso_rx_adapter_queue_add( queue_conf->vector_sz, queue_conf->vector_timeout_ns, queue_conf->vector_mp); + + if (cnxk_eth_dev->vec_drop_re_dis) + rc |= roc_nix_rx_drop_re_set(&cnxk_eth_dev->nix, + false); } rox_nix_fc_npa_bp_cfg(&cnxk_eth_dev->nix, rxq_sp->qconf.mp->pool_id, true, @@ -290,6 +294,10 @@ cnxk_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev, rxq_sp->qconf.mp->pool_id, false, dev->force_ena_bp); cnxk_eth_dev->nb_rxq_sso--; + + /* Enable drop_re if it was disabled earlier */ + if (cnxk_eth_dev->vec_drop_re_dis && !cnxk_eth_dev->nb_rxq_sso) + rc |= roc_nix_rx_drop_re_set(&cnxk_eth_dev->nix, true); } if (rc < 0) diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c index 5d9536c..8378cbf 100644 --- a/drivers/net/cnxk/cn10k_ethdev.c +++ b/drivers/net/cnxk/cn10k_ethdev.c @@ -553,10 +553,15 @@ cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) dev = cnxk_eth_pmd_priv(eth_dev); - /* DROP_RE is not supported with inline IPSec for CN10K A0 */ - if (roc_model_is_cn10ka_a0() || roc_model_is_cnf10ka_a0() || - roc_model_is_cnf10kb_a0()) + /* DROP_RE is not supported with inline IPSec for CN10K A0 and + * when vector mode is enabled. + */ + if ((roc_model_is_cn10ka_a0() || roc_model_is_cnf10ka_a0() || + roc_model_is_cnf10kb_a0()) && + !roc_env_is_asim()) { dev->ipsecd_drop_re_dis = 1; + dev->vec_drop_re_dis = 1; + } /* Register up msg callbacks for PTP information */ roc_nix_ptp_info_cb_register(&dev->nix, cn10k_nix_ptp_info_update_cb); diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 93879c8..7cbd9f1 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -342,6 +342,7 @@ struct cnxk_eth_dev { struct { uint64_t cq_min_4k : 1; uint64_t ipsecd_drop_re_dis : 1; + uint64_t vec_drop_re_dis : 1; }; uint64_t hwcap; };