From patchwork Wed Nov 3 11:22:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar Velumuri X-Patchwork-Id: 103648 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D2E54A0C53; Wed, 3 Nov 2021 12:22:27 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9F2C74115A; Wed, 3 Nov 2021 12:22:27 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 1554441134 for ; Wed, 3 Nov 2021 12:22:25 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1A36ocdc008843; Wed, 3 Nov 2021 04:22:25 -0700 DKIM-Signature: v=1; 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Wed, 3 Nov 2021 04:22:23 -0700 Received: from vvelumuri_asim.marvell.com (unknown [10.29.53.48]) by maili.marvell.com (Postfix) with ESMTP id 74CE83F704F; Wed, 3 Nov 2021 04:22:20 -0700 (PDT) From: Vidya Sagar Velumuri To: , , , , , CC: , Date: Wed, 3 Nov 2021 11:22:09 +0000 Message-ID: <20211103112210.32650-1-vvelumuri@marvell.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Proofpoint-GUID: OKz8eOLfwAUgS11yT3ejyUMAbWLt96G8 X-Proofpoint-ORIG-GUID: OKz8eOLfwAUgS11yT3ejyUMAbWLt96G8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-03_03,2021-11-03_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v1 1/2] common/cnxk: fix: use appropriate zuc constants X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Use appropriate ZUC constants based on key length and mac length Fixes: a90db80d7d72 ("common/cnxk: set key length for PDCP algos") Cc: vvelumuri@marvell.com Signed-off-by: Vidya Sagar Velumuri Change-Id: Ie982110035916d2168cc4e79b7f5145c6d6ac021 diff --git a/drivers/common/cnxk/roc_se.c b/drivers/common/cnxk/roc_se.c index 4edbc8e547..e81a0c9ecb 100644 --- a/drivers/common/cnxk/roc_se.c +++ b/drivers/common/cnxk/roc_se.c @@ -4,10 +4,26 @@ #include "roc_api.h" -static uint8_t zuc_d[32] = {0x44, 0xD7, 0x26, 0xBC, 0x62, 0x6B, 0x13, 0x5E, - 0x57, 0x89, 0x35, 0xE2, 0x71, 0x35, 0x09, 0xAF, - 0x4D, 0x78, 0x2F, 0x13, 0x6B, 0xC4, 0x1A, 0xF1, - 0x5E, 0x26, 0x3C, 0x4D, 0x78, 0x9A, 0x47, 0xAC}; +static uint8_t zuc_key128[32] = { + 0x44, 0xD7, 0x26, 0xBC, 0x62, 0x6B, 0x13, 0x5E, 0x57, 0x89, 0x35, + 0xE2, 0x71, 0x35, 0x09, 0xAF, 0x4D, 0x78, 0x2F, 0x13, 0x6B, 0xC4, + 0x1A, 0xF1, 0x5E, 0x26, 0x3C, 0x4D, 0x78, 0x9A, 0x47, 0xAC}; + +static uint8_t zuc_key256[16] = {0x22, 0x2f, 0x24, 0x2a, 0x6d, 0x40, + 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, + 0x40, 0x52, 0x10, 0x30}; + +static uint8_t zuc_key256_mac4[16] = {0x22, 0x2f, 0x25, 0x2a, 0x6d, 0x40, + 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, + 0x40, 0x52, 0x10, 0x30}; + +static uint8_t zuc_key256_mac8[16] = {0x23, 0x2f, 0x24, 0x2a, 0x6d, 0x40, + 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, + 0x40, 0x52, 0x10, 0x30}; + +static uint8_t zuc_key256_mac16[16] = {0x23, 0x2f, 0x25, 0x2a, 0x6d, 0x40, + 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, + 0x40, 0x52, 0x10, 0x30}; static inline void cpt_snow3g_key_gen(const uint8_t *ck, uint32_t *keyx) @@ -185,6 +201,28 @@ cpt_pdcp_mac_len_set(struct roc_se_zuc_snow3g_ctx *zs_ctx, uint16_t mac_len) return 0; } +static void +cpt_pdcp_update_zuc_const(uint8_t *zuc_const, int key_len, int mac_len) +{ + if (key_len == 16) { + memcpy(zuc_const, zuc_key128, 32); + } else if (key_len == 32) { + switch (mac_len) { + case 4: + memcpy(zuc_const, zuc_key256_mac4, 16); + break; + case 8: + memcpy(zuc_const, zuc_key256_mac8, 16); + break; + case 16: + memcpy(zuc_const, zuc_key256_mac16, 16); + break; + default: + plt_err("Unsupported mac len"); + } + } +} + int roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type, const uint8_t *key, uint16_t key_len, uint16_t mac_len) @@ -245,7 +283,7 @@ roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type, return ret; se_ctx->pdcp_alg_type = ROC_SE_PDCP_ALG_TYPE_ZUC; memcpy(ci_key, key, key_len); - memcpy(zuc_const, zuc_d, 32); + cpt_pdcp_update_zuc_const(zuc_const, key_len, mac_len); se_ctx->fc_type = ROC_SE_PDCP; se_ctx->zsk_flags = 0x1; break; @@ -421,7 +459,11 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, zs_ctx->zuc.otk_ctx.w0.s.alg_type = ROC_SE_PDCP_ALG_TYPE_ZUC; se_ctx->pdcp_alg_type = ROC_SE_PDCP_ALG_TYPE_ZUC; memcpy(ci_key, key, key_len); - memcpy(zuc_const, zuc_d, 32); + if (key_len == 32) + memcpy(zuc_const, zuc_key256, 16); + else + memcpy(zuc_const, zuc_key128, 32); + se_ctx->zsk_flags = 0; goto success; case ROC_SE_AES_CTR_EEA2: diff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h index 051d496f88..5be832fa75 100644 --- a/drivers/common/cnxk/roc_se.h +++ b/drivers/common/cnxk/roc_se.h @@ -259,7 +259,8 @@ struct roc_se_fc_params { struct roc_se_buf_ptr meta_buf; struct roc_se_buf_ptr ctx_buf; uint32_t rsvd2; - uint16_t rsvd3; + uint8_t rsvd3; + uint8_t iv_ovr; uint8_t cipher_iv_len; uint8_t auth_iv_len; From patchwork Wed Nov 3 11:22:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar Velumuri X-Patchwork-Id: 103649 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 93C22A0C53; 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Wed, 03 Nov 2021 04:22:33 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 3 Nov 2021 04:22:31 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 3 Nov 2021 04:22:30 -0700 Received: from vvelumuri_asim.marvell.com (unknown [10.29.53.48]) by maili.marvell.com (Postfix) with ESMTP id CC7583F7041; Wed, 3 Nov 2021 04:22:28 -0700 (PDT) From: Vidya Sagar Velumuri To: , , , , , CC: , Date: Wed, 3 Nov 2021 11:22:10 +0000 Message-ID: <20211103112210.32650-2-vvelumuri@marvell.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211103112210.32650-1-vvelumuri@marvell.com> References: <20211103112210.32650-1-vvelumuri@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: _ONHuDd02ZW-WvCehuZyCfhMgClzXdyV X-Proofpoint-GUID: _ONHuDd02ZW-WvCehuZyCfhMgClzXdyV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-03_03,2021-11-03_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v1 2/2] crypto/cnxk: fix: supported iv length for zuc 256 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Fix supported IV length for ZUC 256 Add support in capability for 4 byte mac len for zuc 256 Pack the last 8 bytes of IV to 6 bytes by ignoring the 2 msb bits of each byte. Fixes: 29742632ac9e ("crypto/cnxk: support ZUC with 256-bit key") Cc: vvelumuri@marvell.com Signed-off-by: Vidya Sagar Velumuri Change-Id: I00e103323a4018e26452717fa31238aec668ec25 diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c index a53b489a04..b94ff851a3 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c @@ -874,8 +874,8 @@ cn10k_crypto_caps_update(struct rte_cryptodev_capabilities cnxk_caps[]) caps->sym.cipher.key_size.max = 32; caps->sym.cipher.key_size.increment = 16; - caps->sym.cipher.iv_size.max = 24; - caps->sym.cipher.iv_size.increment = 8; + caps->sym.cipher.iv_size.max = 25; + caps->sym.cipher.iv_size.increment = 1; } if ((caps->op == RTE_CRYPTO_OP_TYPE_SYMMETRIC) && @@ -886,8 +886,8 @@ cn10k_crypto_caps_update(struct rte_cryptodev_capabilities cnxk_caps[]) caps->sym.auth.key_size.increment = 16; caps->sym.auth.digest_size.max = 16; caps->sym.auth.digest_size.increment = 4; - caps->sym.auth.iv_size.max = 24; - caps->sym.auth.iv_size.increment = 8; + caps->sym.auth.iv_size.max = 25; + caps->sym.auth.iv_size.increment = 1; } } } diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h index 7959c4c7af..e4e554e8b7 100644 --- a/drivers/crypto/cnxk/cnxk_se.h +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -37,7 +37,24 @@ struct cnxk_se_sess { } __rte_cache_aligned; static inline void -pdcp_iv_copy(uint8_t *iv_d, uint8_t *iv_s, const uint8_t pdcp_alg_type) +cpt_pack_iv(uint8_t *iv_src, uint8_t *iv_dst) +{ + iv_dst[16] = iv_src[16]; + /* pack the last 8 bytes of IV to 6 bytes. + * discard the 2 MSB bits of each byte + */ + iv_dst[17] = (((iv_src[17] & 0x3f) << 2) | ((iv_src[18] >> 4) & 0x3)); + iv_dst[18] = (((iv_src[18] & 0xf) << 4) | ((iv_src[19] >> 2) & 0xf)); + iv_dst[19] = (((iv_src[19] & 0x3) << 6) | (iv_src[20] & 0x3f)); + + iv_dst[20] = (((iv_src[21] & 0x3f) << 2) | ((iv_src[22] >> 4) & 0x3)); + iv_dst[21] = (((iv_src[22] & 0xf) << 4) | ((iv_src[23] >> 2) & 0xf)); + iv_dst[22] = (((iv_src[23] & 0x3) << 6) | (iv_src[24] & 0x3f)); +} + +static inline void +pdcp_iv_copy(uint8_t *iv_d, uint8_t *iv_s, const uint8_t pdcp_alg_type, + uint8_t pack_iv) { uint32_t *iv_s_temp, iv_temp[4]; int j; @@ -56,6 +73,8 @@ pdcp_iv_copy(uint8_t *iv_d, uint8_t *iv_s, const uint8_t pdcp_alg_type) } else { /* ZUC doesn't need a swap */ memcpy(iv_d, iv_s, 16); + if (pack_iv) + cpt_pack_iv(iv_s, iv_d); } } @@ -984,6 +1003,7 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, uint64_t offset_ctrl; uint64_t *offset_vaddr; uint8_t *iv_s; + uint8_t pack_iv = 0; union cpt_inst_w4 cpt_inst_w4; se_ctx = params->ctx_buf.vaddr; @@ -999,6 +1019,11 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, iv_s = params->auth_iv_buf; iv_len = params->auth_iv_len; + if (iv_len == 25) { + iv_len -= 2; + pack_iv = 1; + } + /* * Microcode expects offsets in bytes * TODO: Rounding off @@ -1023,6 +1048,11 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, iv_s = params->iv_buf; iv_len = params->cipher_iv_len; + if (iv_len == 25) { + iv_len -= 2; + pack_iv = 1; + } + /* EEA3 or UEA2 */ /* * Microcode expects offsets in bytes @@ -1081,7 +1111,7 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN; uint8_t *iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN); - pdcp_iv_copy(iv_d, iv_s, pdcp_alg_type); + pdcp_iv_copy(iv_d, iv_s, pdcp_alg_type, pack_iv); *offset_vaddr = offset_ctrl; } else { @@ -1095,7 +1125,8 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, /* save space for iv */ offset_vaddr = m_vaddr; - m_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + iv_len; + m_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + + RTE_ALIGN_CEIL(iv_len, 8); cpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE; @@ -1123,7 +1154,7 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, *offset_vaddr = offset_ctrl; iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN); - pdcp_iv_copy(iv_d, iv_s, pdcp_alg_type); + pdcp_iv_copy(iv_d, iv_s, pdcp_alg_type, pack_iv); /* input data */ size = inputlen - iv_len;