From patchwork Thu Nov 4 12:49:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raja Zidane X-Patchwork-Id: 103763 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 53876A0548; Thu, 4 Nov 2021 13:50:06 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CC64442716; Thu, 4 Nov 2021 13:50:00 +0100 (CET) Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam08on2069.outbound.protection.outlook.com [40.107.101.69]) by mails.dpdk.org (Postfix) with ESMTP id 7F4DA41223; Thu, 4 Nov 2021 13:49:58 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=JyxoSVA1UrJBjNjNycwLlr8NU5/NLKg44cRDIUc2w2SRuSsdKq5aAotVgqhaThaISeEch1ED249kAoSqWogEUkkc9nVzb4kImRnCYq0RX1moRn3fgCohA8xVUwrJ9ACDB2ow+jbm5IUbr823tmncy2vgKWnlmvZx7GJ7T2xcn/d6MnjxiM8sJzhbZy8UGkGvCt3/6eVFCrAWo5fDjuEC6ge5Wyh+OufYxAKJJWUlyF8oycOLYy0EMfHVv+ny48/TruMQtNUP25JaLkdrEOk/+bMg1scF4G+RYvH4fUWMtAPbeYuQ43pSC3dsiz6c4j1S+JXjPOT83s9nY7x4Kos7qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=o2IFU7XPo1Y9+rh+0e0Ux7Ko2XWKjWch7yMBO5ODr9E=; b=mOVp5O00YcLtLrwosJgeGyYDMOArMgLRUy+Pl5rNXUUUKj1qSPSEEIMk04nbFq7aTDHgVkbYDwS1ltGNc/LQ3Yj9jmKIhF718Cx+pRLs2ZrZJCTJ4huo3LOYQnYwz3fFVqxFztW7OHck4bUjNtogRIo0QetkgtBAIhg9WBTTWR/bNA5p6mxfllkkD4fIgNlBilUwL7bhIaDBndWDbu/bCmjhRrtjaUDPKCRme6kZBMgJaUTjfgRRXJyuIXAmogxAi975sxISjOcqgX/e7t5Vye7+pHG02LfxF+EOY3HtiUcUh+GMI10Z8encD+cnYH5NR05V6ntgQ7k6dgVH/9DPpQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=o2IFU7XPo1Y9+rh+0e0Ux7Ko2XWKjWch7yMBO5ODr9E=; b=AJ96VNDlf7tkkXYbXPkSt1YCMD8EW2ve2V3zWQBqbd3yXqVY10MSC121HkHOmhqm80WCc4/viMfXu/sAbQhXpatYYN38hJX81Q5to28g7nxaA0nkL376LJCPlfShi1hOdIfMbAoQtFf9M0aUcnmGGlIGupzq+4KsFvkDhgXT932y9KVewGOg5Pi9QefFn32MTQghX23K5S0mUxeO6g71aV2XlFRL8WJaLfM5ZuUGcL/7Ec/FvbEvJdjjjARLgIjCfpf79fD1p/Y4xSegvBVGQAIyrqfBIgaJ1WoON9gt22BeFXC7EIN8nQtw3hkp46Z0KhN3RgKbuC5+G0VSTShSMg== Received: from BN9PR03CA0391.namprd03.prod.outlook.com (2603:10b6:408:111::6) by DM6PR12MB4187.namprd12.prod.outlook.com (2603:10b6:5:212::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.11; Thu, 4 Nov 2021 12:49:56 +0000 Received: from BN8NAM11FT045.eop-nam11.prod.protection.outlook.com (2603:10b6:408:111:cafe::8) by BN9PR03CA0391.outlook.office365.com (2603:10b6:408:111::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.11 via Frontend Transport; Thu, 4 Nov 2021 12:49:56 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT045.mail.protection.outlook.com (10.13.177.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Thu, 4 Nov 2021 12:49:56 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 4 Nov 2021 12:49:52 +0000 From: Raja Zidane To: CC: Matan Azrad , Date: Thu, 4 Nov 2021 12:49:26 +0000 Message-ID: <20211104124929.24899-2-rzidane@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211104124929.24899-1-rzidane@nvidia.com> References: <20211104124929.24899-1-rzidane@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1b69ac63-d216-4fa3-5e4f-08d99f919ac8 X-MS-TrafficTypeDiagnostic: DM6PR12MB4187: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3826; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 06GaI/jEY6sTfmhlAeXI8hCgCUslkvkVvvLWnyxyQuWStUm1hbnlLkbCrfD3VQ518FMRAwP0V8rwj8J9aKEGDzuhq111C7B/D2GVaZNEI2P/MzQU0liIKnswzcxoA65VBO5w34BSX8rRGjOMmUQoqhO5/VzidZbkbs3GNJCunnK08wQ1bjaSOvP+Y222aCz5mcmV7p97VEehOIhr9MYmOgzr82m4DUh6AYOYrVzWOzqS7lmpioKXh/kJZjpC05uEnjtsuIWewtAEHIGw4tjK2fz1M06k3Sws543P2H+l0tjiLRasK+xsvT9tHgy0sTLgENPFCn+1IMML/ZidY4+I9760Kr+sGFsTRW8KexGgP7eloD/cCcoaet4iZtjIcpMElpchAlZWTg/nWJFOng6EIiPw8Ufv+2KRWx5Nz4VKHbsyNJVJW2BeE2gE4SLF3Ts08FSRx8vcB2KbeC9yBEjRSkctDNNPhq2vhICAX5u/fEck5vus45LI7qNNaHfMkQFRwa3yPSIzvhyArwGw85bvsuchyiLEeH36TP/vJew493YQaoHA4Z1DaiDkxNJY0/SaDqgnlY9/7H790xoVDB/D0KvIlkXmcXSourJPAwHSCR1MF+XJeq46yYSIpTVsrUSVAVi0xmpAIFDB7FbsEDjYmbnWb6INPqZMYGnj0C/WESx4bXJgYWP/4AWXSiGvOhGdspA4zDn/+sf0mPwMjDQSPQ== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(83380400001)(36860700001)(336012)(1076003)(86362001)(4326008)(450100002)(54906003)(6666004)(2616005)(7636003)(426003)(316002)(55016002)(82310400003)(356005)(8936002)(16526019)(47076005)(70206006)(186003)(508600001)(8676002)(36756003)(26005)(6286002)(7696005)(5660300002)(2906002)(6916009)(70586007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 12:49:56.2934 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b69ac63-d216-4fa3-5e4f-08d99f919ac8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4187 Subject: [dpdk-dev] [PATCH 1/4] common/mlx5: fix overflows in DevX queues size calculations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The HW QP/SQ/RQ/CQ queue sizes may be bigger than 64KB. The width of the variable handled the queue size is 16 bits which cannot contain the maximum queue size. Replace the size type to be uint32_t. Fixes: 9dab4d62b4dc ("common/mlx5: share DevX CQ creation") Fixes: 38f537635c15 ("common/mlx5: share DevX SQ creation") Fixes: f9213ab12cf9 ("common/mlx5: share DevX queue pair operations") Cc: stable@dpdk.org Signed-off-by: Raja Zidane Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_common_devx.c | 16 ++++++++-------- drivers/common/mlx5/mlx5_common_devx.h | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/common/mlx5/mlx5_common_devx.c b/drivers/common/mlx5/mlx5_common_devx.c index 825f84b183..0e58308b0b 100644 --- a/drivers/common/mlx5/mlx5_common_devx.c +++ b/drivers/common/mlx5/mlx5_common_devx.c @@ -86,7 +86,7 @@ mlx5_devx_cq_create(void *ctx, struct mlx5_devx_cq *cq_obj, uint16_t log_desc_n, size_t alignment = MLX5_CQE_BUF_ALIGNMENT; uint32_t umem_size, umem_dbrec; uint32_t eqn; - uint16_t cq_size = 1 << log_desc_n; + uint32_t num_of_cqes = RTE_BIT32(log_desc_n); int ret; if (page_size == (size_t)-1 || alignment == (size_t)-1) { @@ -102,7 +102,7 @@ mlx5_devx_cq_create(void *ctx, struct mlx5_devx_cq *cq_obj, uint16_t log_desc_n, return -rte_errno; } /* Allocate memory buffer for CQEs and doorbell record. */ - umem_size = sizeof(struct mlx5_cqe) * cq_size; + umem_size = sizeof(struct mlx5_cqe) * num_of_cqes; umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); umem_size += MLX5_DBR_SIZE; umem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size, @@ -142,7 +142,7 @@ mlx5_devx_cq_create(void *ctx, struct mlx5_devx_cq *cq_obj, uint16_t log_desc_n, cq_obj->cq = cq; cq_obj->db_rec = RTE_PTR_ADD(cq_obj->umem_buf, umem_dbrec); /* Mark all CQEs initially as invalid. */ - mlx5_cq_init(cq_obj, cq_size); + mlx5_cq_init(cq_obj, num_of_cqes); return 0; error: ret = rte_errno; @@ -211,7 +211,7 @@ mlx5_devx_sq_create(void *ctx, struct mlx5_devx_sq *sq_obj, uint16_t log_wqbb_n, void *umem_buf = NULL; size_t alignment = MLX5_WQE_BUF_ALIGNMENT; uint32_t umem_size, umem_dbrec; - uint16_t sq_size = 1 << log_wqbb_n; + uint32_t num_of_wqbbs = RTE_BIT32(log_wqbb_n); int ret; if (alignment == (size_t)-1) { @@ -220,7 +220,7 @@ mlx5_devx_sq_create(void *ctx, struct mlx5_devx_sq *sq_obj, uint16_t log_wqbb_n, return -rte_errno; } /* Allocate memory buffer for WQEs and doorbell record. */ - umem_size = MLX5_WQE_SIZE * sq_size; + umem_size = MLX5_WQE_SIZE * num_of_wqbbs; umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); umem_size += MLX5_DBR_SIZE; umem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size, @@ -316,7 +316,7 @@ mlx5_devx_qp_destroy(struct mlx5_devx_qp *qp) * 0 on success, a negative errno value otherwise and rte_errno is set. */ int -mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, uint16_t log_wqbb_n, +mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, uint32_t log_wqbb_n, struct mlx5_devx_qp_attr *attr, int socket) { struct mlx5_devx_obj *qp = NULL; @@ -324,7 +324,7 @@ mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, uint16_t log_wqbb_n, void *umem_buf = NULL; size_t alignment = MLX5_WQE_BUF_ALIGNMENT; uint32_t umem_size, umem_dbrec; - uint16_t qp_size = 1 << log_wqbb_n; + uint32_t num_of_wqbbs = RTE_BIT32(log_wqbb_n); int ret; if (alignment == (size_t)-1) { @@ -333,7 +333,7 @@ mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, uint16_t log_wqbb_n, return -rte_errno; } /* Allocate memory buffer for WQEs and doorbell record. */ - umem_size = MLX5_WQE_SIZE * qp_size; + umem_size = MLX5_WQE_SIZE * num_of_wqbbs; umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); umem_size += MLX5_DBR_SIZE; umem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size, diff --git a/drivers/common/mlx5/mlx5_common_devx.h b/drivers/common/mlx5/mlx5_common_devx.h index f699405f69..7138bd7914 100644 --- a/drivers/common/mlx5/mlx5_common_devx.h +++ b/drivers/common/mlx5/mlx5_common_devx.h @@ -76,7 +76,7 @@ void mlx5_devx_qp_destroy(struct mlx5_devx_qp *qp); __rte_internal int mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, - uint16_t log_wqbb_n, + uint32_t log_wqbb_n, struct mlx5_devx_qp_attr *attr, int socket); __rte_internal From patchwork Thu Nov 4 12:49:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raja Zidane X-Patchwork-Id: 103764 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 464E7A0548; Thu, 4 Nov 2021 13:50:14 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1A41642724; Thu, 4 Nov 2021 13:50:02 +0100 (CET) Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam07on2058.outbound.protection.outlook.com [40.107.212.58]) by mails.dpdk.org (Postfix) with ESMTP id A9B684270F; Thu, 4 Nov 2021 13:50:00 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=JYsZeeRPjH8ebQ+H6kZfH7MvhcFKGOZGCUDdP+JuDT8H0o55+IoNxGEfHS6v+WtBxYxmneo74Af4uLjElngXmZjLdx+dKMHiQqEf9njiGznNidrpa0ZbMcGONu331NMBHHCJri6gjriozWGuREB14qkvsxr6WtAbLFowh4/ojRLx01Pum59NfKZTsWetXKkZHlRF1o2adJeC9QawF1DIBn/LDEHXwPXridKmPUHWfY0AiZXGo5RulsOEqabwf7YaClHP6LpLgyX0FQU3Mg+eTw9JBbriafvUlQVuEWSanhLg8gsnwSyz+FcgcGq3im2+usCbsJ684UnUo+miK3YVzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=HvyKCxF52EpIR7MoCRhYozFilxe0wInfqMul/mckr0A=; b=UBcJHKE1R6WRRJuAIHYDTyz9DjWiuu5SEqiJiFy6QqBvvnnNNTq+n2bATTuBWc0CW5j14EkgHtXWso6UuMtwVGScQSHZkr1FnCTqVeC5NVQhydnLcYW97CCBo66x5oUPvYftKkiyLCpWjSVlP0R8pbmqD9P68mtfVqpzwTNr/WEawOQyec8IoHQI02R/0UzuaPQbo4JqQ63Wd56gFYuIkagaYy5+ab6H0MqRosEyrIJrIgIl1PyrrDbgheBh3+BxIgKk5ARDb0rZDeCvPVjpgr7gxSxEoHyfrMzhHTcp0ObclSbYgjbywEKFrecEKca18V2Qwsci0G8fR0IHQ2aVRQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HvyKCxF52EpIR7MoCRhYozFilxe0wInfqMul/mckr0A=; b=E7Pv3qLVw4ijYrqn0Q3846luK91sMzwrp0Mx7+FZzhagD4X1354jtskhVZQTtGI4WIUUISs6PDzEdMKzmzsQKkDWet1nvKEzyYvkhWc+z18RFNv5sOq9DHsSyX3lxoNF+hsHcdN26xLQ02uL0a2pt+sGa2/arczZRUmNpx3gJiNfrCaf6T+jjiU4DqgdNwdsQnwQvcwi54HZAwyzBfTgIJlEA9TVRCnWzKjb5bQqzb9tjW7XSLZi+d7syPdT2akImtbt9KKYxJyHM49O2w8cYlYK4f98WD8eRMZ8shTEA6hhs0dohvLs/JeWxqeXARkyEvY3N6rXk8r4ro36TrV0Yw== Received: from BN9PR03CA0396.namprd03.prod.outlook.com (2603:10b6:408:111::11) by BYAPR12MB3528.namprd12.prod.outlook.com (2603:10b6:a03:138::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.15; Thu, 4 Nov 2021 12:49:58 +0000 Received: from BN8NAM11FT045.eop-nam11.prod.protection.outlook.com (2603:10b6:408:111:cafe::6b) by BN9PR03CA0396.outlook.office365.com (2603:10b6:408:111::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.10 via Frontend Transport; Thu, 4 Nov 2021 12:49:58 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT045.mail.protection.outlook.com (10.13.177.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Thu, 4 Nov 2021 12:49:57 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 4 Nov 2021 12:49:53 +0000 From: Raja Zidane To: CC: Matan Azrad , Date: Thu, 4 Nov 2021 12:49:27 +0000 Message-ID: <20211104124929.24899-3-rzidane@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211104124929.24899-1-rzidane@nvidia.com> References: <20211104124929.24899-1-rzidane@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c6e39c96-2a05-4c3a-6016-08d99f919ba1 X-MS-TrafficTypeDiagnostic: BYAPR12MB3528: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:52; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: quSeQnYnyXp/c2+kYx5jORsbIma5ZxEkBGfv52aZ7sc5kGNpF7oNOCRfT8u5Q9uhDyA2OI99abubnUl/5pT5Z0U1fxjXhXHpY/0D8jR9H2TAeI+WW+a3lYcb84Bv07PQCTEQFvS1AuibS/d9kAPNp/eiUuI4OTPIfddkcJKI1iU7bCeq2IjQDm47faWfoSpO/0iUllUmJnrBAHwpz0S4yRc0jvGqDW4eCDKEVvk/nX22jh3u60k1FBB/Y5JqlHv/F2i20dPzh6P03AzQcGqHiWJEk+8UofEE+B8eojbl+il8bvWPkrpsij3thnTb4pa17OiG6Ji76Ib+dRULqUP1EpXtaMZ19SYP4Zp3pqgmysELHochZGWA3mWaByKysLGFl6nC5+SIS8jMvMcQmF770Il9RwXUeU5DZHPxObmbVk+0NY2pF0uS1T1LOVN7GJbAa1FjMmJ8mF/9M4DnHLeaS4Kvn3ZKCyIu0+fC3uslmjhS7jHuFzNTXONEKdPt7B7rMZUPf8RbRcEGlxIA2UYuvZUIZ4lpnrONcmOKrq9e75mu+U7ikZTKT3dGlF7Sigfrs+v1D5R4Ww2WexPcUvoTuJlEXRU5aq6iYnd1RJOTRR1c5bEyVWf09I45OaSw5jkJA/romrGEg0XslpHjBhh2erB7NPZnwECQlwUsCtL6zCKdmWw3lx3NyMYrb/F7OMuTrhGVCgvcPO8uFzYhncNtHQ== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(2906002)(7696005)(70206006)(356005)(86362001)(70586007)(55016002)(6666004)(36756003)(4744005)(82310400003)(508600001)(36860700001)(2616005)(1076003)(47076005)(7636003)(6286002)(16526019)(186003)(8676002)(54906003)(26005)(336012)(8936002)(6916009)(426003)(316002)(450100002)(83380400001)(5660300002)(4326008); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 12:49:57.7925 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6e39c96-2a05-4c3a-6016-08d99f919ba1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3528 Subject: [dpdk-dev] [PATCH 2/4] crypto/mlx5: fix driver destroy before the configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When calling device close, unset dek is called which destroys a hash list. In case of error during dev probe, close is called when dek hlist is not initialized. Ensure non null list destroy. Fixes: 90646d6c6e22 ("crypto/mlx5: support basic operations") Cc: stable@dpdk.org Signed-off-by: Raja Zidane Acked-by: Matan Azrad --- drivers/crypto/mlx5/mlx5_crypto_dek.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto_dek.c b/drivers/crypto/mlx5/mlx5_crypto_dek.c index de0d2545d1..472ee373aa 100644 --- a/drivers/crypto/mlx5/mlx5_crypto_dek.c +++ b/drivers/crypto/mlx5/mlx5_crypto_dek.c @@ -156,6 +156,8 @@ mlx5_crypto_dek_setup(struct mlx5_crypto_priv *priv) void mlx5_crypto_dek_unset(struct mlx5_crypto_priv *priv) { - mlx5_hlist_destroy(priv->dek_hlist); - priv->dek_hlist = NULL; + if (priv->dek_hlist) { + mlx5_hlist_destroy(priv->dek_hlist); + priv->dek_hlist = NULL; + } } From patchwork Thu Nov 4 12:49:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raja Zidane X-Patchwork-Id: 103765 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 848A8A0548; Thu, 4 Nov 2021 13:50:21 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5020E42732; Thu, 4 Nov 2021 13:50:03 +0100 (CET) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2046.outbound.protection.outlook.com [40.107.237.46]) by mails.dpdk.org (Postfix) with ESMTP id C3EF24271E; Thu, 4 Nov 2021 13:50:01 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=l8BrgMR+0H5AnTigOFekbNtpgVRH8JP+oUoejqVGasXA7guR0B8EijnlHSZCjLiXQUTUuVmHW3F4WqiTu2AyEop5wzXikTESHPKbocO3U155eSHeyNp65aFuWl2QHL3iNLRXqx88dip15yU2xO3JPC2LXrdE/ITmyEZJej8hMS62zcN0ws15eq9jKmi710ltob07vrQczWN0n+7v9WS+qihX07ZUgbu8RhIHcmw7nxOXDBxPLj3QLdk/ZNQjAPOSB0JewvRSf75OxCOxoploKmybcHhvqhgNGLgom+KwZPyhiIJbLDd2ZQaKT1QJ5qIuPzBZ2X07gvHEj+vvVJKODA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=SbbyKUp+ygGpntHAmZoEgo+0nI4v2+ajcS+vVw2udcE=; b=e8Gw/M5nDBPWRSTLUwXWw/KpaPfB0xeudIwA40Lv8AsZb1QC1aBppDDkk5DsvVX1vi7LarI5LjLp+UREWQUhDKkYi2lgj6/UBRKg7rY63fRVxbUn+j2SDgpOY7UX3G1ilo8GS1DGNZMiQGV4EbSgDN7ynBJ/a/RwRIxdWU9a6atbXbl32JrwKDw1CbCy6sJ/+JrPo+IP/EATs/53GdDtnNnit6Nzetmn1qFfcSoMuT+KfwMjHKuKKZO0ZeTA8RM5mabtoVL3303IsjcRTuhSDJR+J+Rg4Dhu4e2ivalNDiPuJkeRvhiPJBmeF75tg2d23L7HF2Cy7eO02usos5Ymxw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SbbyKUp+ygGpntHAmZoEgo+0nI4v2+ajcS+vVw2udcE=; b=Gi/8NU633Ma9lwS6sQVuQLq116d4VVc7OagTia7KeikNqa8Qmy+hRFFZDDMaEvfNyJisEKDvbsLyBb7/NV7VVxs4ycehW/h5QBEDwlgQ+zhkpcazr6DEhXI6CwEpGDUuIFFwQyko4oWSTshbmeAAG1gwkzzTZgUlkoFEa70KMtXAWOoDXyQrVF04P+lHkQdb3QZ6/ejpBdYDf03THKJRbw2KqDKLn0N/F87OlWSvTfAuBfd2kkOPVGONpFPlh4U/9fqY/wDDKL0TFBHCQLvPRMMlOr3YhIuy92E+fLuV4zetF5FZw39TpFGrf8LnP3TEh2clZctyNWyCYIyRXGeWrg== Received: from BN9PR03CA0419.namprd03.prod.outlook.com (2603:10b6:408:111::34) by DM6PR12MB3243.namprd12.prod.outlook.com (2603:10b6:5:185::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18; Thu, 4 Nov 2021 12:49:59 +0000 Received: from BN8NAM11FT045.eop-nam11.prod.protection.outlook.com (2603:10b6:408:111:cafe::ee) by BN9PR03CA0419.outlook.office365.com (2603:10b6:408:111::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.11 via Frontend Transport; Thu, 4 Nov 2021 12:49:59 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT045.mail.protection.outlook.com (10.13.177.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Thu, 4 Nov 2021 12:49:59 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 4 Nov 2021 12:49:54 +0000 From: Raja Zidane To: CC: Matan Azrad , Date: Thu, 4 Nov 2021 12:49:28 +0000 Message-ID: <20211104124929.24899-4-rzidane@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211104124929.24899-1-rzidane@nvidia.com> References: <20211104124929.24899-1-rzidane@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d36a743d-74d5-45c2-4700-08d99f919c86 X-MS-TrafficTypeDiagnostic: DM6PR12MB3243: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QmobYEJjTn1EZ+lSKtOm4KUHruXhKtEKI+J6SaLV6shb9HXFs/cRlqnb3vwzGAqMNWbfFdkfxUZSlThmNY4qAXGvbIbIJhLYzKNYgwSvkHGJxf044T9LwxotD+PYAQByQglEU3k08jJ2Q+tb9q+Xlo5nINFgzkJ5WBaQ88xST+peSL+gXIzuduK7i0H/v4fcTGIsduWQ9JH4oUtVRajqVmGA97XleNTcU92xkua7KzvXJLYkPXTUwy4SOdwh55nozT6lNvliBoNqD/EZnn5GvxD+cgoml9Pnmu3MTcoGWOcVvmzuRDFuG2dnlASw2Q6FRqZPME4iqRt/Ny2IJCJwIZ0hmENe+PyLsEApwOsgz4sCi5CLKJlV0JMYPh+sQgyXXgDDNKlF2fpIn7QVOz/w4IawB6TbjuxzSAd2ORW7yRSzV1P4G+a8dHMqYn1kI/Sda5SpWtMFH/S4zh218UJxZaGWISYxgZfe7ydyWBBtaofmHK2678JWWTepyD8cyIAcIZ7gppXJKQpD6yO4czS15DHk/VbdP8uZn7m6+zTnuDJX43L8f1ZgNGoH2yP9ZYGK7kOH0DN/RQzEcyayuPojkjaDFO40I5wAcz9j3REfM8VAK6cwlz7mvc+tEWwbf/k8axCaf3YZ9gIjcK6OPmPRZyWeGeSlp2PkOfRMn+wX0/eLE+kFUg7r1U19LTc5R2gRMItdNYAzZdpPwHV6jvaXcg== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(356005)(5660300002)(7696005)(83380400001)(82310400003)(6666004)(508600001)(36756003)(26005)(36860700001)(86362001)(426003)(55016002)(450100002)(186003)(16526019)(6286002)(8936002)(70586007)(47076005)(336012)(4326008)(7636003)(2616005)(70206006)(316002)(54906003)(6916009)(8676002)(1076003)(2906002)(30864003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 12:49:59.3016 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d36a743d-74d5-45c2-4700-08d99f919c86 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3243 Subject: [dpdk-dev] [PATCH 3/4] crypto/mlx5: fix the queue size configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The DevX interface for QP creation expects the number of WQEBBs. Wrongly, the number of descriptors was provided to the QP creation. In addition, the QP size must be a power of 2 what was not guaranteed. Provide the number of WQEBBs to the QP creation API. Round up the SQ size to a power of 2. Rename (sq/rq)_size to num_of_(send/receive)_wqes. Fixes: 6152534e211e ("crypto/mlx5: support queue pairs operations") Cc: stable@dpdk.org Signed-off-by: Raja Zidane Acked-by: Matan Azrad Acked-by: Tal Shnaiderman --- drivers/common/mlx5/mlx5_devx_cmds.c | 14 +-- drivers/common/mlx5/mlx5_devx_cmds.h | 5 +- drivers/compress/mlx5/mlx5_compress.c | 4 +- drivers/crypto/mlx5/mlx5_crypto.c | 120 +++++++++++++++++++----- drivers/crypto/mlx5/mlx5_crypto.h | 8 +- drivers/regex/mlx5/mlx5_regex_control.c | 4 +- drivers/vdpa/mlx5/mlx5_vdpa_event.c | 4 +- 7 files changed, 120 insertions(+), 39 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 802c11c0d8..05382a66b8 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -832,6 +832,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, MLX5_HCA_CAP_OPMOD_GET_CUR); if (!hcattr) return rc; + attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); attr->flow_counter_bulk_alloc_bitmap = MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, @@ -2099,21 +2100,22 @@ mlx5_devx_cmd_create_qp(void *ctx, if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) MLX5_SET(qpc, qpc, log_page_size, attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); - if (attr->sq_size) { - MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); + if (attr->num_of_send_wqbbs) { + MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); MLX5_SET(qpc, qpc, log_sq_size, - rte_log2_u32(attr->sq_size)); + rte_log2_u32(attr->num_of_send_wqbbs)); } else { MLX5_SET(qpc, qpc, no_sq, 1); } - if (attr->rq_size) { - MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); + if (attr->num_of_receive_wqes) { + MLX5_ASSERT(RTE_IS_POWER_OF_2( + attr->num_of_receive_wqes)); MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - MLX5_LOG_RQ_STRIDE_SHIFT); MLX5_SET(qpc, qpc, log_rq_size, - rte_log2_u32(attr->rq_size)); + rte_log2_u32(attr->num_of_receive_wqes)); MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); } else { MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 2326f1e968..fdc253da00 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -247,6 +247,7 @@ struct mlx5_hca_attr { uint32_t log_max_mmo_decompress:5; uint32_t umr_modify_entity_size_disabled:1; uint32_t umr_indirect_mkey_disabled:1; + uint16_t max_wqe_sz_sq; }; /* LAG Context. */ @@ -462,9 +463,9 @@ struct mlx5_devx_qp_attr { uint32_t uar_index:24; uint32_t cqn:24; uint32_t log_page_size:5; - uint32_t rq_size:17; /* Must be power of 2. */ + uint32_t num_of_receive_wqes:17; /* Must be power of 2. */ uint32_t log_rq_stride:3; - uint32_t sq_size:17; /* Must be power of 2. */ + uint32_t num_of_send_wqbbs:17; /* Must be power of 2. */ uint32_t ts_format:2; uint32_t dbr_umem_valid:1; uint32_t dbr_umem_id; diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index c4081c5f7d..6bb750781f 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -243,8 +243,8 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, qp_attr.cqn = qp->cq.cq->id; qp_attr.ts_format = mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format); - qp_attr.rq_size = 0; - qp_attr.sq_size = RTE_BIT32(log_ops_n); + qp_attr.num_of_receive_wqes = 0; + qp_attr.num_of_send_wqbbs = RTE_BIT32(log_ops_n); qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp && priv->mmo_dma_qp; ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp, log_ops_n, &qp_attr, diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index 07c2a9c68b..7931a84070 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -557,7 +557,7 @@ mlx5_crypto_qp_init(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp) ucseg->if_cf_toe_cq_res = RTE_BE32(1u << MLX5_UMRC_IF_OFFSET); ucseg->mkey_mask = RTE_BE64(1u << 0); /* Mkey length bit. */ ucseg->ko_to_bs = rte_cpu_to_be_32 - ((RTE_ALIGN(priv->max_segs_num, 4u) << + ((MLX5_CRYPTO_KLM_SEGS_NUM(priv->umr_wqe_size) << MLX5_UMRC_KO_OFFSET) | (4 << MLX5_UMRC_TO_BS_OFFSET)); bsf->keytag = priv->keytag; /* Init RDMA WRITE WQE. */ @@ -581,7 +581,7 @@ mlx5_crypto_indirect_mkeys_prepare(struct mlx5_crypto_priv *priv, .umr_en = 1, .crypto_en = 1, .set_remote_rw = 1, - .klm_num = RTE_ALIGN(priv->max_segs_num, 4), + .klm_num = MLX5_CRYPTO_KLM_SEGS_NUM(priv->umr_wqe_size), }; for (umr = (struct mlx5_umr_wqe *)qp->qp_obj.umem_buf, i = 0; @@ -609,6 +609,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, uint16_t log_nb_desc = rte_log2_u32(qp_conf->nb_descriptors); uint32_t ret; uint32_t alloc_size = sizeof(*qp); + uint32_t log_wqbb_n; struct mlx5_devx_cq_attr cq_attr = { .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar), }; @@ -631,14 +632,16 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, DRV_LOG(ERR, "Failed to create CQ."); goto error; } + log_wqbb_n = rte_log2_u32(RTE_BIT32(log_nb_desc) * + (priv->wqe_set_size / MLX5_SEND_WQE_BB)); attr.pd = priv->cdev->pdn; attr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar); attr.cqn = qp->cq_obj.cq->id; - attr.rq_size = 0; - attr.sq_size = RTE_BIT32(log_nb_desc); + attr.num_of_receive_wqes = 0; + attr.num_of_send_wqbbs = RTE_BIT32(log_wqbb_n); attr.ts_format = mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format); - ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp_obj, log_nb_desc, + ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp_obj, log_wqbb_n, &attr, socket_id); if (ret) { DRV_LOG(ERR, "Failed to create QP."); @@ -783,10 +786,8 @@ mlx5_crypto_args_check_handler(const char *key, const char *val, void *opaque) return -errno; } if (strcmp(key, "max_segs_num") == 0) { - if (!tmp || tmp > MLX5_CRYPTO_MAX_SEGS) { - DRV_LOG(WARNING, "Invalid max_segs_num: %d, should" - " be less than %d.", - (uint32_t)tmp, MLX5_CRYPTO_MAX_SEGS); + if (!tmp) { + DRV_LOG(ERR, "max_segs_num must be greater than 0."); rte_errno = EINVAL; return -rte_errno; } @@ -845,6 +846,81 @@ mlx5_crypto_parse_devargs(struct rte_devargs *devargs, return 0; } +/* + * Calculate UMR WQE size and RDMA Write WQE size with the + * following limitations: + * - Each WQE size is multiple of 64. + * - The summarize of both UMR WQE and RDMA_W WQE is a power of 2. + * - The number of entries in the UMR WQE's KLM list is multiple of 4. + */ +static void +mlx5_crypto_get_wqe_sizes(uint32_t segs_num, uint32_t *umr_size, + uint32_t *rdmaw_size) +{ + uint32_t diff, wqe_set_size; + + *umr_size = MLX5_CRYPTO_UMR_WQE_STATIC_SIZE + + RTE_ALIGN(segs_num, 4) * + sizeof(struct mlx5_wqe_dseg); + /* Make sure UMR WQE size is multiple of WQBB. */ + *umr_size = RTE_ALIGN(*umr_size, MLX5_SEND_WQE_BB); + *rdmaw_size = sizeof(struct mlx5_rdma_write_wqe) + + sizeof(struct mlx5_wqe_dseg) * + (segs_num <= 2 ? 2 : 2 + + RTE_ALIGN(segs_num - 2, 4)); + /* Make sure RDMA_WRITE WQE size is multiple of WQBB. */ + *rdmaw_size = RTE_ALIGN(*rdmaw_size, MLX5_SEND_WQE_BB); + wqe_set_size = *rdmaw_size + *umr_size; + diff = rte_align32pow2(wqe_set_size) - wqe_set_size; + /* Make sure wqe_set size is power of 2. */ + if (diff) + *umr_size += diff; +} + +static uint8_t +mlx5_crypto_max_segs_num(uint16_t max_wqe_size) +{ + int klms_sizes = max_wqe_size - MLX5_CRYPTO_UMR_WQE_STATIC_SIZE; + uint32_t max_segs_cap = RTE_ALIGN_FLOOR(klms_sizes, MLX5_SEND_WQE_BB) / + sizeof(struct mlx5_wqe_dseg); + + MLX5_ASSERT(klms_sizes >= MLX5_SEND_WQE_BB); + while (max_segs_cap) { + uint32_t umr_wqe_size, rdmw_wqe_size; + + mlx5_crypto_get_wqe_sizes(max_segs_cap, &umr_wqe_size, + &rdmw_wqe_size); + if (umr_wqe_size <= max_wqe_size && + rdmw_wqe_size <= max_wqe_size) + break; + max_segs_cap -= 4; + } + return max_segs_cap; +} + +static int +mlx5_crypto_configure_wqe_size(struct mlx5_crypto_priv *priv, + uint16_t max_wqe_size, uint32_t max_segs_num) +{ + uint32_t rdmw_wqe_size, umr_wqe_size; + + mlx5_crypto_get_wqe_sizes(max_segs_num, &umr_wqe_size, + &rdmw_wqe_size); + priv->wqe_set_size = rdmw_wqe_size + umr_wqe_size; + if (umr_wqe_size > max_wqe_size || + rdmw_wqe_size > max_wqe_size) { + DRV_LOG(ERR, "Invalid max_segs_num: %u. should be %u or lower.", + max_segs_num, + mlx5_crypto_max_segs_num(max_wqe_size)); + rte_errno = EINVAL; + return -EINVAL; + } + priv->umr_wqe_size = (uint16_t)umr_wqe_size; + priv->umr_wqe_stride = priv->umr_wqe_size / MLX5_SEND_WQE_BB; + priv->max_rdmar_ds = rdmw_wqe_size / sizeof(struct mlx5_wqe_dseg); + return 0; +} + static int mlx5_crypto_dev_probe(struct mlx5_common_device *cdev) { @@ -860,7 +936,6 @@ mlx5_crypto_dev_probe(struct mlx5_common_device *cdev) RTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS, }; const char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx); - uint16_t rdmw_wqe_size; int ret; if (rte_eal_process_type() != RTE_PROC_PRIMARY) { @@ -907,20 +982,17 @@ mlx5_crypto_dev_probe(struct mlx5_common_device *cdev) return -1; } priv->keytag = rte_cpu_to_be_64(devarg_prms.keytag); - priv->max_segs_num = devarg_prms.max_segs_num; - priv->umr_wqe_size = sizeof(struct mlx5_wqe_umr_bsf_seg) + - sizeof(struct mlx5_wqe_cseg) + - sizeof(struct mlx5_wqe_umr_cseg) + - sizeof(struct mlx5_wqe_mkey_cseg) + - RTE_ALIGN(priv->max_segs_num, 4) * - sizeof(struct mlx5_wqe_dseg); - rdmw_wqe_size = sizeof(struct mlx5_rdma_write_wqe) + - sizeof(struct mlx5_wqe_dseg) * - (priv->max_segs_num <= 2 ? 2 : 2 + - RTE_ALIGN(priv->max_segs_num - 2, 4)); - priv->wqe_set_size = priv->umr_wqe_size + rdmw_wqe_size; - priv->umr_wqe_stride = priv->umr_wqe_size / MLX5_SEND_WQE_BB; - priv->max_rdmar_ds = rdmw_wqe_size / sizeof(struct mlx5_wqe_dseg); + ret = mlx5_crypto_configure_wqe_size(priv, + cdev->config.hca_attr.max_wqe_sz_sq, devarg_prms.max_segs_num); + if (ret) { + mlx5_crypto_uar_release(priv); + rte_cryptodev_pmd_destroy(priv->crypto_dev); + return -1; + } + DRV_LOG(INFO, "Max number of segments: %u.", + (unsigned int)RTE_MIN( + MLX5_CRYPTO_KLM_SEGS_NUM(priv->umr_wqe_size), + (uint16_t)(priv->max_rdmar_ds - 2))); pthread_mutex_lock(&priv_list_lock); TAILQ_INSERT_TAIL(&mlx5_crypto_priv_list, priv, next); pthread_mutex_unlock(&priv_list_lock); diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index 69cef81d77..33f244aaf3 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -16,6 +16,13 @@ #define MLX5_CRYPTO_DEK_HTABLE_SZ (1 << 11) #define MLX5_CRYPTO_KEY_LENGTH 80 +#define MLX5_CRYPTO_UMR_WQE_STATIC_SIZE (sizeof(struct mlx5_wqe_cseg) +\ + sizeof(struct mlx5_wqe_umr_cseg) +\ + sizeof(struct mlx5_wqe_mkey_cseg) +\ + sizeof(struct mlx5_wqe_umr_bsf_seg)) +#define MLX5_CRYPTO_KLM_SEGS_NUM(umr_wqe_sz) ((umr_wqe_sz -\ + MLX5_CRYPTO_UMR_WQE_STATIC_SIZE) /\ + MLX5_WSEG_SIZE) struct mlx5_crypto_priv { TAILQ_ENTRY(mlx5_crypto_priv) next; @@ -23,7 +30,6 @@ struct mlx5_crypto_priv { struct rte_cryptodev *crypto_dev; void *uar; /* User Access Region. */ volatile uint64_t *uar_addr; - uint32_t max_segs_num; /* Maximum supported data segs. */ struct mlx5_hlist *dek_hlist; /* Dek hash list. */ struct rte_cryptodev_config dev_config; struct mlx5_devx_obj *login_obj; diff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c index 50c966a022..4491f1c98a 100644 --- a/drivers/regex/mlx5/mlx5_regex_control.c +++ b/drivers/regex/mlx5/mlx5_regex_control.c @@ -150,8 +150,8 @@ regex_ctrl_create_hw_qp(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, qp_obj->qpn = q_ind; qp_obj->ci = 0; qp_obj->pi = 0; - attr.rq_size = 0; - attr.sq_size = RTE_BIT32(MLX5_REGEX_WQE_LOG_NUM(priv->has_umr, + attr.num_of_receive_wqes = 0; + attr.num_of_send_wqbbs = RTE_BIT32(MLX5_REGEX_WQE_LOG_NUM(priv->has_umr, log_nb_desc)); attr.mmo = priv->mmo_regex_qp_cap; ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp_obj->qp_obj, diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c index 042d22777f..759d7633c9 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c @@ -608,9 +608,9 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n, } attr.uar_index = priv->uar->page_id; attr.cqn = eqp->cq.cq_obj.cq->id; - attr.rq_size = RTE_BIT32(log_desc_n); + attr.num_of_receive_wqes = RTE_BIT32(log_desc_n); attr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE); - attr.sq_size = 0; /* No need SQ. */ + attr.num_of_send_wqbbs = 0; /* No need SQ. */ attr.ts_format = mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format); ret = mlx5_devx_qp_create(priv->cdev->ctx, &(eqp->sw_qp), log_desc_n, From patchwork Thu Nov 4 12:49:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raja Zidane X-Patchwork-Id: 103766 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 12F32A0548; Thu, 4 Nov 2021 13:50:29 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A10B742740; Thu, 4 Nov 2021 13:50:04 +0100 (CET) Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2068.outbound.protection.outlook.com [40.107.92.68]) by mails.dpdk.org (Postfix) with ESMTP id C6FD54271B for ; Thu, 4 Nov 2021 13:50:02 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CEtyzyCt6OKv3xVXNuILkXq5e10s4f/54sFjw1XrqdV5HENEdYZ8VsHlebBCCOH4c7nXnXBChIlS6t01q4sSbHW6+s0k2l27VjdFCox1naYThU39Dat/XtsiyHzceK1b4R/HAaJyJCrylh9Y+TvtcMdV6UjXjIoLv+mOXwExteOqo0gF00unVVe/xKxktgfArmgLzMDD7BGz3SZP2lr44KtFbD8FwljRaZuiWmKbQsNjaj5I08o6YEXfC8Qw+mVgW/0hKQBihhCB3CydsiJh4QCKGkIyuRvgc25LUyzqRagbWRc+2IaJXWkUOszj/QjnTNLtOg/v8oc+arZsiVoU/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=XrUsgZM8b2y/auhjIPSQEdN7+T5GfgEO08JbxTibM9w=; b=jDvXUpC7i69BZjTyar3q95OPyKDmHS90WfVu10izVoRm+yM9z6AdsvWcxxpgbyJX3D2oqVTiXN4hSdlTLY/Q6L58jcjPtnpocWyLADs71eGSKPpLP1gQrmJGv3Gi/uP0daCLIwi22Tuy/r//sOqG2LvtlleT+yeDz/L7osV6+P35l+KB4ROk2oqC4inixXR/ky25jIp8exU427HlR6OweISVydrGuLES5im48YB3xA0C3u2GQ7RxWSpVMaM2uauenSQYTjvDoZa+wSBVgGyLFUDz44lzARF6SmShFqa/64od7zCrh3q+olat/Aee2QDwNSmc2eThcoMuwI3+BolghQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XrUsgZM8b2y/auhjIPSQEdN7+T5GfgEO08JbxTibM9w=; b=M2CEqvcAlUQ6x96tsSzJNHhw2/F79g6zXdbx5szClb9lyyf5sccnoMPc9q69paU087rjYKk5KcO0Img3CPz2PAHK2r/+knciYEjNdMDDCp/X1uTX5u6CiVmJC+wAjBw+/4DY4Q1Arb5/V0KjXjGUt9Qz7q7NMeaua9W5O03bHojF4X0v9N2NFGZBrb3hN6CG/YE+riIwHdyvq/GLs9PKj4VXNcNPVcSYn3xebJTpIAJwhnqMERJAdPznk0TQt3RY84BMzK41upbySpaML1zTZDZlhQhU+eSOlwjwxTnD/WZsP8oqtmJm9rd60oPBMgiypUN3ymGx5WQAjaBKWaskzQ== Received: from BN9PR03CA0391.namprd03.prod.outlook.com (2603:10b6:408:111::6) by BL1PR12MB5189.namprd12.prod.outlook.com (2603:10b6:208:308::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.15; Thu, 4 Nov 2021 12:50:01 +0000 Received: from BN8NAM11FT045.eop-nam11.prod.protection.outlook.com (2603:10b6:408:111:cafe::2b) by BN9PR03CA0391.outlook.office365.com (2603:10b6:408:111::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.11 via Frontend Transport; Thu, 4 Nov 2021 12:50:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT045.mail.protection.outlook.com (10.13.177.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Thu, 4 Nov 2021 12:50:01 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 4 Nov 2021 12:49:56 +0000 From: Raja Zidane To: CC: Matan Azrad Date: Thu, 4 Nov 2021 12:49:29 +0000 Message-ID: <20211104124929.24899-5-rzidane@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211104124929.24899-1-rzidane@nvidia.com> References: <20211104124929.24899-1-rzidane@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4550dc57-4106-42ee-9782-08d99f919d93 X-MS-TrafficTypeDiagnostic: BL1PR12MB5189: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2582; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZAEhptgFdA2MhzLNaN8OWG14+kMC9mw5RiC+k31vu77WWZ6Ulv3jqWEMQaJIJ8T1v+6nwap64l0D9pZD4lmvRFZajYA8Wc1ufxUMfplJqukcyqN5fpk4iE2gtVdT+FCEWX2DM7ZOcWJt9h4u6iktFmlixIZO2ooG+L+CNXSXl76mLxsSnQSBXlZysOrTTBIvKUgDQxRCObFVijjKJfdgVaxnVY3/8a/At3PT0lvNwMnEXNY5FqugOt9Sxhuj/1HACisyONU3hJgO8/7Dk6MngOruwSoIWNp1FOW2O0RpnqeRN8rceF06ayDG4mewB7KI/J3ELm5MzNvAwPJ21yTNWcPC8JMI2Sj/sQEM+PvjUx1gveTwWwW1eJfnFsT0pyAzImKJd2C2hgjPs/+8PB2jyV0VABYLwIQqxqQ56fg9zWOhY/tSILA7k/z8CWp+jeZ2KRCfcw1pz3BR/ChIS+VNundBTR4h4yhL6TyeDhizhOUKez9++JnCkb94s4avztm9WFHzSGmn8gZzKWO9XmXX/V/yJpCKSvaRstazVQtHipv4juEpsxqTY960P7/xUGKnHmEQdDzX/Ct8x5jt5h5HUpM+7rYNq5A4H2lID7PGW3PXRSX+3YnUTx8cW1IVYxY1gJbL9CzH2tMrpDd+XUz9z5zSbE2NY2BlyvZvSvSxIpystlYAAxGvZQEFIr1TRdSR3tpk0G1HSJCiZzaMGb5kVA== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(4326008)(86362001)(55016002)(16526019)(8676002)(70206006)(2906002)(6666004)(47076005)(8936002)(508600001)(186003)(336012)(70586007)(5660300002)(7636003)(36860700001)(82310400003)(1076003)(426003)(107886003)(6286002)(356005)(6916009)(2616005)(26005)(83380400001)(36756003)(316002)(7696005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 12:50:01.0566 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4550dc57-4106-42ee-9782-08d99f919d93 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5189 Subject: [dpdk-dev] [PATCH 4/4] common/mlx5: fix RQ size configuration in QP create X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The number of WQEBBs was provided to QP create, and QP size was calculated by multiplying the number of WQEBBs by 64, which is the send WQE size. When creating RQ in the QP (i.e., vdpa driver), the queue size was bigger because the receive WQE size is 16. Provide queue size to QP create instead of the number of WQEBBs. Fixes: f9213ab12cf9 ("common/mlx5: share DevX queue pair operations") Signed-off-by: Raja Zidane Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_common_devx.c | 9 ++++----- drivers/common/mlx5/mlx5_common_devx.h | 2 +- drivers/compress/mlx5/mlx5_compress.c | 5 +++-- drivers/crypto/mlx5/mlx5_crypto.c | 5 +++-- drivers/regex/mlx5/mlx5_regex_control.c | 4 ++-- drivers/vdpa/mlx5/mlx5_vdpa_event.c | 5 +++-- 6 files changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/common/mlx5/mlx5_common_devx.c b/drivers/common/mlx5/mlx5_common_devx.c index 0e58308b0b..cd491012a0 100644 --- a/drivers/common/mlx5/mlx5_common_devx.c +++ b/drivers/common/mlx5/mlx5_common_devx.c @@ -305,8 +305,8 @@ mlx5_devx_qp_destroy(struct mlx5_devx_qp *qp) * Context returned from mlx5 open_device() glue function. * @param[in/out] qp_obj * Pointer to QP to create. - * @param[in] log_wqbb_n - * Log of number of WQBBs in queue. + * @param[in] queue_size + * Size of queue to create. * @param[in] attr * Pointer to QP attributes structure. * @param[in] socket @@ -316,7 +316,7 @@ mlx5_devx_qp_destroy(struct mlx5_devx_qp *qp) * 0 on success, a negative errno value otherwise and rte_errno is set. */ int -mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, uint32_t log_wqbb_n, +mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, uint32_t queue_size, struct mlx5_devx_qp_attr *attr, int socket) { struct mlx5_devx_obj *qp = NULL; @@ -324,7 +324,6 @@ mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, uint32_t log_wqbb_n, void *umem_buf = NULL; size_t alignment = MLX5_WQE_BUF_ALIGNMENT; uint32_t umem_size, umem_dbrec; - uint32_t num_of_wqbbs = RTE_BIT32(log_wqbb_n); int ret; if (alignment == (size_t)-1) { @@ -333,7 +332,7 @@ mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, uint32_t log_wqbb_n, return -rte_errno; } /* Allocate memory buffer for WQEs and doorbell record. */ - umem_size = MLX5_WQE_SIZE * num_of_wqbbs; + umem_size = queue_size; umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); umem_size += MLX5_DBR_SIZE; umem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size, diff --git a/drivers/common/mlx5/mlx5_common_devx.h b/drivers/common/mlx5/mlx5_common_devx.h index 7138bd7914..14e90ddb38 100644 --- a/drivers/common/mlx5/mlx5_common_devx.h +++ b/drivers/common/mlx5/mlx5_common_devx.h @@ -76,7 +76,7 @@ void mlx5_devx_qp_destroy(struct mlx5_devx_qp *qp); __rte_internal int mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, - uint32_t log_wqbb_n, + uint32_t queue_size, struct mlx5_devx_qp_attr *attr, int socket); __rte_internal diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 6bb750781f..e7344c9d92 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -247,8 +247,9 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, qp_attr.num_of_send_wqbbs = RTE_BIT32(log_ops_n); qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp && priv->mmo_dma_qp; - ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp, log_ops_n, &qp_attr, - socket_id); + ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp, + qp_attr.num_of_send_wqbbs * + MLX5_WQE_SIZE, &qp_attr, socket_id); if (ret != 0) { DRV_LOG(ERR, "Failed to create QP."); goto err; diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index 7931a84070..56941a5c1c 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -641,8 +641,9 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, attr.num_of_send_wqbbs = RTE_BIT32(log_wqbb_n); attr.ts_format = mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format); - ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp_obj, log_wqbb_n, - &attr, socket_id); + ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp_obj, + attr.num_of_send_wqbbs * MLX5_WQE_SIZE, + &attr, socket_id); if (ret) { DRV_LOG(ERR, "Failed to create QP."); goto error; diff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c index 4491f1c98a..2c1d933bbf 100644 --- a/drivers/regex/mlx5/mlx5_regex_control.c +++ b/drivers/regex/mlx5/mlx5_regex_control.c @@ -155,8 +155,8 @@ regex_ctrl_create_hw_qp(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, log_nb_desc)); attr.mmo = priv->mmo_regex_qp_cap; ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp_obj->qp_obj, - MLX5_REGEX_WQE_LOG_NUM(priv->has_umr, log_nb_desc), - &attr, SOCKET_ID_ANY); + attr.num_of_send_wqbbs * MLX5_WQE_SIZE, &attr, + SOCKET_ID_ANY); if (ret) { DRV_LOG(ERR, "Can't create QP object."); rte_errno = ENOMEM; diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c index 759d7633c9..3590afd52c 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c @@ -613,8 +613,9 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n, attr.num_of_send_wqbbs = 0; /* No need SQ. */ attr.ts_format = mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format); - ret = mlx5_devx_qp_create(priv->cdev->ctx, &(eqp->sw_qp), log_desc_n, - &attr, SOCKET_ID_ANY); + ret = mlx5_devx_qp_create(priv->cdev->ctx, &(eqp->sw_qp), + attr.num_of_receive_wqes * + MLX5_WSEG_SIZE, &attr, SOCKET_ID_ANY); if (ret) { DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno); goto error;