From patchwork Mon Jan 17 02:43:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 105885 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 19E46A034F; Mon, 17 Jan 2022 03:43:04 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 23D32411CB; Mon, 17 Jan 2022 03:42:48 +0100 (CET) Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by mails.dpdk.org (Postfix) with ESMTP id EC300410F7 for ; Mon, 17 Jan 2022 03:42:43 +0100 (CET) Received: from dggeme756-chm.china.huawei.com (unknown [172.30.72.57]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4Jcbh32bK6z1FCcd; Mon, 17 Jan 2022 10:38:59 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.21; Mon, 17 Jan 2022 10:42:41 +0800 From: "Min Hu (Connor)" To: CC: , Subject: [PATCH 1/3] net/hns3: fix Rx/Tx when fast path operation introduced Date: Mon, 17 Jan 2022 10:43:00 +0800 Message-ID: <20220117024302.16006-2-humin29@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220117024302.16006-1-humin29@huawei.com> References: <20220117024302.16006-1-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggeme756-chm.china.huawei.com (10.3.19.102) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When fast path operation is introduced, the Rx/Tx function is done by object 'rte_eth_fp_ops'. So 'rte_eth_fp_ops' should be updated if 'fast-path functions' need to be changed, such as PMD receive function, prepare function and so on. This patch fixed receiving packets bug when fast path operation is introduced. Fixes: bba63669831 ("net/hns3: support Rx/Tx and related operations") Fixes: 168b7d79dada ("net/hns3: support set link up/down for PF") Cc: stable@dpdk.org Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_mp.c | 7 ++----- drivers/net/hns3/hns3_rxtx.c | 28 +++++++++++++++++++++++++++- 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/net/hns3/hns3_mp.c b/drivers/net/hns3/hns3_mp.c index 999b407f7d..e74ddea195 100644 --- a/drivers/net/hns3/hns3_mp.c +++ b/drivers/net/hns3/hns3_mp.c @@ -74,7 +74,6 @@ mp_secondary_handle(const struct rte_mp_msg *mp_msg, const void *peer) struct hns3_mp_param *res = (struct hns3_mp_param *)mp_res.param; const struct hns3_mp_param *param = (const struct hns3_mp_param *)mp_msg->param; - eth_tx_prep_t prep = NULL; struct rte_eth_dev *dev; int ret; @@ -98,14 +97,12 @@ mp_secondary_handle(const struct rte_mp_msg *mp_msg, const void *peer) case HNS3_MP_REQ_START_TX: PMD_INIT_LOG(INFO, "port %u starting Tx datapath", dev->data->port_id); - dev->tx_pkt_burst = hns3_get_tx_function(dev, &prep); - dev->tx_pkt_prepare = prep; + hns3_start_tx_datapath(dev); break; case HNS3_MP_REQ_STOP_TX: PMD_INIT_LOG(INFO, "port %u stopping Tx datapath", dev->data->port_id); - dev->tx_pkt_burst = hns3_dummy_rxtx_burst; - dev->tx_pkt_prepare = NULL; + hns3_stop_tx_datapath(dev); break; default: rte_errno = EINVAL; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index d240e36e6a..c86aeb2366 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -4408,7 +4408,21 @@ hns3_trace_rxtx_function(struct rte_eth_dev *dev) rx_mode.info, tx_mode.info); } -void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) +static void +hns3_eth_dev_fp_ops_config(const struct rte_eth_dev *dev) +{ + struct rte_eth_fp_ops *fpo = rte_eth_fp_ops; + uint16_t port_id = dev->data->port_id; + + fpo[port_id].rx_pkt_burst = dev->rx_pkt_burst; + fpo[port_id].tx_pkt_burst = dev->tx_pkt_burst; + fpo[port_id].tx_pkt_prepare = dev->tx_pkt_prepare; + fpo[port_id].rx_descriptor_status = dev->rx_descriptor_status; + fpo[port_id].tx_descriptor_status = dev->tx_descriptor_status; +} + +void +hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) { struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); struct hns3_adapter *hns = eth_dev->data->dev_private; @@ -4429,6 +4443,8 @@ void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst; eth_dev->tx_pkt_prepare = NULL; } + + hns3_eth_dev_fp_ops_config(eth_dev); } void @@ -4729,6 +4745,11 @@ hns3_stop_tx_datapath(struct rte_eth_dev *dev) { dev->tx_pkt_burst = hns3_dummy_rxtx_burst; dev->tx_pkt_prepare = NULL; + hns3_eth_dev_fp_ops_config(dev); + + if (rte_eal_process_type() == RTE_PROC_SECONDARY) + return; + rte_wmb(); /* Disable tx datapath on secondary process. */ hns3_mp_req_stop_tx(dev); @@ -4743,5 +4764,10 @@ hns3_start_tx_datapath(struct rte_eth_dev *dev) dev->tx_pkt_burst = hns3_get_tx_function(dev, &prep); dev->tx_pkt_prepare = prep; + hns3_eth_dev_fp_ops_config(dev); + + if (rte_eal_process_type() == RTE_PROC_SECONDARY) + return; + hns3_mp_req_start_tx(dev); } From patchwork Mon Jan 17 02:43:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 105882 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EBB31A034F; Mon, 17 Jan 2022 03:42:45 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4F8BB40DDA; Mon, 17 Jan 2022 03:42:45 +0100 (CET) Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) by mails.dpdk.org (Postfix) with ESMTP id DF1CC4067B for ; Mon, 17 Jan 2022 03:42:43 +0100 (CET) Received: from dggeme756-chm.china.huawei.com (unknown [172.30.72.56]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4Jcbj62M2rz5HpD; Mon, 17 Jan 2022 10:39:54 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.21; Mon, 17 Jan 2022 10:42:41 +0800 From: "Min Hu (Connor)" To: CC: , Subject: [PATCH 2/3] net/hns3: fix mailbox wait time uninitialization Date: Mon, 17 Jan 2022 10:43:01 +0800 Message-ID: <20220117024302.16006-3-humin29@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220117024302.16006-1-humin29@huawei.com> References: <20220117024302.16006-1-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggeme756-chm.china.huawei.com (10.3.19.102) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Huisong Li The mailbox wait time can be specified at runtime. But the variable that controls this time are not initialized when the variable isn't designated or is specified as an invalid value, which will fail to initialize device in the case where no device is bound to initialize the device. Fixes: 2fc3e696a7f1 ("net/hns3: add runtime config for mailbox limit time") Cc: stable@dpdk.org Signed-off-by: Huisong Li --- drivers/net/hns3/hns3_common.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/hns3/hns3_common.c b/drivers/net/hns3/hns3_common.c index 0bb552ea3e..78158401f2 100644 --- a/drivers/net/hns3/hns3_common.c +++ b/drivers/net/hns3/hns3_common.c @@ -216,7 +216,7 @@ hns3_parse_mbx_time_limit(const char *key, const char *value, void *extra_args) /* * 500ms is empirical value in process of mailbox communication. If - * the delay value is set to one lower thanthe empirical value, mailbox + * the delay value is set to one lower than the empirical value, mailbox * communication may fail. */ if (val > HNS3_MBX_DEF_TIME_LIMIT_MS && val <= UINT16_MAX) @@ -236,6 +236,12 @@ hns3_parse_devargs(struct rte_eth_dev *dev) uint64_t dev_caps_mask = 0; struct rte_kvargs *kvlist; + /* Set default value of runtime config parameters. */ + hns->rx_func_hint = HNS3_IO_FUNC_HINT_NONE; + hns->tx_func_hint = HNS3_IO_FUNC_HINT_NONE; + hns->dev_caps_mask = 0; + hns->mbx_time_limit_ms = HNS3_MBX_DEF_TIME_LIMIT_MS; + if (dev->device->devargs == NULL) return; From patchwork Mon Jan 17 02:43:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 105884 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9CF2FA034F; Mon, 17 Jan 2022 03:42:57 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 251DC411AB; Mon, 17 Jan 2022 03:42:47 +0100 (CET) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id E37FD40DDA for ; Mon, 17 Jan 2022 03:42:43 +0100 (CET) Received: from dggeme756-chm.china.huawei.com (unknown [172.30.72.56]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4JcblV5QkDzbk0L; Mon, 17 Jan 2022 10:41:58 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.21; Mon, 17 Jan 2022 10:42:41 +0800 From: "Min Hu (Connor)" To: CC: , Subject: [PATCH 3/3] net/hns3: fix vector burst unsupported when PTP enable Date: Mon, 17 Jan 2022 10:43:02 +0800 Message-ID: <20220117024302.16006-4-humin29@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220117024302.16006-1-humin29@huawei.com> References: <20220117024302.16006-1-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggeme756-chm.china.huawei.com (10.3.19.102) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org If hardware supports IEEE 1588 PTP, PTP capability will be set. Currently, vec and sve burst is unsupported when PTP capability is set. For sake of Rx/Tx performance, IEEE 1588 PTP is not supported in sve or vec burst mode. When enabling IEEE 1588 PTP, Rx/Tx burst mode should be simple or common. Rx/Tx burst mode could be set like this, for example: -a 0000:35:00.0,rx_func_hint=common,tx_func_hint=common This patch supports vec and sve burst when PTP is disabled. And only support simple or common burst When PTP is enabled. Fixes: 38b539d96eb6 ("net/hns3: support IEEE 1588 PTP") Cc: stable@dpdk.org Signed-off-by: Min Hu (Connor) --- doc/guides/nics/hns3.rst | 5 +++++ drivers/net/hns3/hns3_ethdev.c | 8 +------- drivers/net/hns3/hns3_ptp.c | 1 + drivers/net/hns3/hns3_rxtx.c | 29 +++++++++++++++++------------ drivers/net/hns3/hns3_rxtx_vec.c | 20 ++++++++++++-------- 5 files changed, 36 insertions(+), 27 deletions(-) diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst index 5f68a10ecf..791c9cc2ed 100644 --- a/doc/guides/nics/hns3.rst +++ b/doc/guides/nics/hns3.rst @@ -290,5 +290,10 @@ Currently, we only support VF device driven by DPDK driver when PF is driven by kernel mode hns3 ethdev driver. VF is not supported when PF is driven by DPDK driver. +For sake of Rx/Tx performance, IEEE 1588 is not supported when using vec or +sve burst function. When enabling IEEE 1588, Rx/Tx burst mode should be +simple or common. It is recommended that enable IEEE 1588 before ethdev +start. In this way, the correct Rx/Tx burst function can be selected. + Build with ICC is not supported yet. X86-32, Power8, ARMv7 and BSD are not supported yet. diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 3b897492d3..ef13d31d19 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -227,17 +227,11 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) return ret; } -static bool -hns3_is_1588_event_type(uint32_t event_type) -{ - return (event_type == HNS3_VECTOR0_EVENT_PTP); -} - static void hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr) { if (event_type == HNS3_VECTOR0_EVENT_RST || - hns3_is_1588_event_type(event_type)) + event_type == HNS3_VECTOR0_EVENT_PTP) hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr); else if (event_type == HNS3_VECTOR0_EVENT_MBX) hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); diff --git a/drivers/net/hns3/hns3_ptp.c b/drivers/net/hns3/hns3_ptp.c index 9a829d7011..1442241a4e 100644 --- a/drivers/net/hns3/hns3_ptp.c +++ b/drivers/net/hns3/hns3_ptp.c @@ -125,6 +125,7 @@ hns3_timesync_enable(struct rte_eth_dev *dev) if (pf->ptp_enable) return 0; + hns3_warn(hw, "note: please ensure Rx/Tx burst mode is simple or common when enabling PTP!"); rte_spinlock_lock(&hw->lock); ret = hns3_timesync_configure(hns, true); diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index c86aeb2366..c43131cac6 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2388,14 +2388,14 @@ hns3_rx_alloc_buffer(struct hns3_rx_queue *rxq) return rte_mbuf_raw_alloc(rxq->mb_pool); } -static inline void +static void hns3_rx_ptp_timestamp_handle(struct hns3_rx_queue *rxq, struct rte_mbuf *mbuf, - volatile struct hns3_desc *rxd) + uint64_t timestamp) { struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(rxq->hns); - uint64_t timestamp = rte_le_to_cpu_64(rxd->timestamp); - mbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP | RTE_MBUF_F_RX_IEEE1588_TMST; + mbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP | + RTE_MBUF_F_RX_IEEE1588_TMST; if (hns3_timestamp_rx_dynflag > 0) { *RTE_MBUF_DYNFIELD(mbuf, hns3_timestamp_dynfield_offset, rte_mbuf_timestamp_t *) = timestamp; @@ -2469,7 +2469,8 @@ hns3_recv_pkts_simple(void *rx_queue, rxe->mbuf = nmb; if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) - hns3_rx_ptp_timestamp_handle(rxq, rxm, rxdp); + hns3_rx_ptp_timestamp_handle(rxq, rxm, + rte_le_to_cpu_64(rxdp->timestamp)); dma_addr = rte_mbuf_data_iova_default(nmb); rxdp->addr = rte_cpu_to_le_64(dma_addr); @@ -2540,6 +2541,7 @@ hns3_recv_scattered_pkts(void *rx_queue, struct rte_mbuf *rxm; struct rte_eth_dev *dev; uint32_t bd_base_info; + uint64_t timestamp; uint32_t l234_info; uint32_t gro_size; uint32_t ol_info; @@ -2649,6 +2651,9 @@ hns3_recv_scattered_pkts(void *rx_queue, rxm = rxe->mbuf; rxe->mbuf = nmb; + if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) + timestamp = rte_le_to_cpu_64(rxdp->timestamp); + dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb)); rxdp->rx.bd_base_info = 0; rxdp->addr = dma_addr; @@ -2671,7 +2676,7 @@ hns3_recv_scattered_pkts(void *rx_queue, } if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) - hns3_rx_ptp_timestamp_handle(rxq, first_seg, rxdp); + hns3_rx_ptp_timestamp_handle(rxq, first_seg, timestamp); /* * The last buffer of the received packet. packet len from @@ -4044,7 +4049,7 @@ static inline void hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) { #define PER_LOOP_NUM 4 - const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B); + uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B); uint64_t dma_addr; uint32_t i; @@ -4055,6 +4060,8 @@ hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) txdp->tx.paylen_fd_dop_ol4cs = 0; txdp->tx.type_cs_vlan_tso_len = 0; txdp->tx.ol_type_vlan_len_msec = 0; + if (unlikely((*pkts)->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)) + bd_flag |= BIT(HNS3_TXD_TSYN_B); txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag); } } @@ -4062,7 +4069,7 @@ hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) static inline void hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) { - const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B); + uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B); uint64_t dma_addr; dma_addr = rte_mbuf_data_iova(*pkts); @@ -4071,6 +4078,8 @@ hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) txdp->tx.paylen_fd_dop_ol4cs = 0; txdp->tx.type_cs_vlan_tso_len = 0; txdp->tx.ol_type_vlan_len_msec = 0; + if (unlikely((*pkts)->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)) + bd_flag |= BIT(HNS3_TXD_TSYN_B); txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag); } @@ -4312,10 +4321,6 @@ hns3_tx_check_simple_support(struct rte_eth_dev *dev) { uint64_t offloads = dev->data->dev_conf.txmode.offloads; - struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); - if (hns3_dev_get_support(hw, PTP)) - return false; - return (offloads == (offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE)); } diff --git a/drivers/net/hns3/hns3_rxtx_vec.c b/drivers/net/hns3/hns3_rxtx_vec.c index 455110361a..73f0ab6bc8 100644 --- a/drivers/net/hns3/hns3_rxtx_vec.c +++ b/drivers/net/hns3/hns3_rxtx_vec.c @@ -17,15 +17,17 @@ int hns3_tx_check_vec_support(struct rte_eth_dev *dev) { struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode; - - struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); - if (hns3_dev_get_support(hw, PTP)) - return -ENOTSUP; + struct hns3_adapter *hns = dev->data->dev_private; + struct hns3_pf *pf = &hns->pf; /* Only support RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE */ if (txmode->offloads != RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) return -ENOTSUP; + /* Vec is not supported when PTP enabled */ + if (pf->ptp_enable) + return -ENOTSUP; + return 0; } @@ -232,10 +234,8 @@ hns3_rx_check_vec_support(struct rte_eth_dev *dev) struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; uint64_t offloads_mask = RTE_ETH_RX_OFFLOAD_TCP_LRO | RTE_ETH_RX_OFFLOAD_VLAN; - - struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); - if (hns3_dev_get_support(hw, PTP)) - return -ENOTSUP; + struct hns3_adapter *hns = dev->data->dev_private; + struct hns3_pf *pf = &hns->pf; if (dev->data->scattered_rx) return -ENOTSUP; @@ -249,5 +249,9 @@ hns3_rx_check_vec_support(struct rte_eth_dev *dev) if (hns3_rxq_iterate(dev, hns3_rxq_vec_check, NULL) != 0) return -ENOTSUP; + /* Vec is not supported when PTP enabled */ + if (pf->ptp_enable) + return -ENOTSUP; + return 0; }