From patchwork Wed Jan 26 15:57:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Yuying" X-Patchwork-Id: 106557 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1ED95A04A7; Wed, 26 Jan 2022 08:56:44 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A6EC642705; Wed, 26 Jan 2022 08:56:43 +0100 (CET) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 6774E4069D for ; Wed, 26 Jan 2022 08:56:41 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643183801; x=1674719801; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tc/XNhAIbJk6YAOxKh903Agj+HtNmwP1AzRHxS9CevI=; b=VgpSAJMrBfCuqgdMSMrsjXYfDnNJKUQFrz0v3i6p0xo7XjvZa1AXmHZb sbQcUlEpe7W6TcKn8Nju0Q98tohFyNy5FR36m/du9NJOw2cFPGXnkAtqA efxXLoijhM/4NEcaZkvLlmXHKLWL8vcJZqkHlCtSI9Ebpz1WxkN+lr3Bv auOFnJUbNcZfdxQRMSmrs1PzUblxNOAgi42Z2VEVny6E4Kois1Oliks4X 05tvDB+xQArOTC+LW1drpdsoOxg5SS+GfIiVjQIVxWCQtE7AqBUxc5iFV 6jYY76FdAi3CTmO9zLyCj6eutNGOImyLcGYmJIG0xmDg5XgHmOCEh2q5Q g==; X-IronPort-AV: E=McAfee;i="6200,9189,10238"; a="246279257" X-IronPort-AV: E=Sophos;i="5.88,317,1635231600"; d="scan'208";a="246279257" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2022 23:56:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,317,1635231600"; d="scan'208";a="563336420" Received: from dpdk-yuyingzh-icelake.sh.intel.com ([10.67.116.254]) by orsmga001.jf.intel.com with ESMTP; 25 Jan 2022 23:56:39 -0800 From: Yuying Zhang To: dev@dpdk.org, qi.z.zhang@intel.com Cc: Yuying Zhang Subject: [PATCH v3 1/2] net/ice/base: add profile validation on switch filter Date: Wed, 26 Jan 2022 15:57:09 +0000 Message-Id: <20220126155710.911525-1-yuying.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Profile type was determined without validation when getting switch field vector bitmap. It caused error when associating profile id with given recipe if no lookup elements were given. Add profile validation to check if the profile is existing before getting bitmap. Signed-off-by: Yuying Zhang Acked-by: Qi Zhang --- drivers/net/ice/base/ice_flex_pipe.c | 11 +++++------ drivers/net/ice/base/ice_flex_type.h | 1 + drivers/net/ice/base/ice_protocol_type.h | 1 + drivers/net/ice/base/ice_switch.c | 1 + 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 395787806b..f6a29f87c5 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -1785,8 +1785,12 @@ static enum ice_prof_type ice_get_sw_prof_type(struct ice_hw *hw, struct ice_fv *fv) { u16 i; + bool valid_prof = false; for (i = 0; i < hw->blk[ICE_BLK_SW].es.fvw; i++) { + if (fv->ew[i].off != ICE_NAN_OFFSET) + valid_prof = true; + /* UDP tunnel will have UDP_OF protocol ID and VNI offset */ if (fv->ew[i].prot_id == (u8)ICE_PROT_UDP_OF && fv->ew[i].off == ICE_VNI_OFFSET) @@ -1801,7 +1805,7 @@ ice_get_sw_prof_type(struct ice_hw *hw, struct ice_fv *fv) return ICE_PROF_TUN_PPPOE; } - return ICE_PROF_NON_TUN; + return valid_prof ? ICE_PROF_NON_TUN : ICE_PROF_INVALID; } /** @@ -1818,11 +1822,6 @@ ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type req_profs, struct ice_seg *ice_seg; struct ice_fv *fv; - if (req_profs == ICE_PROF_ALL) { - ice_bitmap_set(bm, 0, ICE_MAX_NUM_PROFILES); - return; - } - ice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM); ice_zero_bitmap(bm, ICE_MAX_NUM_PROFILES); ice_seg = hw->seg; diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h index 59eeca0a30..09a02fe9ac 100644 --- a/drivers/net/ice/base/ice_flex_type.h +++ b/drivers/net/ice/base/ice_flex_type.h @@ -1003,6 +1003,7 @@ struct ice_chs_chg { #define ICE_FLOW_PTYPE_MAX ICE_XLT1_CNT enum ice_prof_type { + ICE_PROF_INVALID = 0x0, ICE_PROF_NON_TUN = 0x1, ICE_PROF_TUN_UDP = 0x2, ICE_PROF_TUN_GRE = 0x4, diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index cef8354f77..0e6e5990be 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -191,6 +191,7 @@ enum ice_prot_id { #define ICE_VNI_OFFSET 12 /* offset of VNI from ICE_PROT_UDP_OF */ +#define ICE_NAN_OFFSET 511 #define ICE_MAC_OFOS_HW 1 #define ICE_MAC_IL_HW 4 #define ICE_ETYPE_OL_HW 9 diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 1fee790c25..d4cc664ad7 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -7779,6 +7779,7 @@ ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo, bool ice_is_prof_rule(enum ice_sw_tunnel_type type) { switch (type) { + case ICE_SW_TUN_AND_NON_TUN: case ICE_SW_TUN_PROFID_IPV6_ESP: case ICE_SW_TUN_PROFID_IPV6_AH: case ICE_SW_TUN_PROFID_MAC_IPV6_L2TPV3: From patchwork Wed Jan 26 15:57:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Yuying" X-Patchwork-Id: 106558 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3622EA04A7; Wed, 26 Jan 2022 08:56:50 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BE42242715; Wed, 26 Jan 2022 08:56:45 +0100 (CET) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 99CE34069D for ; Wed, 26 Jan 2022 08:56:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643183803; x=1674719803; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DCLYbIRZ13oOv2BBoNFnAggWEsjiDGnangq+1DNwdK0=; b=DsjYZEZeqZPQbpq0B9UFXubjaUX6nbQ8hnAYe8tkcWooj/5zawfLHqRv Skh1edy4T6JRHRN2EuE3M1CcNi8pFE5RsBEZrh+jk8Qqr0ScsyfUQlDWK d3WT5gRsFy56JedRLOnJxcibUu1RVh5+3u2sq9ky9CGrDabqTX0e1qwG9 aAA/o6Hr7ZF1R8lYl3IGZR8trKERvXcakR7zGki3r9TzfgXkaHgV5jJer vYv9g0Y7samM8M90VQi/rx8Fs+5obYrUdPDq2pjSF4Y5+iEzAdV9GMIJ4 WevRgdYUZdEee31VanjBF+wAHhmEnORYbHsBI+PfcBkXuhC/NCyZHw9rz Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10238"; a="246279260" X-IronPort-AV: E=Sophos;i="5.88,317,1635231600"; d="scan'208";a="246279260" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2022 23:56:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,317,1635231600"; d="scan'208";a="563336431" Received: from dpdk-yuyingzh-icelake.sh.intel.com ([10.67.116.254]) by orsmga001.jf.intel.com with ESMTP; 25 Jan 2022 23:56:42 -0800 From: Yuying Zhang To: dev@dpdk.org, qi.z.zhang@intel.com Cc: Yuying Zhang Subject: [PATCH v3 2/2] net/ice: support drop any and steer all to queue Date: Wed, 26 Jan 2022 15:57:10 +0000 Message-Id: <20220126155710.911525-2-yuying.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220126155710.911525-1-yuying.zhang@intel.com> References: <20220126155710.911525-1-yuying.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch supports drop any and steer all to queue in switch filter. Support new rte_flow pattern any to handle all packets. The usage is listed below. 1. drop any: flow create 0 ingress pattern any / end actions drop / end All packets received in port 0 will be dropped. 2. steer all to queue: flow create 0 ingress pattern any / end actions queue index 3 / end All packets received in port 0 will be steered to queue 3. Signed-off-by: Yuying Zhang Acked-by: Qi Zhang --- drivers/net/ice/ice_generic_flow.c | 6 ++++++ drivers/net/ice/ice_generic_flow.h | 3 +++ drivers/net/ice/ice_switch_filter.c | 6 ++++++ 3 files changed, 15 insertions(+) diff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c index 406a0a953f..53b1c0b69a 100644 --- a/drivers/net/ice/ice_generic_flow.c +++ b/drivers/net/ice/ice_generic_flow.c @@ -65,6 +65,11 @@ enum rte_flow_item_type pattern_empty[] = { RTE_FLOW_ITEM_TYPE_END, }; +enum rte_flow_item_type pattern_any[] = { + RTE_FLOW_ITEM_TYPE_ANY, + RTE_FLOW_ITEM_TYPE_END, +}; + /* raw */ enum rte_flow_item_type pattern_raw[] = { RTE_FLOW_ITEM_TYPE_RAW, @@ -2111,6 +2116,7 @@ struct ice_ptype_match { static struct ice_ptype_match ice_ptype_map[] = { {pattern_raw, ICE_PTYPE_IPV4_PAY}, + {pattern_any, ICE_PTYPE_IPV4_PAY}, {pattern_eth_ipv4, ICE_PTYPE_IPV4_PAY}, {pattern_eth_ipv4_udp, ICE_PTYPE_IPV4_UDP_PAY}, {pattern_eth_ipv4_tcp, ICE_PTYPE_IPV4_TCP_PAY}, diff --git a/drivers/net/ice/ice_generic_flow.h b/drivers/net/ice/ice_generic_flow.h index 1b030c0466..11f51a5c15 100644 --- a/drivers/net/ice/ice_generic_flow.h +++ b/drivers/net/ice/ice_generic_flow.h @@ -124,6 +124,9 @@ /* empty pattern */ extern enum rte_flow_item_type pattern_empty[]; +/* any pattern */ +extern enum rte_flow_item_type pattern_any[]; + /* raw pattern */ extern enum rte_flow_item_type pattern_raw[]; diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c index bd805d9606..36c9bffb73 100644 --- a/drivers/net/ice/ice_switch_filter.c +++ b/drivers/net/ice/ice_switch_filter.c @@ -206,6 +206,7 @@ static struct ice_flow_parser ice_switch_perm_parser; static struct ice_pattern_match_item ice_switch_pattern_dist_list[] = { + {pattern_any, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_ethertype, ICE_SW_INSET_ETHER, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_ethertype_vlan, ICE_SW_INSET_MAC_VLAN, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_ethertype_qinq, ICE_SW_INSET_MAC_QINQ, ICE_INSET_NONE, ICE_INSET_NONE}, @@ -289,6 +290,7 @@ ice_pattern_match_item ice_switch_pattern_dist_list[] = { static struct ice_pattern_match_item ice_switch_pattern_perm_list[] = { + {pattern_any, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_ethertype, ICE_SW_INSET_ETHER, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_ethertype_vlan, ICE_SW_INSET_MAC_VLAN, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_ethertype_qinq, ICE_SW_INSET_MAC_QINQ, ICE_INSET_NONE, ICE_INSET_NONE}, @@ -582,6 +584,10 @@ ice_switch_parse_pattern(const struct rte_flow_item pattern[], item_type = item->type; switch (item_type) { + case RTE_FLOW_ITEM_TYPE_ANY: + *tun_type = ICE_SW_TUN_AND_NON_TUN; + break; + case RTE_FLOW_ITEM_TYPE_ETH: eth_spec = item->spec; eth_mask = item->mask;