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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.234) by DM6NAM11FT035.mail.protection.outlook.com (10.13.172.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4930.15 via Frontend Transport; Wed, 26 Jan 2022 08:44:23 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 26 Jan 2022 08:44:22 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Wed, 26 Jan 2022 00:44:21 -0800 From: Sean Zhang To: , Olivier Matz CC: Subject: [v1 1/4] lib: add optional fields in GRE header Date: Wed, 26 Jan 2022 10:44:01 +0200 Message-ID: <20220126084404.40178-2-xiazhang@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220126084404.40178-1-xiazhang@nvidia.com> References: <20211230030817.15264-2-xiazhang@nvidia.com> <20220126084404.40178-1-xiazhang@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: drhqmail203.nvidia.com (10.126.190.182) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f2c942bd-0f65-458a-1615-08d9e0a80da1 X-MS-TrafficTypeDiagnostic: DM5PR12MB1386:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2150; 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SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(40470700004)(36840700001)(46966006)(426003)(6666004)(8676002)(6286002)(7696005)(86362001)(508600001)(336012)(47076005)(1076003)(356005)(26005)(316002)(55016003)(186003)(16526019)(8936002)(5660300002)(70586007)(36860700001)(70206006)(110136005)(4744005)(81166007)(82310400004)(2616005)(2906002)(4326008)(36756003)(40460700003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2022 08:44:23.6174 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2c942bd-0f65-458a-1615-08d9e0a80da1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1386 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org There are optional fields in GRE header(checksum/key/sequence), this patch adds definition of structures of the optional fields. Signed-off-by: Sean Zhang Acked-by: Ori Kam --- lib/net/rte_gre.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/lib/net/rte_gre.h b/lib/net/rte_gre.h index 5897756..5113e79 100644 --- a/lib/net/rte_gre.h +++ b/lib/net/rte_gre.h @@ -48,6 +48,27 @@ struct rte_gre_hdr { uint16_t proto; /**< Protocol Type */ } __rte_packed; +/** + * Optional field checksum in GRE header + */ +struct rte_gre_hdr_opt_checksum { + rte_be16_t checksum; +} __rte_packed; + +/** + * Optional field key in GRE header + */ +struct rte_gre_hdr_opt_key { + rte_be32_t key; +} __rte_packed; + +/** + * Optional field sequence in GRE header + */ +struct rte_gre_hdr_opt_sequence { + rte_be32_t sequence; +} __rte_packed; + #ifdef __cplusplus } #endif From patchwork Wed Jan 26 08:44:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Zhang X-Patchwork-Id: 106563 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 70E9EA04A8; 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And the flags in gre item should be correspondingly set with the new added items. Signed-off-by: Sean Zhang --- doc/guides/prog_guide/rte_flow.rst | 17 +++++++++++++++++ lib/ethdev/rte_flow.c | 1 + lib/ethdev/rte_flow.h | 19 +++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index b4aa9c4..0e47501 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -1106,6 +1106,7 @@ Matches a GRE header. Item: ``GRE_KEY`` ^^^^^^^^^^^^^^^^^ +This action is deprecated. Consider `Item: GRE_OPTION`. Matches a GRE key field. This should be preceded by item ``GRE``. @@ -1113,6 +1114,22 @@ This should be preceded by item ``GRE``. - Value to be matched is a big-endian 32 bit integer. - When this item present it implicitly match K bit in default mask as "1" +Item: ``GRE_OPTION`` +^^^^^^^^^^^^^^^^^^^^ + +Matches a GRE optional fields (checksum/key/sequence). +This should be preceded by item ``GRE``. + +- ``checksum``: checksum. +- ``key``: key. +- ``sequence``: sequence. +- The items in GRE_OPTION do not change bit flags(c_bit/k_bit/s_bit) in GRE + item. The bit flags need be set with GRE item by application. When the items + present, the corresponding bits in GRE spec and mask should be set "1" by + application, it means to match specified value of the fields. When the items + no present, but the corresponding bits in GRE spec and mask is "1", it means + to match any value of the fields. + Item: ``FUZZY`` ^^^^^^^^^^^^^^^ diff --git a/lib/ethdev/rte_flow.c b/lib/ethdev/rte_flow.c index a93f68a..7f93900 100644 --- a/lib/ethdev/rte_flow.c +++ b/lib/ethdev/rte_flow.c @@ -139,6 +139,7 @@ struct rte_flow_desc_data { MK_FLOW_ITEM(META, sizeof(struct rte_flow_item_meta)), MK_FLOW_ITEM(TAG, sizeof(struct rte_flow_item_tag)), MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)), + MK_FLOW_ITEM(GRE_OPTION, sizeof(struct rte_flow_item_gre_opt)), MK_FLOW_ITEM(GTP_PSC, sizeof(struct rte_flow_item_gtp_psc)), MK_FLOW_ITEM(PPPOES, sizeof(struct rte_flow_item_pppoe)), MK_FLOW_ITEM(PPPOED, sizeof(struct rte_flow_item_pppoe)), diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h index 1031fb2..db58b47 100644 --- a/lib/ethdev/rte_flow.h +++ b/lib/ethdev/rte_flow.h @@ -37,6 +37,7 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { @@ -660,6 +661,13 @@ enum rte_flow_item_type { * See struct rte_flow_item_ppp. */ RTE_FLOW_ITEM_TYPE_PPP, + + /** + * Matches GRE optional fields. + * + * See struct rte_flow_item_gre_opt. + */ + RTE_FLOW_ITEM_TYPE_GRE_OPTION, }; /** @@ -1196,6 +1204,17 @@ struct rte_flow_item_gre { #endif /** + * RTE_FLOW_ITEM_TYPE_GRE_OPTION. + * + * Matches GRE optional fields in header. + */ +struct rte_flow_item_gre_opt { + struct rte_gre_hdr_opt_checksum checksum; + struct rte_gre_hdr_opt_key key; + struct rte_gre_hdr_opt_sequence sequence; +}; + +/** * RTE_FLOW_ITEM_TYPE_FUZZY * * Fuzzy pattern match, expect faster than default. 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The item must follow gre item, and the item does not change the flags in gre item, the application should set the flags in gre item correspondingly. Application can still use gre_key item 'gre_key value is xx' for key matching, the effect is the same with using 'gre_option key is xx'. The examples for gre_option are as follows: To match on checksum field with value 0x11: testpmd> ... pattern / eth / gre c_bit is 1 / gre_option checksum is 0x11 / end .. To match on checksum field with value 0x11 and any value of key: testpmd> ... pattern / eth / gre c_bit is 1 k_bit is 1 / gre_option checksum is 0x11 / end .. To match on checksum field with value 0x11 and no key field in packet: testpmd> ... pattern / eth / gre c_bit is 1 k_bit is 0 / gre_option checksum is 0x11 / end .. The invalid patterns for gre_option are as follows: testpmd> ... pattern / eth / gre / gre_option checksum is 0x11 / end .. (c_bit in gre item not present) testpmd> ... pattern / eth / gre c_bit is 0 / gre_option checksum is 0x11 / end .. (c_bit is unset for gre item, but checksum is specified by gre_option item) Signed-off-by: Sean Zhang Acked-by: Ori Kam --- app/test-pmd/cmdline_flow.c | 59 +++++++++++++++++++++++++++++ doc/guides/testpmd_app_ug/testpmd_funcs.rst | 6 +++ 2 files changed, 65 insertions(+) diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c index 5c2bba4..b7aacac 100644 --- a/app/test-pmd/cmdline_flow.c +++ b/app/test-pmd/cmdline_flow.c @@ -271,6 +271,10 @@ enum index { ITEM_META_DATA, ITEM_GRE_KEY, ITEM_GRE_KEY_VALUE, + ITEM_GRE_OPTION, + ITEM_GRE_OPTION_CHECKSUM, + ITEM_GRE_OPTION_KEY, + ITEM_GRE_OPTION_SEQUENCE, ITEM_GTP_PSC, ITEM_GTP_PSC_QFI, ITEM_GTP_PSC_PDU_T, @@ -1042,6 +1046,7 @@ struct parse_action_priv { ITEM_ICMP6_ND_OPT_TLA_ETH, ITEM_META, ITEM_GRE_KEY, + ITEM_GRE_OPTION, ITEM_GTP_PSC, ITEM_PPPOES, ITEM_PPPOED, @@ -1232,6 +1237,14 @@ struct parse_action_priv { ZERO, }; +static const enum index item_gre_option[] = { + ITEM_GRE_OPTION_CHECKSUM, + ITEM_GRE_OPTION_KEY, + ITEM_GRE_OPTION_SEQUENCE, + ITEM_NEXT, + ZERO, +}; + static const enum index item_gtp[] = { ITEM_GTP_FLAGS, ITEM_GTP_MSG_TYPE, @@ -3479,6 +3492,38 @@ static int comp_set_modify_field_id(struct context *, const struct token *, item_param), .args = ARGS(ARG_ENTRY_HTON(rte_be32_t)), }, + [ITEM_GRE_OPTION] = { + .name = "gre_option", + .help = "match GRE optional fields", + .priv = PRIV_ITEM(GRE_OPTION, + sizeof(struct rte_flow_item_gre_opt)), + .next = NEXT(item_gre_option), + .call = parse_vc, + }, + [ITEM_GRE_OPTION_CHECKSUM] = { + .name = "checksum", + .help = "match GRE checksum", + .next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED), + item_param), + .args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_opt, + checksum)), + }, + [ITEM_GRE_OPTION_KEY] = { + .name = "key", + .help = "match GRE key", + .next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED), + item_param), + .args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_opt, + key)), + }, + [ITEM_GRE_OPTION_SEQUENCE] = { + .name = "sequence", + .help = "match GRE sequence", + .next = NEXT(item_gre_option, NEXT_ENTRY(COMMON_UNSIGNED), + item_param), + .args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_opt, + sequence)), + }, [ITEM_GTP_PSC] = { .name = "gtp_psc", .help = "match GTP extension header with type 0x85", @@ -9235,6 +9280,20 @@ static int comp_set_modify_field_id(struct context *, const struct token *, ((const struct rte_flow_item_flex *) item->spec)->length : 0; break; + case RTE_FLOW_ITEM_TYPE_GRE_OPTION: + size = 0; + if (item->spec) { + const struct rte_flow_item_gre_opt + *opt = item->spec; + if (opt->checksum.checksum) + size += 4; + if (opt->key.key) + size += 4; + if (opt->sequence.sequence) + size += 4; + } + proto = 0x2F; + break; default: fprintf(stderr, "Error - Not supported item\n"); goto error; diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst index 94792d8..751503e 100644 --- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst +++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst @@ -3714,6 +3714,12 @@ This section lists supported pattern items and their attributes, if any. - ``value {unsigned}``: key value. +- ``gre_option``: match GRE optional fields(checksum/key/sequence). + + - ``checksum {unsigned}``: checksum value. + - ``key {unsigned}``: key value. + - ``sequence {unsigned}``: sequence number value. + - ``fuzzy``: fuzzy pattern match, expect faster than default. - ``thresh {unsigned}``: accuracy threshold. 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The matching of checksum and sequence fields requests support from rdma-core with capability of misc5 and tunner_header 0-3. For patterns without checksum and sequence specified, keep using misc for matching as before, but for patterns with checksum or sequence, validate capability first and then use misc5 for the matching. Signed-off-by: Sean Zhang --- drivers/common/mlx5/mlx5_devx_cmds.c | 3 + drivers/net/mlx5/linux/mlx5_os.c | 2 + drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_flow.c | 106 +++++++++++++++++++++++++ drivers/net/mlx5/mlx5_flow.h | 6 ++ drivers/net/mlx5/mlx5_flow_dv.c | 146 +++++++++++++++++++++++++++++++++++ 6 files changed, 264 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 7cd3d4f..5d21480 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -1027,6 +1027,9 @@ struct mlx5_devx_obj * attr->flow.tunnel_header_0_1 = MLX5_GET (flow_table_nic_cap, hcattr, ft_field_support_2_nic_receive.tunnel_header_0_1); + attr->flow.tunnel_header_2_3 = MLX5_GET + (flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive.tunnel_header_2_3); attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); attr->inner_ipv4_ihl = MLX5_GET (flow_table_nic_cap, hcattr, diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 36f0fbf..6dbbb1f 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1385,6 +1385,8 @@ } if (config->hca_attr.flow.tunnel_header_0_1) sh->tunnel_header_0_1 = 1; + if (config->hca_attr.flow.tunnel_header_2_3) + sh->tunnel_header_2_3 = 1; #endif #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO if (config->hca_attr.flow_hit_aso && diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index b55f581..32b1c7b 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1150,6 +1150,7 @@ struct mlx5_dev_ctx_shared { uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */ uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */ uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */ + uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported. */ uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */ uint32_t reclaim_mode:1; /* Reclaim memory. */ uint32_t dr_drop_action_en:1; /* Use DR drop action. */ diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index b7cf414..9e608ba 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -2802,6 +2802,112 @@ struct mlx5_flow_tunnel_info { } /** + * Validate GRE optional item. + * + * @param[in] dev + * Pointer to the Ethernet device structure. + * @param[in] item + * Item specification. + * @param[in] item_flags + * Bit flags to mark detected items. + * @param[in] attr + * Flow rule attributes. + * @param[in] gre_item + * Pointer to gre_item + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev, + const struct rte_flow_item *item, + uint64_t item_flags, + const struct rte_flow_attr *attr, + const struct rte_flow_item *gre_item, + struct rte_flow_error *error) +{ + const struct rte_flow_item_gre *gre_spec = gre_item->spec; + const struct rte_flow_item_gre *gre_mask = gre_item->mask; + const struct rte_flow_item_gre_opt *spec = item->spec; + const struct rte_flow_item_gre_opt *mask = item->mask; + struct mlx5_priv *priv = dev->data->dev_private; + int ret = 0; + + if (!(item_flags & MLX5_FLOW_LAYER_GRE)) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, item, + "No preceding GRE header"); + if (item_flags & MLX5_FLOW_LAYER_INNER) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, item, + "GRE option following a wrong item"); + if (!gre_mask) + gre_mask = &rte_flow_item_gre_mask; + + struct rte_flow_item_gre_opt gre_option_default_mask = { + .checksum = { + .checksum = 0xffff, + }, + .key = { + .key = 0xffffffff, + }, + .sequence = { + .sequence = 0xffffffff, + }, + }; + + if (!mask) + mask = &gre_option_default_mask; + + if (spec && mask->checksum.checksum) + if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x8000)) && + !(gre_spec->c_rsvd0_ver & RTE_BE16(0x8000))) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Checksum bit must be on"); + + if (spec && mask->key.key) + if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && + !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Key bit must be on"); + + if (spec && mask->sequence.sequence) + if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x1000)) && + !(gre_spec->c_rsvd0_ver & RTE_BE16(0x1000))) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Sequence bit must be on"); + + if (spec && (mask->checksum.checksum || mask->sequence.sequence)) { + if (priv->sh->steering_format_version == + MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || + ((attr->group || attr->transfer) && + !priv->sh->misc5_cap) || + (!(priv->sh->tunnel_header_0_1 && + priv->sh->tunnel_header_2_3) && + !attr->group && !attr->transfer)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "Checksum/Sequence not supported"); + } + + ret = mlx5_flow_item_acceptable + (item, (const uint8_t *)mask, + (const uint8_t *)&gre_option_default_mask, + sizeof(struct rte_flow_item_gre_opt), + MLX5_ITEM_RANGE_NOT_ACCEPTED, error); + + return ret; +} + +/** * Validate GRE item. * * @param[in] item diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 8c131d6..210cc26 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1523,6 +1523,12 @@ int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, uint64_t item_flags, const struct rte_flow_item *gre_item, struct rte_flow_error *error); +int mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev, + const struct rte_flow_item *item, + uint64_t item_flags, + const struct rte_flow_attr *attr, + const struct rte_flow_item *gre_item, + struct rte_flow_error *error); int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, uint64_t item_flags, uint64_t last_item, diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 8022d7d..4536ddb 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7112,6 +7112,13 @@ struct mlx5_list_entry * gre_item = items; last_item = MLX5_FLOW_LAYER_GRE; break; + case RTE_FLOW_ITEM_TYPE_GRE_OPTION: + ret = mlx5_flow_validate_item_gre_option(dev, items, item_flags, + attr, gre_item, error); + if (ret < 0) + return ret; + last_item = MLX5_FLOW_LAYER_GRE; + break; case RTE_FLOW_ITEM_TYPE_NVGRE: ret = mlx5_flow_validate_item_nvgre(items, item_flags, next_protocol, @@ -8833,6 +8840,135 @@ struct mlx5_list_entry * } /** + * Add GRE optional items to matcher and to the value. + * + * @param[in, out] matcher + * Flow matcher. + * @param[in, out] key + * Flow matcher value. + * @param[in] item + * Flow pattern to translate. + * @param[in] gre_item + * Pointer to gre_item. + * @param[in] pattern_flags + * Accumulated pattern flags. + */ +static void +flow_dv_translate_item_gre_option(void *matcher, void *key, + const struct rte_flow_item *item, + const struct rte_flow_item *gre_item, + uint64_t pattern_flags) +{ + const struct rte_flow_item_gre_opt *option_m = item->mask; + const struct rte_flow_item_gre_opt *option_v = item->spec; + const struct rte_flow_item_gre *gre_m = gre_item->mask; + const struct rte_flow_item_gre *gre_v = gre_item->spec; + static const struct rte_flow_item_gre empty_gre = {0}; + struct rte_flow_item gre_key_item; + uint16_t c_rsvd0_ver_m, c_rsvd0_ver_v; + uint16_t protocol_m, protocol_v; + uint32_t *tunnel_header_v[4]; + uint32_t *tunnel_header_m[4]; + void *misc5_m; + void *misc5_v; + + struct rte_flow_item_gre_opt gre_option_default_mask = { + .checksum = { + .checksum = 0xffff, + }, + .key = { + .key = 0xffffffff, + }, + .sequence = { + .sequence = 0xffffffff, + }, + }; + + if (!option_v) + return; + if (!option_m) + option_m = &gre_option_default_mask; + + if (!(option_m->sequence.sequence || option_m->checksum.checksum)) { + flow_dv_translate_item_gre(matcher, key, gre_item, + pattern_flags); + gre_key_item.spec = &option_v->key.key; + gre_key_item.mask = &option_m->key.key; + flow_dv_translate_item_gre_key(matcher, key, &gre_key_item); + return; + } + + if (!gre_v) { + gre_v = &empty_gre; + gre_m = &empty_gre; + } else { + if (!gre_m) + gre_m = &rte_flow_item_gre_mask; + } + + misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5); + misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5); + tunnel_header_v[0] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, + misc5_v, tunnel_header_0); + tunnel_header_m[0] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, + misc5_m, tunnel_header_0); + tunnel_header_v[1] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, + misc5_v, tunnel_header_1); + tunnel_header_m[1] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, + misc5_m, tunnel_header_1); + tunnel_header_v[2] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, + misc5_v, tunnel_header_2); + tunnel_header_m[2] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, + misc5_m, tunnel_header_2); + tunnel_header_v[3] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, + misc5_v, tunnel_header_3); + tunnel_header_m[3] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, + misc5_m, tunnel_header_3); + + protocol_v = gre_v->protocol; + protocol_m = gre_m->protocol; + if (!protocol_m) { + /* Force next protocol to prevent matchers duplication */ + uint16_t ether_type = + mlx5_translate_tunnel_etypes(pattern_flags); + if (ether_type) { + protocol_v = rte_be_to_cpu_16(ether_type); + protocol_m = 0xFFFF; + } + } + c_rsvd0_ver_v = gre_v->c_rsvd0_ver; + c_rsvd0_ver_m = gre_m->c_rsvd0_ver; + + + if (option_m->sequence.sequence) { + c_rsvd0_ver_v |= RTE_BE16(0x1000); + c_rsvd0_ver_m |= RTE_BE16(0x1000); + } + + if (option_m->key.key) { + c_rsvd0_ver_v |= RTE_BE16(0x2000); + c_rsvd0_ver_m |= RTE_BE16(0x2000); + } + + if (option_m->checksum.checksum) { + c_rsvd0_ver_v |= RTE_BE16(0x8000); + c_rsvd0_ver_m |= RTE_BE16(0x8000); + } + + *tunnel_header_v[0] = (c_rsvd0_ver_v | protocol_v << 16) & + (c_rsvd0_ver_m | protocol_m << 16); + *tunnel_header_m[0] = c_rsvd0_ver_m | protocol_m << 16; + *tunnel_header_v[1] = option_v->checksum.checksum & + option_m->checksum.checksum; + *tunnel_header_m[1] = option_m->checksum.checksum; + *tunnel_header_v[2] = option_v->key.key & option_m->key.key; + *tunnel_header_m[2] = option_m->key.key; + *tunnel_header_v[3] = option_v->sequence.sequence & + option_m->sequence.sequence; + *tunnel_header_m[3] = option_m->sequence.sequence; +} + +/** * Add NVGRE item to matcher and to the value. * * @param[in, out] matcher @@ -12708,6 +12844,7 @@ struct mlx5_list_entry * }; const struct rte_flow_item *integrity_items[2] = {NULL, NULL}; const struct rte_flow_item *tunnel_item = NULL; + const struct rte_flow_item *gre_item = NULL; if (!wks) return rte_flow_error_set(error, ENOMEM, @@ -13480,12 +13617,18 @@ struct mlx5_list_entry * matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); last_item = MLX5_FLOW_LAYER_GRE; tunnel_item = items; + gre_item = items; break; case RTE_FLOW_ITEM_TYPE_GRE_KEY: flow_dv_translate_item_gre_key(match_mask, match_value, items); last_item = MLX5_FLOW_LAYER_GRE_KEY; break; + case RTE_FLOW_ITEM_TYPE_GRE_OPTION: + matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); + last_item = MLX5_FLOW_LAYER_GRE; + tunnel_item = items; + break; case RTE_FLOW_ITEM_TYPE_NVGRE: matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); last_item = MLX5_FLOW_LAYER_GRE; @@ -13645,6 +13788,9 @@ struct mlx5_list_entry * else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE) flow_dv_translate_item_nvgre(match_mask, match_value, tunnel_item, item_flags); + else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE_OPTION) + flow_dv_translate_item_gre_option(match_mask, match_value, + tunnel_item, gre_item, item_flags); else MLX5_ASSERT(false); }