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Sun, 10 Apr 2022 02:25:35 -0700 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Subject: [PATCH 1/3] net/mlx5: fix setting flags to external RxQ Date: Sun, 10 Apr 2022 12:25:26 +0300 Message-ID: <20220410092528.1001685-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220410092528.1001685-1-michaelba@nvidia.com> References: <20220410092528.1001685-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a8e8d04b-b1a3-4c19-213c-08da1ad41374 X-MS-TrafficTypeDiagnostic: MN2PR12MB4392:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: meXolAZmbiZwzNuwnt3mjBrcaTGColjYoFm34ehgKTSpW3LRHsMP6fdeuaPAYo5e6e9hYEfwwSFCcZvUz2qAJSWtwd5zm36s90YVptqTrjXqQQz6A2cAQzdXgTSiKiEAmve4OljxD3g7lng5UiwYqlgpjc4QVOVNkZL4mCUEcQt42/W17bJ0ijeCicrsF0Efxfva0awCyd6sdkcDpvtNKUkDZtWkKparoYS7Ziz1Ws6QQIh2CxnkFFa9bV8fg9kjo0esZNi8HLcnvBnKunQeExLc7T64hHrCTz3W3JoUgPZmZ6D0e3S2pe1aFv4Y7KOW4btk+vm8FU4DkwY28vwekiV0nBcGA+cZUvHZN6vCDLgJ8IUIOLUHQEpAbGsx/rOcITgC5nLYOjfhSPiH4+OW5b6HwIGzZSnIiiT+4NWElUDHLcTANJkMA6ZipX6hWFBAqppPAtBE0br8mx49R1uVQGmHtPxK3BaX4LKiwML/4eHDzW/eBTcwbL4Lprb+YXYiK1shT7A1ZFa9lfJ+5ddpTPAkJhz1+frUd+AvrgGhtZ0JwhOs0Hlfq4ELH0o0heFCfxC265iRHyqlkzpfvzEL2Q583162A3gLS7GUX4NVLmlsd86P0H0e9/wurjlimrBTOZe7GSCIl+68pnVVcewic875JzNBKmwcD//0NA53AGJeho+HqN3txVAGbt5XFIRlLddjmR93h6ACHqVPzNhWEw== X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(2616005)(5660300002)(4326008)(8676002)(2906002)(86362001)(82310400005)(6666004)(7696005)(356005)(6286002)(8936002)(36756003)(508600001)(83380400001)(26005)(81166007)(316002)(55016003)(47076005)(186003)(6916009)(1076003)(40460700003)(336012)(426003)(54906003)(70586007)(450100002)(36860700001)(70206006)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2022 09:25:38.6394 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8e8d04b-b1a3-4c19-213c-08da1ad41374 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4392 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The flow_drv_rxq_flags_set sets the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the device flow. It tries to get the RxQ control structure to update its ptype. however, external RxQs don't have control structure to update and it may cause a crash. This patch add check whether this Queue is external. Fixes: 311b17e669ab ("net/mlx5: support queue/RSS actions for external Rx queue") Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_flow.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 78cb38d42b..e7542afa80 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1379,8 +1379,11 @@ flow_drv_rxq_flags_set(struct rte_eth_dev *dev, return; for (i = 0; i != ind_tbl->queues_n; ++i) { int idx = ind_tbl->queues[i]; - struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); + struct mlx5_rxq_ctrl *rxq_ctrl; + if (mlx5_is_external_rxq(dev, idx)) + continue; + rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); MLX5_ASSERT(rxq_ctrl != NULL); if (rxq_ctrl == NULL) continue; @@ -1483,8 +1486,11 @@ flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, MLX5_ASSERT(dev->data->dev_started); for (i = 0; i != ind_tbl->queues_n; ++i) { int idx = ind_tbl->queues[i]; - struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); + struct mlx5_rxq_ctrl *rxq_ctrl; + if (mlx5_is_external_rxq(dev, idx)) + continue; + rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); MLX5_ASSERT(rxq_ctrl != NULL); if (rxq_ctrl == NULL) continue; From patchwork Sun Apr 10 09:25:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 109549 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 46985A00BE; Sun, 10 Apr 2022 11:25:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6549C427EE; Sun, 10 Apr 2022 11:25:44 +0200 (CEST) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2084.outbound.protection.outlook.com [40.107.223.84]) by mails.dpdk.org (Postfix) with ESMTP id 35CA1415D7; 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Sun, 10 Apr 2022 09:25:40 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sun, 10 Apr 2022 02:25:39 -0700 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22 via Frontend Transport; Sun, 10 Apr 2022 02:25:37 -0700 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Subject: [PATCH 2/3] net/mlx5: fix reading invalid index in RxQ array Date: Sun, 10 Apr 2022 12:25:27 +0300 Message-ID: <20220410092528.1001685-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220410092528.1001685-1-michaelba@nvidia.com> References: <20220410092528.1001685-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4d1980de-50ec-41a1-1a98-08da1ad4149a X-MS-TrafficTypeDiagnostic: SA0PR12MB4509:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2022 09:25:40.6129 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d1980de-50ec-41a1-1a98-08da1ad4149a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4509 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The mlx5_rxq_get() function gets RxQ index and return RxQ priv accordingly. When it gets an invalid index, it accesses out of array bounds which might cause undefined behavior. This patch adds a check for invalid indexes before accessing to array. Fixes: 0cedf34da78f ("net/mlx5: move Rx queue reference count") Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_rxq.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index f16795bac3..d41834f46f 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -2042,6 +2042,8 @@ mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx) { struct mlx5_priv *priv = dev->data->dev_private; + if (idx >= priv->rxqs_n) + return NULL; MLX5_ASSERT(priv->rxq_privs != NULL); return (*priv->rxq_privs)[idx]; } From patchwork Sun Apr 10 09:25:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 109550 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E91FEA00BE; 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Sun, 10 Apr 2022 09:25:41 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sun, 10 Apr 2022 02:25:41 -0700 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22 via Frontend Transport; Sun, 10 Apr 2022 02:25:39 -0700 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko Subject: [PATCH 3/3] net/mlx5: optimize Rx is hairpin function Date: Sun, 10 Apr 2022 12:25:28 +0300 Message-ID: <20220410092528.1001685-4-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220410092528.1001685-1-michaelba@nvidia.com> References: <20220410092528.1001685-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1a288500-c3d0-467f-2429-08da1ad41574 X-MS-TrafficTypeDiagnostic: BN8PR12MB4785:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2022 09:25:42.0574 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a288500-c3d0-467f-2429-08da1ad41574 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB4785 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The mlx5_rxq_is_hairpin() function checks whether RxQ type is Hairpin. It is done by reading a flag in Rx control structure coming from mlx5_rxq_ctrl_get() function. The function verifies that the queue index is valid even though it has been checked within the mlx5_rxq_ctrl_get() function. This patch removes the redundant check. Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_rxq.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index d41834f46f..1782d52f71 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -2332,13 +2332,12 @@ mlx5_ext_rxq_verify(struct rte_eth_dev *dev) bool mlx5_rxq_is_hairpin(struct rte_eth_dev *dev, uint16_t idx) { - struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_rxq_ctrl *rxq_ctrl; if (mlx5_is_external_rxq(dev, idx)) return false; rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); - return (idx < priv->rxqs_n && rxq_ctrl != NULL && rxq_ctrl->is_hairpin); + return (rxq_ctrl != NULL && rxq_ctrl->is_hairpin); } /* @@ -2355,9 +2354,12 @@ mlx5_rxq_is_hairpin(struct rte_eth_dev *dev, uint16_t idx) const struct rte_eth_hairpin_conf * mlx5_rxq_get_hairpin_conf(struct rte_eth_dev *dev, uint16_t idx) { - struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx); + if (mlx5_rxq_is_hairpin(dev, idx)) { + struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx); - return mlx5_rxq_is_hairpin(dev, idx) ? &rxq->hairpin_conf : NULL; + return rxq != NULL ? &rxq->hairpin_conf : NULL; + } + return NULL; } /** @@ -2367,7 +2369,7 @@ mlx5_rxq_get_hairpin_conf(struct rte_eth_dev *dev, uint16_t idx) * @param ind_tbl * Pointer to indirection table to match. * @param queues - * Queues to match to ques in indirection table. + * Queues to match to queues in indirection table. * @param queues_n * Number of queues in the array. * @@ -2376,11 +2378,11 @@ mlx5_rxq_get_hairpin_conf(struct rte_eth_dev *dev, uint16_t idx) */ static int mlx5_ind_table_obj_match_queues(const struct mlx5_ind_table_obj *ind_tbl, - const uint16_t *queues, uint32_t queues_n) + const uint16_t *queues, uint32_t queues_n) { - return (ind_tbl->queues_n == queues_n) && - (!memcmp(ind_tbl->queues, queues, - ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))); + return (ind_tbl->queues_n == queues_n) && + (!memcmp(ind_tbl->queues, queues, + ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))); } /**