From patchwork Thu Apr 28 03:30:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 110403 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A9A6EA0503; Thu, 28 Apr 2022 05:53:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DD46542803; Thu, 28 Apr 2022 05:52:54 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id E1791410F3 for ; Thu, 28 Apr 2022 05:52:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651117972; x=1682653972; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=xEKefMjR3h9JAESPdnQE2kx5ptBt1rR8l5zTEtJ2nDc=; b=FFvc3ruBhjc9yrF2eYr+nCyouz60BBGt/D7/dyigMi8yWZ3VErJHQ3vn E3gobvTGUH5vbjPl+tx+YMK3cqgFcGiY/mXSy+8qSOiHxV+CpFC0JoztH HpNhZnVdzCNHID1TWYLWXm0Cd/3gE+0hjUk1eFKQXQQTNrXkzI+CQSFSN d4nDw4c4Tx0c3F2dIq2+Gz+E0W9pN+kUKtvTO/OvUxxCSmKKPv81fBOO8 OxHBD6mRWxKL62WNqhD8AeHAW436Xz+84dqNzU3L9MaigAsBp9JHtCenB BZmRZSZodgapGaObOgQHYgpwkN/t+zH7HM392vExJJmNv8DGH6J5RVwKE g==; X-IronPort-AV: E=McAfee;i="6400,9594,10330"; a="253531275" X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="253531275" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 20:52:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="514044782" Received: from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181]) by orsmga003.jf.intel.com with ESMTP; 27 Apr 2022 20:52:40 -0700 From: Wenjun Wu To: dev@dpdk.org, qiming.yang@intel.com, qi.z.zhang@intel.com Subject: [PATCH v9 1/9] net/ice/base: fix dead lock issue when getting node from ID type Date: Thu, 28 Apr 2022 11:30:26 +0800 Message-Id: <20220428033034.3490183-2-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220428033034.3490183-1-wenjun1.wu@intel.com> References: <20220329014813.1092054-1-wenjun1.wu@intel.com> <20220428033034.3490183-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The function ice_sched_get_node_by_id_type needs to be called with the scheduler lock held. However, the function ice_sched_get_node also requests the scheduler lock. It will cause the dead lock issue. This patch replaces function ice_sched_get_node with function ice_sched_find_node_by_teid to solve this problem. Signed-off-by: Wenjun Wu --- drivers/net/ice/base/ice_sched.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index 2620892c9e..e697c579be 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -4774,12 +4774,12 @@ ice_sched_get_node_by_id_type(struct ice_port_info *pi, u32 id, case ICE_AGG_TYPE_Q: /* The current implementation allows single queue to modify */ - node = ice_sched_get_node(pi, id); + node = ice_sched_find_node_by_teid(pi->root, id); break; case ICE_AGG_TYPE_QG: /* The current implementation allows single qg to modify */ - child_node = ice_sched_get_node(pi, id); + child_node = ice_sched_find_node_by_teid(pi->root, id); if (!child_node) break; node = child_node->parent; From patchwork Thu Apr 28 03:30:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 110401 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 59EB3A0503; Thu, 28 Apr 2022 05:53:02 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 131394068F; Thu, 28 Apr 2022 05:52:53 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 1D87C40691 for ; Thu, 28 Apr 2022 05:52:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651117971; x=1682653971; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=BCeKKmCoeiqtM9BOGYhY7vGXbguWchhw2/6bSnaD6pk=; b=Dj6A/eVSNvt5lSPTcR/TGO/tOg7Q3/XaPpYZfwf929lF6/qsgKcUr8qN f209m5KTPv5l3Vx3jYHwUaYrqPxwvj+Cnyhr98KEXsT+ZAtN4Xlpv6tgL oYPjeQv0QuqmleNmunPdPHFmcsUWnoO4uyvyKQtjfjfPC0xWhHnMv91ic 9GGq7kAGB9hut/JR4POyHxif4zE84StsoPdoer8vq2knFCB9hbL1gK8vU WxHs4+jqVj11tbwk+RGk3oXd4c7ju5Vzxx+YbMuiOV0J8eqs1N0PBbbih D6uMCvPk3uOzek/Whcc5EnJUuEuUKDiNBm2uhjM+FqCSXc1V0tnP4FSmw w==; X-IronPort-AV: E=McAfee;i="6400,9594,10330"; a="253531277" X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="253531277" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 20:52:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="514044787" Received: from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181]) by orsmga003.jf.intel.com with ESMTP; 27 Apr 2022 20:52:42 -0700 From: Wenjun Wu To: dev@dpdk.org, qiming.yang@intel.com, qi.z.zhang@intel.com Subject: [PATCH v9 2/9] net/ice/base: support queue BW allocation configuration Date: Thu, 28 Apr 2022 11:30:27 +0800 Message-Id: <20220428033034.3490183-3-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220428033034.3490183-1-wenjun1.wu@intel.com> References: <20220329014813.1092054-1-wenjun1.wu@intel.com> <20220428033034.3490183-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds BW allocation support of queue scheduling node to support WFQ in queue level. Signed-off-by: Wenjun Wu --- drivers/net/ice/base/ice_sched.c | 64 ++++++++++++++++++++++++++++++++ drivers/net/ice/base/ice_sched.h | 3 ++ 2 files changed, 67 insertions(+) diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index e697c579be..4ca15bf8f8 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -3613,6 +3613,70 @@ ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids, return status; } +/** + * ice_sched_save_q_bw_alloc - save queue node's BW allocation information + * @q_ctx: queue context structure + * @rl_type: rate limit type min, max, or shared + * @bw_alloc: BW weight/allocation + * + * Save BW information of queue type node for post replay use. + */ +static enum ice_status +ice_sched_save_q_bw_alloc(struct ice_q_ctx *q_ctx, enum ice_rl_type rl_type, + u32 bw_alloc) +{ + switch (rl_type) { + case ICE_MIN_BW: + ice_set_clear_cir_bw_alloc(&q_ctx->bw_t_info, bw_alloc); + break; + case ICE_MAX_BW: + ice_set_clear_eir_bw_alloc(&q_ctx->bw_t_info, bw_alloc); + break; + default: + return ICE_ERR_PARAM; + } + return ICE_SUCCESS; +} + +/** + * ice_cfg_q_bw_alloc - configure queue BW weight/alloc params + * @pi: port information structure + * @vsi_handle: sw VSI handle + * @tc: traffic class + * @q_handle: software queue handle + * @rl_type: min, max, or shared + * @bw_alloc: BW weight/allocation + * + * This function configures BW allocation of queue scheduling node. + */ +enum ice_status +ice_cfg_q_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, + u16 q_handle, enum ice_rl_type rl_type, u32 bw_alloc) +{ + enum ice_status status = ICE_ERR_PARAM; + struct ice_sched_node *node; + struct ice_q_ctx *q_ctx; + + ice_acquire_lock(&pi->sched_lock); + q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handle); + if (!q_ctx) + goto exit_q_bw_alloc; + + node = ice_sched_find_node_by_teid(pi->root, q_ctx->q_teid); + if (!node) { + ice_debug(pi->hw, ICE_DBG_SCHED, "Wrong q_teid\n"); + goto exit_q_bw_alloc; + } + + status = ice_sched_cfg_node_bw_alloc(pi->hw, node, rl_type, bw_alloc); + if (!status) + status = ice_sched_save_q_bw_alloc(q_ctx, rl_type, bw_alloc); + +exit_q_bw_alloc: + ice_release_lock(&pi->sched_lock); + return status; +} + /** * ice_cfg_agg_vsi_priority_per_tc - config aggregator's VSI priority per TC * @pi: port information structure diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h index 1441b5f191..184ad09e6a 100644 --- a/drivers/net/ice/base/ice_sched.h +++ b/drivers/net/ice/base/ice_sched.h @@ -172,6 +172,9 @@ enum ice_status ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids, u8 *q_prio); enum ice_status +ice_cfg_q_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, + u16 q_handle, enum ice_rl_type rl_type, u32 bw_alloc); +enum ice_status ice_cfg_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 ena_tcmap, enum ice_rl_type rl_type, u8 *bw_alloc); enum ice_status From patchwork Thu Apr 28 03:30:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 110399 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BC35FA0503; Thu, 28 Apr 2022 05:52:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5C1E3410DC; Thu, 28 Apr 2022 05:52:51 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id B02DE4068F for ; Thu, 28 Apr 2022 05:52:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651117969; x=1682653969; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ktOj2bbb+GPsPVYYlUyLtrIxuLdSm+53i17qdYeA7VE=; b=AyVR8utBYN81ehAOLutOmUdB/G1lAqBOA7vdhlRohJ0W+HOvrfL8ypwE CGjcFePM1ThzrdxSj0jPrREoSSV/2EYnniV5HbONcIil41y9wP7u0CHRG +ZorVSF3WXQtjsZN1VNjbloCcfFmhK+StqCMwkNKHlkJ8TEdZUAQJOU2q wvo7XkfLxjy48LspPllbYNzzJgOZwZF/ps/kWrCWKATFbkHwgQ8ZDr9Ez ARfFKe+B+nPNCO/wLcqKxiJHfPOev6G+HUO5voESPPa+1hInYGryaySJR Jb41xNeGOsvxwkcM4th4pC+Pg81mtwV9FnHAK+ivC+KmpEsrWlqGhW59r g==; X-IronPort-AV: E=McAfee;i="6400,9594,10330"; a="253531278" X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="253531278" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 20:52:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="514044793" Received: from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181]) by orsmga003.jf.intel.com with ESMTP; 27 Apr 2022 20:52:43 -0700 From: Wenjun Wu To: dev@dpdk.org, qiming.yang@intel.com, qi.z.zhang@intel.com Subject: [PATCH v9 3/9] net/ice/base: support priority configuration of the exact node Date: Thu, 28 Apr 2022 11:30:28 +0800 Message-Id: <20220428033034.3490183-4-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220428033034.3490183-1-wenjun1.wu@intel.com> References: <20220329014813.1092054-1-wenjun1.wu@intel.com> <20220428033034.3490183-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds priority configuration support of the exact node in the scheduler tree. This function does not need additional calls to the scheduler lock. Signed-off-by: Wenjun Wu --- drivers/net/ice/base/ice_sched.c | 22 ++++++++++++++++++++++ drivers/net/ice/base/ice_sched.h | 3 +++ 2 files changed, 25 insertions(+) diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index 4ca15bf8f8..1b060d3567 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -3613,6 +3613,28 @@ ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids, return status; } +/** + * ice_sched_cfg_sibl_node_prio_lock - config priority of node + * @pi: port information structure + * @node: sched node to configure + * @priority: sibling priority + * + * This function configures node element's sibling priority only. + */ +enum ice_status +ice_sched_cfg_sibl_node_prio_lock(struct ice_port_info *pi, + struct ice_sched_node *node, + u8 priority) +{ + enum ice_status status; + + ice_acquire_lock(&pi->sched_lock); + status = ice_sched_cfg_sibl_node_prio(pi, node, priority); + ice_release_lock(&pi->sched_lock); + + return status; +} + /** * ice_sched_save_q_bw_alloc - save queue node's BW allocation information * @q_ctx: queue context structure diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h index 184ad09e6a..c9f3f79eff 100644 --- a/drivers/net/ice/base/ice_sched.h +++ b/drivers/net/ice/base/ice_sched.h @@ -169,6 +169,9 @@ enum ice_status ice_cfg_agg_bw_no_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc); enum ice_status +ice_sched_cfg_sibl_node_prio_lock(struct ice_port_info *pi, + struct ice_sched_node *node, u8 priority); +enum ice_status ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids, u8 *q_prio); enum ice_status From patchwork Thu Apr 28 03:30:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 110402 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C9018A0503; Thu, 28 Apr 2022 05:53:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F1A76427FC; Thu, 28 Apr 2022 05:52:53 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 04ADD4068F for ; Thu, 28 Apr 2022 05:52:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651117971; x=1682653971; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=zynhbHLpKia99DqCRD81kP3atZOdfH8BtVSUGufESmI=; b=PQOisI7Gz4X7HiTbtLgqVvanc23YxwowFawtLBUdk7Q+E6DblM5uJuWJ EwjGxRC03Z0oEYXLRs/4LoREi+MJJVQ7pT+68/WMCAgIqqco8Z8bpi7Pa dKtHrrJDfDPaI6wP6PQ9syLZ3ptTaA7JWjes0bqle2+UgZd509vgUzFi0 lv/5OLlV/ZUina2xLpJ0LCOsPjHIApUA3Jz9YGEKx6Iq37f2oJYIWvCOL p4zMLdNSwA2NbSvFUSynZ53/Pd0gGWgr6FuMa/U7iUbSUjoRmkqYs0RRP 6T6JSi7yIYTcMw6JjgS69fLNjWDQXgqN47zL8QA3QeOfyGH2a2gpYX+bY w==; X-IronPort-AV: E=McAfee;i="6400,9594,10330"; a="253531280" X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="253531280" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 20:52:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="514044804" Received: from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181]) by orsmga003.jf.intel.com with ESMTP; 27 Apr 2022 20:52:44 -0700 From: Wenjun Wu To: dev@dpdk.org, qiming.yang@intel.com, qi.z.zhang@intel.com Subject: [PATCH v9 4/9] net/ice: support queue bandwidth limit Date: Thu, 28 Apr 2022 11:30:29 +0800 Message-Id: <20220428033034.3490183-5-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220428033034.3490183-1-wenjun1.wu@intel.com> References: <20220329014813.1092054-1-wenjun1.wu@intel.com> <20220428033034.3490183-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ting Xu Enable basic TM API for PF only. Support for adding profiles and queue nodes. Only max bandwidth is supported in profiles. Profiles can be assigned to target queues. Only TC0 is valid. Signed-off-by: Wenjun Wu Signed-off-by: Ting Xu --- doc/guides/rel_notes/release_22_07.rst | 5 + drivers/net/ice/ice_ethdev.c | 19 + drivers/net/ice/ice_ethdev.h | 48 ++ drivers/net/ice/ice_tm.c | 599 +++++++++++++++++++++++++ drivers/net/ice/meson.build | 1 + 5 files changed, 672 insertions(+) create mode 100644 drivers/net/ice/ice_tm.c diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index 90123bb807..4797da32da 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -60,6 +60,11 @@ New Features * Added Tx QoS queue rate limitation support. * Added quanta size configuration support. +* **Updated Intel ice driver.** + + * Added Tx QoS rate limitation and priority configuration support for queue and queue group. + * Added TX QoS queue weight configuration support. + Removed Items ------------- diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 00ac2bb191..35ab542e61 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -205,6 +205,18 @@ static const struct rte_pci_id pci_id_ice_map[] = { { .vendor_id = 0, /* sentinel */ }, }; +static int +ice_tm_ops_get(struct rte_eth_dev *dev __rte_unused, + void *arg) +{ + if (!arg) + return -EINVAL; + + *(const void **)arg = &ice_tm_ops; + + return 0; +} + static const struct eth_dev_ops ice_eth_dev_ops = { .dev_configure = ice_dev_configure, .dev_start = ice_dev_start, @@ -267,6 +279,7 @@ static const struct eth_dev_ops ice_eth_dev_ops = { .timesync_read_time = ice_timesync_read_time, .timesync_write_time = ice_timesync_write_time, .timesync_disable = ice_timesync_disable, + .tm_ops_get = ice_tm_ops_get, }; /* store statistics names and its offset in stats structure */ @@ -2328,6 +2341,9 @@ ice_dev_init(struct rte_eth_dev *dev) /* Initialize RSS context for gtpu_eh */ ice_rss_ctx_init(pf); + /* Initialize TM configuration */ + ice_tm_conf_init(dev); + if (!ad->is_safe_mode) { ret = ice_flow_init(ad); if (ret) { @@ -2508,6 +2524,9 @@ ice_dev_close(struct rte_eth_dev *dev) rte_free(pf->proto_xtr); pf->proto_xtr = NULL; + /* Uninit TM configuration */ + ice_tm_conf_uninit(dev); + if (ad->devargs.pps_out_ena) { ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(pin_idx, timer), 0); ICE_WRITE_REG(hw, GLTSYN_CLKO(pin_idx, timer), 0); diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h index 3d8427225f..4359c61624 100644 --- a/drivers/net/ice/ice_ethdev.h +++ b/drivers/net/ice/ice_ethdev.h @@ -9,10 +9,12 @@ #include #include +#include #include "base/ice_common.h" #include "base/ice_adminq_cmd.h" #include "base/ice_flow.h" +#include "base/ice_sched.h" #define ICE_ADMINQ_LEN 32 #define ICE_SBIOQ_LEN 32 @@ -453,6 +455,48 @@ struct ice_acl_info { uint64_t hw_entry_id[MAX_ACL_NORMAL_ENTRIES]; }; +TAILQ_HEAD(ice_shaper_profile_list, ice_tm_shaper_profile); +TAILQ_HEAD(ice_tm_node_list, ice_tm_node); + +struct ice_tm_shaper_profile { + TAILQ_ENTRY(ice_tm_shaper_profile) node; + uint32_t shaper_profile_id; + uint32_t reference_count; + struct rte_tm_shaper_params profile; +}; + +/* Struct to store Traffic Manager node configuration. */ +struct ice_tm_node { + TAILQ_ENTRY(ice_tm_node) node; + uint32_t id; + uint32_t tc; + uint32_t priority; + uint32_t weight; + uint32_t reference_count; + struct ice_tm_node *parent; + struct ice_tm_shaper_profile *shaper_profile; + struct rte_tm_node_params params; +}; + +/* node type of Traffic Manager */ +enum ice_tm_node_type { + ICE_TM_NODE_TYPE_PORT, + ICE_TM_NODE_TYPE_TC, + ICE_TM_NODE_TYPE_QUEUE, + ICE_TM_NODE_TYPE_MAX, +}; + +/* Struct to store all the Traffic Manager configuration. */ +struct ice_tm_conf { + struct ice_shaper_profile_list shaper_profile_list; + struct ice_tm_node *root; /* root node - vf vsi */ + struct ice_tm_node_list tc_list; /* node list for all the TCs */ + struct ice_tm_node_list queue_list; /* node list for all the queues */ + uint32_t nb_tc_node; + uint32_t nb_queue_node; + bool committed; +}; + struct ice_pf { struct ice_adapter *adapter; /* The adapter this PF associate to */ struct ice_vsi *main_vsi; /* pointer to main VSI structure */ @@ -497,6 +541,7 @@ struct ice_pf { uint64_t old_tx_bytes; uint64_t supported_rxdid; /* bitmap for supported RXDID */ uint64_t rss_hf; + struct ice_tm_conf tm_conf; }; #define ICE_MAX_QUEUE_NUM 2048 @@ -624,6 +669,9 @@ int ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, struct ice_rss_hash_cfg *cfg); int ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, struct ice_rss_hash_cfg *cfg); +void ice_tm_conf_init(struct rte_eth_dev *dev); +void ice_tm_conf_uninit(struct rte_eth_dev *dev); +extern const struct rte_tm_ops ice_tm_ops; static inline int ice_align_floor(int n) diff --git a/drivers/net/ice/ice_tm.c b/drivers/net/ice/ice_tm.c new file mode 100644 index 0000000000..383af88981 --- /dev/null +++ b/drivers/net/ice/ice_tm.c @@ -0,0 +1,599 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Intel Corporation + */ +#include + +#include "ice_ethdev.h" +#include "ice_rxtx.h" + +static int ice_hierarchy_commit(struct rte_eth_dev *dev, + int clear_on_fail, + __rte_unused struct rte_tm_error *error); +static int ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id, + uint32_t parent_node_id, uint32_t priority, + uint32_t weight, uint32_t level_id, + struct rte_tm_node_params *params, + struct rte_tm_error *error); +static int ice_tm_node_delete(struct rte_eth_dev *dev, uint32_t node_id, + struct rte_tm_error *error); +static int ice_node_type_get(struct rte_eth_dev *dev, uint32_t node_id, + int *is_leaf, struct rte_tm_error *error); +static int ice_shaper_profile_add(struct rte_eth_dev *dev, + uint32_t shaper_profile_id, + struct rte_tm_shaper_params *profile, + struct rte_tm_error *error); +static int ice_shaper_profile_del(struct rte_eth_dev *dev, + uint32_t shaper_profile_id, + struct rte_tm_error *error); + +const struct rte_tm_ops ice_tm_ops = { + .shaper_profile_add = ice_shaper_profile_add, + .shaper_profile_delete = ice_shaper_profile_del, + .node_add = ice_tm_node_add, + .node_delete = ice_tm_node_delete, + .node_type_get = ice_node_type_get, + .hierarchy_commit = ice_hierarchy_commit, +}; + +void +ice_tm_conf_init(struct rte_eth_dev *dev) +{ + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + + /* initialize node configuration */ + TAILQ_INIT(&pf->tm_conf.shaper_profile_list); + pf->tm_conf.root = NULL; + TAILQ_INIT(&pf->tm_conf.tc_list); + TAILQ_INIT(&pf->tm_conf.queue_list); + pf->tm_conf.nb_tc_node = 0; + pf->tm_conf.nb_queue_node = 0; + pf->tm_conf.committed = false; +} + +void +ice_tm_conf_uninit(struct rte_eth_dev *dev) +{ + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + struct ice_tm_node *tm_node; + + /* clear node configuration */ + while ((tm_node = TAILQ_FIRST(&pf->tm_conf.queue_list))) { + TAILQ_REMOVE(&pf->tm_conf.queue_list, tm_node, node); + rte_free(tm_node); + } + pf->tm_conf.nb_queue_node = 0; + while ((tm_node = TAILQ_FIRST(&pf->tm_conf.tc_list))) { + TAILQ_REMOVE(&pf->tm_conf.tc_list, tm_node, node); + rte_free(tm_node); + } + pf->tm_conf.nb_tc_node = 0; + if (pf->tm_conf.root) { + rte_free(pf->tm_conf.root); + pf->tm_conf.root = NULL; + } +} + +static inline struct ice_tm_node * +ice_tm_node_search(struct rte_eth_dev *dev, + uint32_t node_id, enum ice_tm_node_type *node_type) +{ + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + struct ice_tm_node_list *tc_list = &pf->tm_conf.tc_list; + struct ice_tm_node_list *queue_list = &pf->tm_conf.queue_list; + struct ice_tm_node *tm_node; + + if (pf->tm_conf.root && pf->tm_conf.root->id == node_id) { + *node_type = ICE_TM_NODE_TYPE_PORT; + return pf->tm_conf.root; + } + + TAILQ_FOREACH(tm_node, tc_list, node) { + if (tm_node->id == node_id) { + *node_type = ICE_TM_NODE_TYPE_TC; + return tm_node; + } + } + + TAILQ_FOREACH(tm_node, queue_list, node) { + if (tm_node->id == node_id) { + *node_type = ICE_TM_NODE_TYPE_QUEUE; + return tm_node; + } + } + + return NULL; +} + +static int +ice_node_param_check(struct ice_pf *pf, uint32_t node_id, + uint32_t priority, uint32_t weight, + struct rte_tm_node_params *params, + struct rte_tm_error *error) +{ + /* checked all the unsupported parameter */ + if (node_id == RTE_TM_NODE_ID_NULL) { + error->type = RTE_TM_ERROR_TYPE_NODE_ID; + error->message = "invalid node id"; + return -EINVAL; + } + + if (priority) { + error->type = RTE_TM_ERROR_TYPE_NODE_PRIORITY; + error->message = "priority should be 0"; + return -EINVAL; + } + + if (weight != 1) { + error->type = RTE_TM_ERROR_TYPE_NODE_WEIGHT; + error->message = "weight must be 1"; + return -EINVAL; + } + + /* not support shared shaper */ + if (params->shared_shaper_id) { + error->type = RTE_TM_ERROR_TYPE_NODE_PARAMS_SHARED_SHAPER_ID; + error->message = "shared shaper not supported"; + return -EINVAL; + } + if (params->n_shared_shapers) { + error->type = RTE_TM_ERROR_TYPE_NODE_PARAMS_N_SHARED_SHAPERS; + error->message = "shared shaper not supported"; + return -EINVAL; + } + + /* for non-leaf node */ + if (node_id >= pf->dev_data->nb_tx_queues) { + if (params->nonleaf.wfq_weight_mode) { + error->type = + RTE_TM_ERROR_TYPE_NODE_PARAMS_WFQ_WEIGHT_MODE; + error->message = "WFQ not supported"; + return -EINVAL; + } + if (params->nonleaf.n_sp_priorities != 1) { + error->type = + RTE_TM_ERROR_TYPE_NODE_PARAMS_N_SP_PRIORITIES; + error->message = "SP priority not supported"; + return -EINVAL; + } else if (params->nonleaf.wfq_weight_mode && + !(*params->nonleaf.wfq_weight_mode)) { + error->type = + RTE_TM_ERROR_TYPE_NODE_PARAMS_WFQ_WEIGHT_MODE; + error->message = "WFP should be byte mode"; + return -EINVAL; + } + + return 0; + } + + /* for leaf node */ + if (params->leaf.cman) { + error->type = RTE_TM_ERROR_TYPE_NODE_PARAMS_CMAN; + error->message = "Congestion management not supported"; + return -EINVAL; + } + if (params->leaf.wred.wred_profile_id != + RTE_TM_WRED_PROFILE_ID_NONE) { + error->type = + RTE_TM_ERROR_TYPE_NODE_PARAMS_WRED_PROFILE_ID; + error->message = "WRED not supported"; + return -EINVAL; + } + if (params->leaf.wred.shared_wred_context_id) { + error->type = + RTE_TM_ERROR_TYPE_NODE_PARAMS_SHARED_WRED_CONTEXT_ID; + error->message = "WRED not supported"; + return -EINVAL; + } + if (params->leaf.wred.n_shared_wred_contexts) { + error->type = + RTE_TM_ERROR_TYPE_NODE_PARAMS_N_SHARED_WRED_CONTEXTS; + error->message = "WRED not supported"; + return -EINVAL; + } + + return 0; +} + +static int +ice_node_type_get(struct rte_eth_dev *dev, uint32_t node_id, + int *is_leaf, struct rte_tm_error *error) +{ + enum ice_tm_node_type node_type = ICE_TM_NODE_TYPE_MAX; + struct ice_tm_node *tm_node; + + if (!is_leaf || !error) + return -EINVAL; + + if (node_id == RTE_TM_NODE_ID_NULL) { + error->type = RTE_TM_ERROR_TYPE_NODE_ID; + error->message = "invalid node id"; + return -EINVAL; + } + + /* check if the node id exists */ + tm_node = ice_tm_node_search(dev, node_id, &node_type); + if (!tm_node) { + error->type = RTE_TM_ERROR_TYPE_NODE_ID; + error->message = "no such node"; + return -EINVAL; + } + + if (node_type == ICE_TM_NODE_TYPE_QUEUE) + *is_leaf = true; + else + *is_leaf = false; + + return 0; +} + +static inline struct ice_tm_shaper_profile * +ice_shaper_profile_search(struct rte_eth_dev *dev, + uint32_t shaper_profile_id) +{ + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + struct ice_shaper_profile_list *shaper_profile_list = + &pf->tm_conf.shaper_profile_list; + struct ice_tm_shaper_profile *shaper_profile; + + TAILQ_FOREACH(shaper_profile, shaper_profile_list, node) { + if (shaper_profile_id == shaper_profile->shaper_profile_id) + return shaper_profile; + } + + return NULL; +} + +static int +ice_shaper_profile_param_check(struct rte_tm_shaper_params *profile, + struct rte_tm_error *error) +{ + /* min bucket size not supported */ + if (profile->committed.size) { + error->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_COMMITTED_SIZE; + error->message = "committed bucket size not supported"; + return -EINVAL; + } + /* max bucket size not supported */ + if (profile->peak.size) { + error->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PEAK_SIZE; + error->message = "peak bucket size not supported"; + return -EINVAL; + } + /* length adjustment not supported */ + if (profile->pkt_length_adjust) { + error->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PKT_ADJUST_LEN; + error->message = "packet length adjustment not supported"; + return -EINVAL; + } + + return 0; +} + +static int +ice_shaper_profile_add(struct rte_eth_dev *dev, + uint32_t shaper_profile_id, + struct rte_tm_shaper_params *profile, + struct rte_tm_error *error) +{ + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + struct ice_tm_shaper_profile *shaper_profile; + int ret; + + if (!profile || !error) + return -EINVAL; + + ret = ice_shaper_profile_param_check(profile, error); + if (ret) + return ret; + + shaper_profile = ice_shaper_profile_search(dev, shaper_profile_id); + + if (shaper_profile) { + error->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID; + error->message = "profile ID exist"; + return -EINVAL; + } + + shaper_profile = rte_zmalloc("ice_tm_shaper_profile", + sizeof(struct ice_tm_shaper_profile), + 0); + if (!shaper_profile) + return -ENOMEM; + shaper_profile->shaper_profile_id = shaper_profile_id; + rte_memcpy(&shaper_profile->profile, profile, + sizeof(struct rte_tm_shaper_params)); + TAILQ_INSERT_TAIL(&pf->tm_conf.shaper_profile_list, + shaper_profile, node); + + return 0; +} + +static int +ice_shaper_profile_del(struct rte_eth_dev *dev, + uint32_t shaper_profile_id, + struct rte_tm_error *error) +{ + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + struct ice_tm_shaper_profile *shaper_profile; + + if (!error) + return -EINVAL; + + shaper_profile = ice_shaper_profile_search(dev, shaper_profile_id); + + if (!shaper_profile) { + error->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID; + error->message = "profile ID not exist"; + return -EINVAL; + } + + /* don't delete a profile if it's used by one or several nodes */ + if (shaper_profile->reference_count) { + error->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE; + error->message = "profile in use"; + return -EINVAL; + } + + TAILQ_REMOVE(&pf->tm_conf.shaper_profile_list, shaper_profile, node); + rte_free(shaper_profile); + + return 0; +} + +static int +ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id, + uint32_t parent_node_id, uint32_t priority, + uint32_t weight, uint32_t level_id, + struct rte_tm_node_params *params, + struct rte_tm_error *error) +{ + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + enum ice_tm_node_type node_type = ICE_TM_NODE_TYPE_MAX; + enum ice_tm_node_type parent_node_type = ICE_TM_NODE_TYPE_MAX; + struct ice_tm_shaper_profile *shaper_profile = NULL; + struct ice_tm_node *tm_node; + struct ice_tm_node *parent_node; + uint16_t tc_nb = 1; + int ret; + + if (!params || !error) + return -EINVAL; + + /* if already committed */ + if (pf->tm_conf.committed) { + error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + error->message = "already committed"; + return -EINVAL; + } + + ret = ice_node_param_check(pf, node_id, priority, weight, + params, error); + if (ret) + return ret; + + /* check if the node is already existed */ + if (ice_tm_node_search(dev, node_id, &node_type)) { + error->type = RTE_TM_ERROR_TYPE_NODE_ID; + error->message = "node id already used"; + return -EINVAL; + } + + /* check the shaper profile id */ + if (params->shaper_profile_id != RTE_TM_SHAPER_PROFILE_ID_NONE) { + shaper_profile = ice_shaper_profile_search(dev, + params->shaper_profile_id); + if (!shaper_profile) { + error->type = + RTE_TM_ERROR_TYPE_NODE_PARAMS_SHAPER_PROFILE_ID; + error->message = "shaper profile not exist"; + return -EINVAL; + } + } + + /* root node if not have a parent */ + if (parent_node_id == RTE_TM_NODE_ID_NULL) { + /* check level */ + if (level_id != ICE_TM_NODE_TYPE_PORT) { + error->type = RTE_TM_ERROR_TYPE_NODE_PARAMS; + error->message = "Wrong level"; + return -EINVAL; + } + + /* obviously no more than one root */ + if (pf->tm_conf.root) { + error->type = RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID; + error->message = "already have a root"; + return -EINVAL; + } + + /* add the root node */ + tm_node = rte_zmalloc("ice_tm_node", + sizeof(struct ice_tm_node), + 0); + if (!tm_node) + return -ENOMEM; + tm_node->id = node_id; + tm_node->parent = NULL; + tm_node->reference_count = 0; + rte_memcpy(&tm_node->params, params, + sizeof(struct rte_tm_node_params)); + pf->tm_conf.root = tm_node; + return 0; + } + + /* TC or queue node */ + /* check the parent node */ + parent_node = ice_tm_node_search(dev, parent_node_id, + &parent_node_type); + if (!parent_node) { + error->type = RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID; + error->message = "parent not exist"; + return -EINVAL; + } + if (parent_node_type != ICE_TM_NODE_TYPE_PORT && + parent_node_type != ICE_TM_NODE_TYPE_TC) { + error->type = RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID; + error->message = "parent is not root or TC"; + return -EINVAL; + } + /* check level */ + if (level_id != RTE_TM_NODE_LEVEL_ID_ANY && + level_id != (uint32_t)parent_node_type + 1) { + error->type = RTE_TM_ERROR_TYPE_NODE_PARAMS; + error->message = "Wrong level"; + return -EINVAL; + } + + /* check the node number */ + if (parent_node_type == ICE_TM_NODE_TYPE_PORT) { + /* check the TC number */ + if (pf->tm_conf.nb_tc_node >= tc_nb) { + error->type = RTE_TM_ERROR_TYPE_NODE_ID; + error->message = "too many TCs"; + return -EINVAL; + } + } else { + /* check the queue number */ + if (parent_node->reference_count >= pf->dev_data->nb_tx_queues) { + error->type = RTE_TM_ERROR_TYPE_NODE_ID; + error->message = "too many queues"; + return -EINVAL; + } + if (node_id >= pf->dev_data->nb_tx_queues) { + error->type = RTE_TM_ERROR_TYPE_NODE_ID; + error->message = "too large queue id"; + return -EINVAL; + } + } + + /* add the TC or queue node */ + tm_node = rte_zmalloc("ice_tm_node", + sizeof(struct ice_tm_node), + 0); + if (!tm_node) + return -ENOMEM; + tm_node->id = node_id; + tm_node->priority = priority; + tm_node->weight = weight; + tm_node->reference_count = 0; + tm_node->parent = parent_node; + tm_node->shaper_profile = shaper_profile; + rte_memcpy(&tm_node->params, params, + sizeof(struct rte_tm_node_params)); + if (parent_node_type == ICE_TM_NODE_TYPE_PORT) { + TAILQ_INSERT_TAIL(&pf->tm_conf.tc_list, + tm_node, node); + tm_node->tc = pf->tm_conf.nb_tc_node; + pf->tm_conf.nb_tc_node++; + } else { + TAILQ_INSERT_TAIL(&pf->tm_conf.queue_list, + tm_node, node); + tm_node->tc = parent_node->tc; + pf->tm_conf.nb_queue_node++; + } + tm_node->parent->reference_count++; + + return 0; +} + +static int +ice_tm_node_delete(struct rte_eth_dev *dev, uint32_t node_id, + struct rte_tm_error *error) +{ + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + enum ice_tm_node_type node_type = ICE_TM_NODE_TYPE_MAX; + struct ice_tm_node *tm_node; + + if (!error) + return -EINVAL; + + /* if already committed */ + if (pf->tm_conf.committed) { + error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + error->message = "already committed"; + return -EINVAL; + } + + if (node_id == RTE_TM_NODE_ID_NULL) { + error->type = RTE_TM_ERROR_TYPE_NODE_ID; + error->message = "invalid node id"; + return -EINVAL; + } + + /* check if the node id exists */ + tm_node = ice_tm_node_search(dev, node_id, &node_type); + if (!tm_node) { + error->type = RTE_TM_ERROR_TYPE_NODE_ID; + error->message = "no such node"; + return -EINVAL; + } + + /* the node should have no child */ + if (tm_node->reference_count) { + error->type = RTE_TM_ERROR_TYPE_NODE_ID; + error->message = + "cannot delete a node which has children"; + return -EINVAL; + } + + /* root node */ + if (node_type == ICE_TM_NODE_TYPE_PORT) { + rte_free(tm_node); + pf->tm_conf.root = NULL; + return 0; + } + + /* TC or queue node */ + tm_node->parent->reference_count--; + if (node_type == ICE_TM_NODE_TYPE_TC) { + TAILQ_REMOVE(&pf->tm_conf.tc_list, tm_node, node); + pf->tm_conf.nb_tc_node--; + } else { + TAILQ_REMOVE(&pf->tm_conf.queue_list, tm_node, node); + pf->tm_conf.nb_queue_node--; + } + rte_free(tm_node); + + return 0; +} + +static int ice_hierarchy_commit(struct rte_eth_dev *dev, + int clear_on_fail, + __rte_unused struct rte_tm_error *error) +{ + struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ice_tm_node_list *queue_list = &pf->tm_conf.queue_list; + struct ice_tm_node *tm_node; + struct ice_tx_queue *txq; + struct ice_vsi *vsi; + int ret_val = ICE_SUCCESS; + uint64_t peak = 0; + + TAILQ_FOREACH(tm_node, queue_list, node) { + txq = dev->data->tx_queues[tm_node->id]; + vsi = txq->vsi; + if (tm_node->shaper_profile) + /* Transfer from Byte per seconds to Kbps */ + peak = tm_node->shaper_profile->profile.peak.rate; + + peak = peak / 1000 * BITS_PER_BYTE; + ret_val = ice_cfg_q_bw_lmt(hw->port_info, vsi->idx, + tm_node->tc, tm_node->id, ICE_MAX_BW, (u32)peak); + if (ret_val) { + error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + PMD_DRV_LOG(ERR, "configure queue %u bandwidth failed", tm_node->id); + goto fail_clear; + } + } + + return ret_val; + +fail_clear: + /* clear all the traffic manager configuration */ + if (clear_on_fail) { + ice_tm_conf_uninit(dev); + ice_tm_conf_init(dev); + } + return ret_val; +} diff --git a/drivers/net/ice/meson.build b/drivers/net/ice/meson.build index d608da7765..de307c9e71 100644 --- a/drivers/net/ice/meson.build +++ b/drivers/net/ice/meson.build @@ -12,6 +12,7 @@ sources = files( 'ice_hash.c', 'ice_rxtx.c', 'ice_switch_filter.c', + 'ice_tm.c', ) deps += ['hash', 'net', 'common_iavf'] From patchwork Thu Apr 28 03:30:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 110405 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4317CA0503; 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a="253531282" X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="253531282" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 20:52:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="514044813" Received: from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181]) by orsmga003.jf.intel.com with ESMTP; 27 Apr 2022 20:52:46 -0700 From: Wenjun Wu To: dev@dpdk.org, qiming.yang@intel.com, qi.z.zhang@intel.com Subject: [PATCH v9 5/9] net/ice: support queue group bandwidth limit Date: Thu, 28 Apr 2022 11:30:30 +0800 Message-Id: <20220428033034.3490183-6-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220428033034.3490183-1-wenjun1.wu@intel.com> References: <20220329014813.1092054-1-wenjun1.wu@intel.com> <20220428033034.3490183-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org To set up the exact queue group, we need to reconfigure topology by delete and then recreate queue nodes. This patch adds queue group configuration support and queue group bandwidth limit support. Signed-off-by: Wenjun Wu --- drivers/net/ice/ice_ethdev.h | 9 +- drivers/net/ice/ice_tm.c | 239 ++++++++++++++++++++++++++++++++--- 2 files changed, 232 insertions(+), 16 deletions(-) diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h index 4359c61624..f9f4a1c71b 100644 --- a/drivers/net/ice/ice_ethdev.h +++ b/drivers/net/ice/ice_ethdev.h @@ -474,6 +474,7 @@ struct ice_tm_node { uint32_t weight; uint32_t reference_count; struct ice_tm_node *parent; + struct ice_tm_node **children; struct ice_tm_shaper_profile *shaper_profile; struct rte_tm_node_params params; }; @@ -482,6 +483,8 @@ struct ice_tm_node { enum ice_tm_node_type { ICE_TM_NODE_TYPE_PORT, ICE_TM_NODE_TYPE_TC, + ICE_TM_NODE_TYPE_VSI, + ICE_TM_NODE_TYPE_QGROUP, ICE_TM_NODE_TYPE_QUEUE, ICE_TM_NODE_TYPE_MAX, }; @@ -489,10 +492,14 @@ enum ice_tm_node_type { /* Struct to store all the Traffic Manager configuration. */ struct ice_tm_conf { struct ice_shaper_profile_list shaper_profile_list; - struct ice_tm_node *root; /* root node - vf vsi */ + struct ice_tm_node *root; /* root node - port */ struct ice_tm_node_list tc_list; /* node list for all the TCs */ + struct ice_tm_node_list vsi_list; /* node list for all the VSIs */ + struct ice_tm_node_list qgroup_list; /* node list for all the queue groups */ struct ice_tm_node_list queue_list; /* node list for all the queues */ uint32_t nb_tc_node; + uint32_t nb_vsi_node; + uint32_t nb_qgroup_node; uint32_t nb_queue_node; bool committed; }; diff --git a/drivers/net/ice/ice_tm.c b/drivers/net/ice/ice_tm.c index 383af88981..d70d077286 100644 --- a/drivers/net/ice/ice_tm.c +++ b/drivers/net/ice/ice_tm.c @@ -44,8 +44,12 @@ ice_tm_conf_init(struct rte_eth_dev *dev) TAILQ_INIT(&pf->tm_conf.shaper_profile_list); pf->tm_conf.root = NULL; TAILQ_INIT(&pf->tm_conf.tc_list); + TAILQ_INIT(&pf->tm_conf.vsi_list); + TAILQ_INIT(&pf->tm_conf.qgroup_list); TAILQ_INIT(&pf->tm_conf.queue_list); pf->tm_conf.nb_tc_node = 0; + pf->tm_conf.nb_vsi_node = 0; + pf->tm_conf.nb_qgroup_node = 0; pf->tm_conf.nb_queue_node = 0; pf->tm_conf.committed = false; } @@ -62,6 +66,16 @@ ice_tm_conf_uninit(struct rte_eth_dev *dev) rte_free(tm_node); } pf->tm_conf.nb_queue_node = 0; + while ((tm_node = TAILQ_FIRST(&pf->tm_conf.qgroup_list))) { + TAILQ_REMOVE(&pf->tm_conf.qgroup_list, tm_node, node); + rte_free(tm_node); + } + pf->tm_conf.nb_qgroup_node = 0; + while ((tm_node = TAILQ_FIRST(&pf->tm_conf.vsi_list))) { + TAILQ_REMOVE(&pf->tm_conf.vsi_list, tm_node, node); + rte_free(tm_node); + } + pf->tm_conf.nb_vsi_node = 0; while ((tm_node = TAILQ_FIRST(&pf->tm_conf.tc_list))) { TAILQ_REMOVE(&pf->tm_conf.tc_list, tm_node, node); rte_free(tm_node); @@ -79,6 +93,8 @@ ice_tm_node_search(struct rte_eth_dev *dev, { struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); struct ice_tm_node_list *tc_list = &pf->tm_conf.tc_list; + struct ice_tm_node_list *vsi_list = &pf->tm_conf.vsi_list; + struct ice_tm_node_list *qgroup_list = &pf->tm_conf.qgroup_list; struct ice_tm_node_list *queue_list = &pf->tm_conf.queue_list; struct ice_tm_node *tm_node; @@ -94,6 +110,20 @@ ice_tm_node_search(struct rte_eth_dev *dev, } } + TAILQ_FOREACH(tm_node, vsi_list, node) { + if (tm_node->id == node_id) { + *node_type = ICE_TM_NODE_TYPE_VSI; + return tm_node; + } + } + + TAILQ_FOREACH(tm_node, qgroup_list, node) { + if (tm_node->id == node_id) { + *node_type = ICE_TM_NODE_TYPE_QGROUP; + return tm_node; + } + } + TAILQ_FOREACH(tm_node, queue_list, node) { if (tm_node->id == node_id) { *node_type = ICE_TM_NODE_TYPE_QUEUE; @@ -354,6 +384,7 @@ ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id, struct ice_tm_node *tm_node; struct ice_tm_node *parent_node; uint16_t tc_nb = 1; + uint16_t vsi_nb = 1; int ret; if (!params || !error) @@ -415,6 +446,8 @@ ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id, tm_node->id = node_id; tm_node->parent = NULL; tm_node->reference_count = 0; + tm_node->children = (struct ice_tm_node **) + rte_calloc(NULL, 256, (sizeof(struct ice_tm_node *)), 0); rte_memcpy(&tm_node->params, params, sizeof(struct rte_tm_node_params)); pf->tm_conf.root = tm_node; @@ -431,9 +464,11 @@ ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id, return -EINVAL; } if (parent_node_type != ICE_TM_NODE_TYPE_PORT && - parent_node_type != ICE_TM_NODE_TYPE_TC) { + parent_node_type != ICE_TM_NODE_TYPE_TC && + parent_node_type != ICE_TM_NODE_TYPE_VSI && + parent_node_type != ICE_TM_NODE_TYPE_QGROUP) { error->type = RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID; - error->message = "parent is not root or TC"; + error->message = "parent is not valid"; return -EINVAL; } /* check level */ @@ -452,6 +487,20 @@ ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id, error->message = "too many TCs"; return -EINVAL; } + } else if (parent_node_type == ICE_TM_NODE_TYPE_TC) { + /* check the VSI number */ + if (pf->tm_conf.nb_vsi_node >= vsi_nb) { + error->type = RTE_TM_ERROR_TYPE_NODE_ID; + error->message = "too many VSIs"; + return -EINVAL; + } + } else if (parent_node_type == ICE_TM_NODE_TYPE_VSI) { + /* check the queue group number */ + if (parent_node->reference_count >= pf->dev_data->nb_tx_queues) { + error->type = RTE_TM_ERROR_TYPE_NODE_ID; + error->message = "too many queue groups"; + return -EINVAL; + } } else { /* check the queue number */ if (parent_node->reference_count >= pf->dev_data->nb_tx_queues) { @@ -466,7 +515,7 @@ ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id, } } - /* add the TC or queue node */ + /* add the TC or VSI or queue group or queue node */ tm_node = rte_zmalloc("ice_tm_node", sizeof(struct ice_tm_node), 0); @@ -478,6 +527,10 @@ ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id, tm_node->reference_count = 0; tm_node->parent = parent_node; tm_node->shaper_profile = shaper_profile; + tm_node->children = (struct ice_tm_node **) + rte_calloc(NULL, 256, (sizeof(struct ice_tm_node *)), 0); + tm_node->parent->children[tm_node->parent->reference_count] = tm_node; + rte_memcpy(&tm_node->params, params, sizeof(struct rte_tm_node_params)); if (parent_node_type == ICE_TM_NODE_TYPE_PORT) { @@ -485,10 +538,20 @@ ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id, tm_node, node); tm_node->tc = pf->tm_conf.nb_tc_node; pf->tm_conf.nb_tc_node++; + } else if (parent_node_type == ICE_TM_NODE_TYPE_TC) { + TAILQ_INSERT_TAIL(&pf->tm_conf.vsi_list, + tm_node, node); + tm_node->tc = parent_node->tc; + pf->tm_conf.nb_vsi_node++; + } else if (parent_node_type == ICE_TM_NODE_TYPE_VSI) { + TAILQ_INSERT_TAIL(&pf->tm_conf.qgroup_list, + tm_node, node); + tm_node->tc = parent_node->parent->tc; + pf->tm_conf.nb_qgroup_node++; } else { TAILQ_INSERT_TAIL(&pf->tm_conf.queue_list, tm_node, node); - tm_node->tc = parent_node->tc; + tm_node->tc = parent_node->parent->parent->tc; pf->tm_conf.nb_queue_node++; } tm_node->parent->reference_count++; @@ -543,11 +606,17 @@ ice_tm_node_delete(struct rte_eth_dev *dev, uint32_t node_id, return 0; } - /* TC or queue node */ + /* TC or VSI or queue group or queue node */ tm_node->parent->reference_count--; if (node_type == ICE_TM_NODE_TYPE_TC) { TAILQ_REMOVE(&pf->tm_conf.tc_list, tm_node, node); pf->tm_conf.nb_tc_node--; + } else if (node_type == ICE_TM_NODE_TYPE_VSI) { + TAILQ_REMOVE(&pf->tm_conf.vsi_list, tm_node, node); + pf->tm_conf.nb_vsi_node--; + } else if (node_type == ICE_TM_NODE_TYPE_QGROUP) { + TAILQ_REMOVE(&pf->tm_conf.qgroup_list, tm_node, node); + pf->tm_conf.nb_qgroup_node--; } else { TAILQ_REMOVE(&pf->tm_conf.queue_list, tm_node, node); pf->tm_conf.nb_queue_node--; @@ -557,36 +626,176 @@ ice_tm_node_delete(struct rte_eth_dev *dev, uint32_t node_id, return 0; } +static int ice_move_recfg_lan_txq(struct rte_eth_dev *dev, + struct ice_sched_node *queue_sched_node, + struct ice_sched_node *dst_node, + uint16_t queue_id) +{ + struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ice_aqc_move_txqs_data *buf; + struct ice_sched_node *queue_parent_node; + uint8_t txqs_moved; + int ret = ICE_SUCCESS; + uint16_t buf_size = ice_struct_size(buf, txqs, 1); + + buf = (struct ice_aqc_move_txqs_data *)ice_malloc(hw, sizeof(*buf)); + + queue_parent_node = queue_sched_node->parent; + buf->src_teid = queue_parent_node->info.node_teid; + buf->dest_teid = dst_node->info.node_teid; + buf->txqs[0].q_teid = queue_sched_node->info.node_teid; + buf->txqs[0].txq_id = queue_id; + + ret = ice_aq_move_recfg_lan_txq(hw, 1, true, false, false, false, 50, + NULL, buf, buf_size, &txqs_moved, NULL); + if (ret || txqs_moved == 0) { + PMD_DRV_LOG(ERR, "move lan queue %u failed", queue_id); + return ICE_ERR_PARAM; + } + + if (queue_parent_node->num_children > 0) { + queue_parent_node->num_children--; + queue_parent_node->children[queue_parent_node->num_children] = NULL; + } else { + PMD_DRV_LOG(ERR, "invalid children number %d for queue %u", + queue_parent_node->num_children, queue_id); + return ICE_ERR_PARAM; + } + dst_node->children[dst_node->num_children++] = queue_sched_node; + queue_sched_node->parent = dst_node; + ice_sched_query_elem(hw, queue_sched_node->info.node_teid, &queue_sched_node->info); + + return ret; +} + static int ice_hierarchy_commit(struct rte_eth_dev *dev, int clear_on_fail, __rte_unused struct rte_tm_error *error) { struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ice_tm_node_list *qgroup_list = &pf->tm_conf.qgroup_list; struct ice_tm_node_list *queue_list = &pf->tm_conf.queue_list; struct ice_tm_node *tm_node; + struct ice_sched_node *node; + struct ice_sched_node *vsi_node; + struct ice_sched_node *queue_node; struct ice_tx_queue *txq; struct ice_vsi *vsi; int ret_val = ICE_SUCCESS; uint64_t peak = 0; + uint32_t i; + uint32_t idx_vsi_child; + uint32_t idx_qg; + uint32_t nb_vsi_child; + uint32_t nb_qg; + uint32_t qid; + uint32_t q_teid; + uint32_t vsi_layer; + + for (i = 0; i < dev->data->nb_tx_queues; i++) { + ret_val = ice_tx_queue_stop(dev, i); + if (ret_val) { + error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + PMD_DRV_LOG(ERR, "stop queue %u failed", i); + goto fail_clear; + } + } - TAILQ_FOREACH(tm_node, queue_list, node) { - txq = dev->data->tx_queues[tm_node->id]; - vsi = txq->vsi; - if (tm_node->shaper_profile) + node = hw->port_info->root; + vsi_layer = hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET; + for (i = 0; i < vsi_layer; i++) + node = node->children[0]; + vsi_node = node; + nb_vsi_child = vsi_node->num_children; + nb_qg = vsi_node->children[0]->num_children; + + idx_vsi_child = 0; + idx_qg = 0; + + TAILQ_FOREACH(tm_node, qgroup_list, node) { + struct ice_tm_node *tm_child_node; + struct ice_sched_node *qgroup_sched_node = + vsi_node->children[idx_vsi_child]->children[idx_qg]; + + for (i = 0; i < tm_node->reference_count; i++) { + tm_child_node = tm_node->children[i]; + qid = tm_child_node->id; + ret_val = ice_tx_queue_start(dev, qid); + if (ret_val) { + error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + PMD_DRV_LOG(ERR, "start queue %u failed", qid); + goto fail_clear; + } + txq = dev->data->tx_queues[qid]; + q_teid = txq->q_teid; + queue_node = ice_sched_get_node(hw->port_info, q_teid); + if (queue_node == NULL) { + error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + PMD_DRV_LOG(ERR, "get queue %u node failed", qid); + goto fail_clear; + } + if (queue_node->info.parent_teid == qgroup_sched_node->info.node_teid) + continue; + ret_val = ice_move_recfg_lan_txq(dev, queue_node, qgroup_sched_node, qid); + if (ret_val) { + error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + PMD_DRV_LOG(ERR, "move queue %u failed", qid); + goto fail_clear; + } + } + if (tm_node->reference_count != 0 && tm_node->shaper_profile) { + uint32_t node_teid = qgroup_sched_node->info.node_teid; /* Transfer from Byte per seconds to Kbps */ peak = tm_node->shaper_profile->profile.peak.rate; - - peak = peak / 1000 * BITS_PER_BYTE; - ret_val = ice_cfg_q_bw_lmt(hw->port_info, vsi->idx, - tm_node->tc, tm_node->id, ICE_MAX_BW, (u32)peak); - if (ret_val) { + peak = peak / 1000 * BITS_PER_BYTE; + ret_val = ice_sched_set_node_bw_lmt_per_tc(hw->port_info, + node_teid, + ICE_AGG_TYPE_Q, + tm_node->tc, + ICE_MAX_BW, + (u32)peak); + if (ret_val) { + error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + PMD_DRV_LOG(ERR, + "configure queue group %u bandwidth failed", + tm_node->id); + goto fail_clear; + } + } + idx_qg++; + if (idx_qg >= nb_qg) { + idx_qg = 0; + idx_vsi_child++; + } + if (idx_vsi_child >= nb_vsi_child) { error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; - PMD_DRV_LOG(ERR, "configure queue %u bandwidth failed", tm_node->id); + PMD_DRV_LOG(ERR, "too many queues"); goto fail_clear; } } + TAILQ_FOREACH(tm_node, queue_list, node) { + qid = tm_node->id; + txq = dev->data->tx_queues[qid]; + vsi = txq->vsi; + if (tm_node->shaper_profile) { + /* Transfer from Byte per seconds to Kbps */ + peak = tm_node->shaper_profile->profile.peak.rate; + peak = peak / 1000 * BITS_PER_BYTE; + ret_val = ice_cfg_q_bw_lmt(hw->port_info, vsi->idx, + tm_node->tc, tm_node->id, + ICE_MAX_BW, (u32)peak); + if (ret_val) { + error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + PMD_DRV_LOG(ERR, + "configure queue %u bandwidth failed", + tm_node->id); + goto fail_clear; + } + } + } + return ret_val; fail_clear: From patchwork Thu Apr 28 03:30:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 110404 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 136B3A0503; Thu, 28 Apr 2022 05:53:19 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C436C42807; Thu, 28 Apr 2022 05:52:55 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 5B8D7427F4 for ; Thu, 28 Apr 2022 05:52:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651117972; x=1682653972; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=uum2pRlzio5gsVpOhps/eoKTw3EdL0ghijuFA1MBGM4=; b=VYqLEuhcvtzv/3BTaZjYBXB5bfOwoPtc6Te5oZM9niQZwHUiJ67UPdb1 vhnSm0UYb+UyFwaAomf0FF5xwU/kc57Jt3Nf1sOJ0Ijb5jZ4Af2jd+OfD 0EhxmOnluqypv4bjLlp5rPP3nJX52tr2D9n7uNcGBNMJncEJMro6CI6d/ l3A6JBSlt8pXhQVqH8wSxG6SOq0RQgDwxZrOGGA77u463oSshTpTwVkBz lG8evDXmOQTyXlLP08TMqKcQRCd/1xRkk38iTrfO0C8bCQd7pq67036D9 RK45bhTYnM+c1YXiXHbuQhaRE9I7xZ1z7PUMo3OQC7ild59pesnWC7kOp A==; X-IronPort-AV: E=McAfee;i="6400,9594,10330"; a="253531283" X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="253531283" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 20:52:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="514044821" Received: from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181]) by orsmga003.jf.intel.com with ESMTP; 27 Apr 2022 20:52:48 -0700 From: Wenjun Wu To: dev@dpdk.org, qiming.yang@intel.com, qi.z.zhang@intel.com Subject: [PATCH v9 6/9] net/ice: support queue priority configuration Date: Thu, 28 Apr 2022 11:30:31 +0800 Message-Id: <20220428033034.3490183-7-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220428033034.3490183-1-wenjun1.wu@intel.com> References: <20220329014813.1092054-1-wenjun1.wu@intel.com> <20220428033034.3490183-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds queue priority configuration support. The highest priority is 0, and the lowest priority is 7. Signed-off-by: Wenjun Wu --- drivers/net/ice/ice_tm.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/ice_tm.c b/drivers/net/ice/ice_tm.c index d70d077286..91e420d653 100644 --- a/drivers/net/ice/ice_tm.c +++ b/drivers/net/ice/ice_tm.c @@ -147,9 +147,9 @@ ice_node_param_check(struct ice_pf *pf, uint32_t node_id, return -EINVAL; } - if (priority) { + if (priority >= 8) { error->type = RTE_TM_ERROR_TYPE_NODE_PRIORITY; - error->message = "priority should be 0"; + error->message = "priority should be less than 8"; return -EINVAL; } @@ -684,6 +684,7 @@ static int ice_hierarchy_commit(struct rte_eth_dev *dev, struct ice_vsi *vsi; int ret_val = ICE_SUCCESS; uint64_t peak = 0; + uint8_t priority; uint32_t i; uint32_t idx_vsi_child; uint32_t idx_qg; @@ -779,6 +780,7 @@ static int ice_hierarchy_commit(struct rte_eth_dev *dev, qid = tm_node->id; txq = dev->data->tx_queues[qid]; vsi = txq->vsi; + q_teid = txq->q_teid; if (tm_node->shaper_profile) { /* Transfer from Byte per seconds to Kbps */ peak = tm_node->shaper_profile->profile.peak.rate; @@ -794,6 +796,14 @@ static int ice_hierarchy_commit(struct rte_eth_dev *dev, goto fail_clear; } } + priority = 7 - tm_node->priority; + ret_val = ice_cfg_vsi_q_priority(hw->port_info, 1, + &q_teid, &priority); + if (ret_val) { + error->type = RTE_TM_ERROR_TYPE_NODE_PRIORITY; + PMD_DRV_LOG(ERR, "configure queue %u priority failed", tm_node->priority); + goto fail_clear; + } } return ret_val; From patchwork Thu Apr 28 03:30:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 110406 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B4486A0503; Thu, 28 Apr 2022 05:53:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9586742815; Thu, 28 Apr 2022 05:52:57 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 892BC410F3 for ; Thu, 28 Apr 2022 05:52:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651117972; x=1682653972; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=6OLUIV174at4F4njhX0qaYOMqYxbof2gefBbfythGek=; b=YiIWR+L1hfYKYSzOJy2aJ+MiZ+b0YInFRSaUtoHmHZPBmnj0SDJRDd5e i5o04NbgSOY/5cpUI3YbZthfMuEq/Go0alVH3i2rVVbXQZbsP2wwDj6kE IddyocARQ8I9DxJO6UKKSYF+HHVSQtdvdFCpbBeNn8xw2EFuMjh0+0eZK Q3UktUrnjOhP3cvKxfDslIqenm/9U+1h+waUWWxRySJ8aCOs4s+GMJc56 XC8wOyrFJ1N6vBRuQBfm7j6SD2+tcbRxSo+rfPDJsGlNJ8n8a3NCeTd4H pswPIAjE3q1bMWizf2TC5hGNQO2/yqHtINWRqgZr4mumsl3evBDnHnabT A==; X-IronPort-AV: E=McAfee;i="6400,9594,10330"; a="253531284" X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="253531284" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 20:52:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="514044830" Received: from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181]) by orsmga003.jf.intel.com with ESMTP; 27 Apr 2022 20:52:49 -0700 From: Wenjun Wu To: dev@dpdk.org, qiming.yang@intel.com, qi.z.zhang@intel.com Subject: [PATCH v9 7/9] net/ice: support queue weight configuration Date: Thu, 28 Apr 2022 11:30:32 +0800 Message-Id: <20220428033034.3490183-8-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220428033034.3490183-1-wenjun1.wu@intel.com> References: <20220329014813.1092054-1-wenjun1.wu@intel.com> <20220428033034.3490183-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds queue weight configuration support. Signed-off-by: Wenjun Wu --- drivers/net/ice/ice_tm.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/ice_tm.c b/drivers/net/ice/ice_tm.c index 91e420d653..4d7bb9102c 100644 --- a/drivers/net/ice/ice_tm.c +++ b/drivers/net/ice/ice_tm.c @@ -153,9 +153,9 @@ ice_node_param_check(struct ice_pf *pf, uint32_t node_id, return -EINVAL; } - if (weight != 1) { + if (weight > 200 || weight < 1) { error->type = RTE_TM_ERROR_TYPE_NODE_WEIGHT; - error->message = "weight must be 1"; + error->message = "weight must be between 1 and 200"; return -EINVAL; } @@ -804,6 +804,15 @@ static int ice_hierarchy_commit(struct rte_eth_dev *dev, PMD_DRV_LOG(ERR, "configure queue %u priority failed", tm_node->priority); goto fail_clear; } + + ret_val = ice_cfg_q_bw_alloc(hw->port_info, vsi->idx, + tm_node->tc, tm_node->id, + ICE_MAX_BW, (u32)tm_node->weight); + if (ret_val) { + error->type = RTE_TM_ERROR_TYPE_NODE_WEIGHT; + PMD_DRV_LOG(ERR, "configure queue %u weight failed", tm_node->weight); + goto fail_clear; + } } return ret_val; From patchwork Thu Apr 28 03:30:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 110407 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B4CC4A0503; Thu, 28 Apr 2022 05:53:36 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CDCC642821; Thu, 28 Apr 2022 05:52:58 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id F25D8427F7 for ; Thu, 28 Apr 2022 05:52:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651117973; x=1682653973; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=hI498RhFk32E++GG9QEjfIi1EDurQQi+TtHssRWjSVk=; b=F+B10BZRo7Ipjw9OhMfiTFKFl9c53ksk6I7Rj4ZjHpIFDi2Ceds34krP u2mVieyH70M7WalrB9G6vZnwdHoGnDbToWUcV9py05NhEhQRjISZM/JFk rwDfOx4wFRIBb8YHmQAHTygOuRfmRPAECtNLSkfc9T1eg51WyYYifgbZE UvT6lgr4WY796Z844WAHVvbkvDX8zePrlkbZcMxuDKnZ0ETXGMlfzChN0 vz4h3wlKgeKQ/HWvPZsrgD/z1rXWIkWZxFcobql2RESkBJ2gZnK7RIbMO THMgBMYi8YS90zGSGquLbfOHfl2t7FD7vwHzThHagKb/YQd/z1gYSC6Px g==; X-IronPort-AV: E=McAfee;i="6400,9594,10330"; a="253531286" X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="253531286" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 20:52:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="514044838" Received: from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181]) by orsmga003.jf.intel.com with ESMTP; 27 Apr 2022 20:52:50 -0700 From: Wenjun Wu To: dev@dpdk.org, qiming.yang@intel.com, qi.z.zhang@intel.com Subject: [PATCH v9 8/9] net/ice: support queue group priority configuration Date: Thu, 28 Apr 2022 11:30:33 +0800 Message-Id: <20220428033034.3490183-9-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220428033034.3490183-1-wenjun1.wu@intel.com> References: <20220329014813.1092054-1-wenjun1.wu@intel.com> <20220428033034.3490183-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds queue group priority configuration support. Signed-off-by: Wenjun Wu --- drivers/net/ice/ice_tm.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/ice/ice_tm.c b/drivers/net/ice/ice_tm.c index 4d7bb9102c..f604523ead 100644 --- a/drivers/net/ice/ice_tm.c +++ b/drivers/net/ice/ice_tm.c @@ -764,6 +764,15 @@ static int ice_hierarchy_commit(struct rte_eth_dev *dev, goto fail_clear; } } + priority = 7 - tm_node->priority; + ret_val = ice_sched_cfg_sibl_node_prio_lock(hw->port_info, qgroup_sched_node, + priority); + if (ret_val) { + error->type = RTE_TM_ERROR_TYPE_NODE_PRIORITY; + PMD_DRV_LOG(ERR, "configure queue group %u priority failed", + tm_node->priority); + goto fail_clear; + } idx_qg++; if (idx_qg >= nb_qg) { idx_qg = 0; From patchwork Thu Apr 28 03:30:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 110408 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4D333A0503; Thu, 28 Apr 2022 05:53:42 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CA43E42825; Thu, 28 Apr 2022 05:52:59 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 3DF8E410F3 for ; Thu, 28 Apr 2022 05:52:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651117973; x=1682653973; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=/M019FDNWIGRZ3mNxqCSj/yo7+1eUnpvPcaTXr5vPjw=; b=BgS3JmhhDHp+x+cnDoS4o7C3fX3xfra7+KDyV16+2roBgr1BbEnx/Dx3 kTeDKz4R/rCI7UuMsnmHTzhSOebGgwUKOI7Yr1Sz4MBL7Wry4h7dDGCKQ 74FXDgbeS0N4MmJ0gqwvv4uJPZJsD9/E+f6npEqHfDfzQDT+lwj4T/0+e BHzV7gfNBztl0A63WErKVT5BJNOANl15MOTddVhINYYj1n6VZmSYpiUPS g4gorPVV2OV/mVp6PelQbfVfHR7lv5o4O0kNa12T0TRcmpt6gFRvP6ZSh EnfSOwL0xbRxiSaop9C2/B8ZfsfnbTrF8RcRzepwl93gVd6O7+S5a26zC A==; X-IronPort-AV: E=McAfee;i="6400,9594,10330"; a="253531287" X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="253531287" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 20:52:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="514044845" Received: from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181]) by orsmga003.jf.intel.com with ESMTP; 27 Apr 2022 20:52:51 -0700 From: Wenjun Wu To: dev@dpdk.org, qiming.yang@intel.com, qi.z.zhang@intel.com Subject: [PATCH v9 9/9] net/ice: add warning log for unsupported configuration Date: Thu, 28 Apr 2022 11:30:34 +0800 Message-Id: <20220428033034.3490183-10-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220428033034.3490183-1-wenjun1.wu@intel.com> References: <20220329014813.1092054-1-wenjun1.wu@intel.com> <20220428033034.3490183-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Priority configuration is enabled in level 3 and level 4. Weight configuration is enabled in level 4. This patch adds warning log for unsupported priority and weight configuration. Signed-off-by: Wenjun Wu --- drivers/net/ice/ice_tm.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/ice/ice_tm.c b/drivers/net/ice/ice_tm.c index f604523ead..34a0bfcff8 100644 --- a/drivers/net/ice/ice_tm.c +++ b/drivers/net/ice/ice_tm.c @@ -531,6 +531,15 @@ ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id, rte_calloc(NULL, 256, (sizeof(struct ice_tm_node *)), 0); tm_node->parent->children[tm_node->parent->reference_count] = tm_node; + if (tm_node->priority != 0 && level_id != ICE_TM_NODE_TYPE_QUEUE && + level_id != ICE_TM_NODE_TYPE_QGROUP) + PMD_DRV_LOG(WARNING, "priority != 0 not supported in level %d", + level_id); + + if (tm_node->weight != 1 && level_id != ICE_TM_NODE_TYPE_QUEUE) + PMD_DRV_LOG(WARNING, "weight != 1 not supported in level %d", + level_id); + rte_memcpy(&tm_node->params, params, sizeof(struct rte_tm_node_params)); if (parent_node_type == ICE_TM_NODE_TYPE_PORT) {