From patchwork Mon May 16 20:48:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 111197 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 66B26A00BE; Mon, 16 May 2022 22:56:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1D3654282F; Mon, 16 May 2022 22:56:26 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 143274068B for ; Mon, 16 May 2022 22:56:22 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652734583; x=1684270583; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=SOB7V4bUlGJPlI+ThJWGImRZnrsPDWN5s3ozefTatvk=; b=OnrGg4w8EhMW9z4SQrdg1IgQeKNojNyqskxDRtNU7hKcchoQ1EPbDwyw 5tGClA/54Va5Yufi9NpGvnuzWGn6RQfgpJzVzMekBabeTVBLIQNxxa8O6 04jphQbp947xLfbw1rRUybNMxhRalI8BNb+ZrYXnoFnRrfK2nql26iCGK XILSoocqqDFGvb8REzH+EO7tiCUuxxM0+wo6YKW6UFFIyEV60CIDVUcug umhvy5MWAcAVK+3Z8o/ueSAfATKTd+Z6Ytq+xpQ02gKN9KawsXR1J97Fx 2GrUb0vUd9iaMIShGP/jPlujMh7OVCbmUfG0wsJ51cqUTU4Ckb+z2Y169 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10349"; a="251476092" X-IronPort-AV: E=Sophos;i="5.91,230,1647327600"; d="scan'208";a="251476092" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2022 13:56:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,230,1647327600"; d="scan'208";a="574199166" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by fmsmga007.fm.intel.com with ESMTP; 16 May 2022 13:56:21 -0700 From: Nicolas Chautru To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: thomas@monjalon.net, ray.kinsella@intel.com, bruce.richardson@intel.com, hemant.agrawal@nxp.com, hernan.vargas@intel.com, david.marchand@redhat.com, Nicolas Chautru Subject: [PATCH v3 1/4] baseband/acc100: introduce PMD for ACC101 Date: Mon, 16 May 2022 13:48:30 -0700 Message-Id: <1652734113-124047-2-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1652734113-124047-1-git-send-email-nicolas.chautru@intel.com> References: <1651083423-33202-1-git-send-email-nicolas.chautru@intel.com> <1652734113-124047-1-git-send-email-nicolas.chautru@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Support for ACC101 as a derivative of ACC100. Reusing existing code when possible. Signed-off-by: Nicolas Chautru --- doc/guides/bbdevs/acc101.rst | 237 +++++++++++++++++++++++++++++++ doc/guides/bbdevs/features/acc101.ini | 13 ++ doc/guides/bbdevs/index.rst | 1 + doc/guides/rel_notes/release_22_07.rst | 4 + drivers/baseband/acc100/rte_acc100_pmd.c | 194 ++++++++++++++++++++++++- drivers/baseband/acc100/rte_acc100_pmd.h | 6 + drivers/baseband/acc100/rte_acc101_pmd.h | 65 +++++++++ 7 files changed, 515 insertions(+), 5 deletions(-) create mode 100644 doc/guides/bbdevs/acc101.rst create mode 100644 doc/guides/bbdevs/features/acc101.ini create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h diff --git a/doc/guides/bbdevs/acc101.rst b/doc/guides/bbdevs/acc101.rst new file mode 100644 index 0000000..46c310b --- /dev/null +++ b/doc/guides/bbdevs/acc101.rst @@ -0,0 +1,237 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2020 Intel Corporation + +Intel(R) ACC101 5G/4G FEC Poll Mode Driver +========================================== + +The BBDEV ACC101 5G/4G FEC poll mode driver (PMD) supports an +implementation of a VRAN FEC wireless acceleration function. +This device is also known as Mount Cirrus. +This is a follow-up to Mount Bryce (ACC100) and includes fixes, improved +feature set for error scenarios and performance capacity increase. + +Features +-------- + +ACC101 5G/4G FEC PMD supports the following features: + +- LDPC Encode in the DL (5GNR) +- LDPC Decode in the UL (5GNR) +- Turbo Encode in the DL (4G) +- Turbo Decode in the UL (4G) +- 16 VFs per PF (physical device) +- Maximum of 128 queues per VF +- PCIe Gen-3 x16 Interface +- MSI +- SR-IOV + +ACC101 5G/4G FEC PMD supports the following BBDEV capabilities: + +* For the LDPC encode operation: + - ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s) + - ``RTE_BBDEV_LDPC_RATE_MATCH`` : if set then do not do Rate Match bypass + - ``RTE_BBDEV_LDPC_INTERLEAVER_BYPASS`` : if set then bypass interleaver + +* For the LDPC decode operation: + - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK`` : check CRC24B from CB(s) + - ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE`` : disable early termination + - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP`` : drops CRC24B bits appended while decoding + - ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE`` : provides an input for HARQ combining + - ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE`` : provides an input for HARQ combining + - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE`` : HARQ memory input is internal + - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE`` : HARQ memory output is internal + - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK`` : loopback data to/from HARQ memory + - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS`` : HARQ memory includes the fillers bits + - ``RTE_BBDEV_LDPC_DEC_SCATTER_GATHER`` : supports scatter-gather for input/output data + - ``RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION`` : supports compression of the HARQ input/output + - ``RTE_BBDEV_LDPC_LLR_COMPRESSION`` : supports LLR input compression + +* For the turbo encode operation: + - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s) + - ``RTE_BBDEV_TURBO_RATE_MATCH`` : if set then do not do Rate Match bypass + - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS`` : set for encoder dequeue interrupts + - ``RTE_BBDEV_TURBO_RV_INDEX_BYPASS`` : set to bypass RV index + - ``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER`` : supports scatter-gather for input/output data + +* For the turbo decode operation: + - ``RTE_BBDEV_TURBO_CRC_TYPE_24B`` : check CRC24B from CB(s) + - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE`` : perform subblock de-interleave + - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS`` : set for decoder dequeue interrupts + - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN`` : set if negative LLR encoder i/p is supported + - ``RTE_BBDEV_TURBO_POS_LLR_1_BIT_IN`` : set if positive LLR encoder i/p is supported + - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP`` : keep CRC24B bits appended while decoding + - ``RTE_BBDEV_TURBO_DEC_CRC_24B_DROP`` : option to drop the code block CRC after decoding + - ``RTE_BBDEV_TURBO_EARLY_TERMINATION`` : set early termination feature + - ``RTE_BBDEV_TURBO_DEC_SCATTER_GATHER`` : supports scatter-gather for input/output data + - ``RTE_BBDEV_TURBO_HALF_ITERATION_EVEN`` : set half iteration granularity + +Installation +------------ + +Section 3 of the DPDK manual provides instructions on installing and compiling DPDK. + +DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual. +The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The +hugepage configuration of a server may be examined using: + +.. code-block:: console + + grep Huge* /proc/meminfo + + +Initialization +-------------- + +When the device first powers up, its PCI Physical Functions (PF) can be listed through this command: + +.. code-block:: console + + sudo lspci -vd8086:57c4 + +The physical and virtual functions are compatible with Linux UIO drivers: +``vfio`` and ``igb_uio``. However, in order to work the ACC101 5G/4G +FEC device first needs to be bound to one of these linux drivers through DPDK. + + +Bind PF UIO driver(s) +~~~~~~~~~~~~~~~~~~~~~ + +Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use +``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver. + +The igb_uio driver may be bound to the PF PCI device using one of two methods: + + +1. PCI functions (physical or virtual, depending on the use case) can be bound to +the UIO driver by repeating this command for every function. + +.. code-block:: console + + cd + insmod ./build/kmod/igb_uio.ko + echo "8086 57c4" > /sys/bus/pci/drivers/igb_uio/new_id + lspci -vd8086:57c4 + + +2. Another way to bind PF with DPDK UIO driver is by using the ``dpdk-devbind.py`` tool + +.. code-block:: console + + cd + ./usertools/dpdk-devbind.py -b igb_uio 0000:06:00.0 + +where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:57c4 + + +In a similar way the ACC101 5G/4G FEC PF may be bound with vfio-pci as any PCIe device. + + +Enable Virtual Functions +~~~~~~~~~~~~~~~~~~~~~~~~ + +Now, it should be visible in the printouts that PCI PF is under igb_uio control +"``Kernel driver in use: igb_uio``" + +To show the number of available VFs on the device, read ``sriov_totalvfs`` file.. + +.. code-block:: console + + cat /sys/bus/pci/devices/0000\:\:./sriov_totalvfs + + where 0000\:\:. is the PCI device ID + + +To enable VFs via igb_uio, echo the number of virtual functions intended to +enable to ``max_vfs`` file.. + +.. code-block:: console + + echo > /sys/bus/pci/devices/0000\:\:./max_vfs + + +Afterwards, all VFs must be bound to appropriate UIO drivers as required, same +way it was done with the physical function previously. + +Enabling SR-IOV via vfio driver is pretty much the same, except that the file +name is different: + +.. code-block:: console + + echo > /sys/bus/pci/devices/0000\:\:./sriov_numvfs + + +Configure the VFs through PF +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The PCI virtual functions must be configured before working or getting assigned +to VMs/Containers. The configuration involves allocating the number of hardware +queues, priorities, load balance, bandwidth and other settings necessary for the +device to perform FEC functions. + +This configuration needs to be executed at least once after reboot or PCI FLR and can +be achieved by using the function ``acc101_configure()``, which sets up the +parameters defined in ``acc100_conf`` structure. + +Test Application +---------------- + +BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing +the functionality of ACC101 5G/4G FEC encode and decode, depending on the device's +capabilities. The test application is located under app->test-bbdev folder and has the +following options: + +.. code-block:: console + + "-p", "--testapp-path": specifies path to the bbdev test app. + "-e", "--eal-params" : EAL arguments which are passed to the test app. + "-t", "--timeout" : Timeout in seconds (default=300). + "-c", "--test-cases" : Defines test cases to run. Run all if not specified. + "-v", "--test-vector" : Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data). + "-n", "--num-ops" : Number of operations to process on device (default=32). + "-b", "--burst-size" : Operations enqueue/dequeue burst size (default=32). + "-s", "--snr" : SNR in dB used when generating LLRs for bler tests. + "-s", "--iter_max" : Number of iterations for LDPC decoder. + "-l", "--num-lcores" : Number of lcores to run (default=16). + "-i", "--init-device" : Initialise PF device with default values. + + +To execute the test application tool using simple decode or encode data, +type one of the following: + +.. code-block:: console + + ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_dec_default.data + ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_enc_default.data + + +The test application ``test-bbdev.py``, supports the ability to configure the PF device with +a default set of values, if the "-i" or "- -init-device" option is included. The default values +are defined in test_bbdev_perf.c. + + +Test Vectors +~~~~~~~~~~~~ + +In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides +a range of additional tests under the test_vectors folder, which may be useful. The results +of these tests will depend on the ACC101 5G/4G FEC capabilities which may cause some +testcases to be skipped, but no failure should be reported. + + +Alternate Baseband Device configuration tool +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +On top of the embedded configuration feature supported in test-bbdev using "- -init-device" +option mentioned above, there is also a tool available to perform that device configuration +using a companion application. +The ``pf_bb_config`` application notably enables then to run bbdev-test from the VF +and not only limited to the PF as captured above. + +See for more details: https://github.com/intel/pf-bb-config + +Specifically for the BBDEV ACC101 PMD, the command below can be used: + +.. code-block:: console + + ./pf_bb_config ACC101 -c acc101/acc101_config_4vf_4g5g.cfg + ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -l 1 -v ./ldpc_dec_default.data \ No newline at end of file diff --git a/doc/guides/bbdevs/features/acc101.ini b/doc/guides/bbdevs/features/acc101.ini new file mode 100644 index 0000000..0e2c21a --- /dev/null +++ b/doc/guides/bbdevs/features/acc101.ini @@ -0,0 +1,13 @@ +; +; Supported features of the 'acc101' bbdev driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] +Turbo Decoder (4G) = Y +Turbo Encoder (4G) = Y +LDPC Decoder (5G) = Y +LDPC Encoder (5G) = Y +LLR/HARQ Compression = Y +External DDR Access = Y +HW Accelerated = Y diff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst index cedd706..e76883c 100644 --- a/doc/guides/bbdevs/index.rst +++ b/doc/guides/bbdevs/index.rst @@ -14,4 +14,5 @@ Baseband Device Drivers fpga_lte_fec fpga_5gnr_fec acc100 + acc101 la12xx diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index 42a5f2d..ef9906b 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -55,6 +55,10 @@ New Features Also, make sure to start the actual text at the margin. ======================================================= +* **Added Intel ACC101 baseband PMD.** + + * Added a new baseband PMD for Intel ACC101 device (Mount Cirrus). + * See the :doc:`../bbdevs/acc101` for more details. Removed Items ------------- diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index de7e4bc..fca27ef 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -22,6 +22,7 @@ #include #include #include "rte_acc100_pmd.h" +#include "rte_acc101_pmd.h" #ifdef RTE_LIBRTE_BBDEV_DEBUG RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG); @@ -1286,6 +1287,12 @@ RTE_BBDEV_TURBO_HALF_ITERATION_EVEN); } +static inline bool +is_acc100(struct acc100_queue *q) +{ + return (q->d->device_variant == ACC100_VARIANT); +} + /* Fill in a frame control word for LDPC decoding. */ static inline void acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, @@ -1412,6 +1419,139 @@ } } +/* Convert offset to harq index for harq_layout structure */ +static inline uint32_t hq_index(uint32_t offset) +{ + return (offset >> ACC100_HARQ_OFFSET_SHIFT) & ACC100_HARQ_OFFSET_MASK; +} + +/* Fill in a frame control word for LDPC decoding for ACC101 */ +static inline void +acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, + union acc100_harq_layout_data *harq_layout) +{ + uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset; + uint32_t harq_index; + uint32_t l; + + fcw->qm = op->ldpc_dec.q_m; + fcw->nfiller = op->ldpc_dec.n_filler; + fcw->BG = (op->ldpc_dec.basegraph - 1); + fcw->Zc = op->ldpc_dec.z_c; + fcw->ncb = op->ldpc_dec.n_cb; + fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph, + op->ldpc_dec.rv_index); + if (op->ldpc_dec.code_block_mode == RTE_BBDEV_CODE_BLOCK) + fcw->rm_e = op->ldpc_dec.cb_params.e; + else + fcw->rm_e = (op->ldpc_dec.tb_params.r < + op->ldpc_dec.tb_params.cab) ? + op->ldpc_dec.tb_params.ea : + op->ldpc_dec.tb_params.eb; + + if (unlikely(check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) && + (op->ldpc_dec.harq_combined_input.length == 0))) { + rte_bbdev_log(WARNING, "Null HARQ input size provided"); + /* Disable HARQ input in that case to carry forward */ + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; + } + + fcw->hcin_en = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE); + fcw->hcout_en = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE); + fcw->crc_select = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK); + fcw->bypass_dec = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_DECODE_BYPASS); + fcw->bypass_intlv = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS); + if (op->ldpc_dec.q_m == 1) { + fcw->bypass_intlv = 1; + fcw->qm = 2; + } + fcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION); + fcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION); + fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_LLR_COMPRESSION); + harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset); + if (fcw->hcin_en > 0) { + harq_in_length = op->ldpc_dec.harq_combined_input.length; + if (fcw->hcin_decomp_mode > 0) + harq_in_length = harq_in_length * 8 / 6; + harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb + - op->ldpc_dec.n_filler); + /* Alignment on next 64B - Already enforced from HC output */ + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64); + fcw->hcin_size0 = harq_in_length; + fcw->hcin_offset = 0; + fcw->hcin_size1 = 0; + } else { + fcw->hcin_size0 = 0; + fcw->hcin_offset = 0; + fcw->hcin_size1 = 0; + } + + fcw->itmax = op->ldpc_dec.iter_max; + fcw->itstop = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE); + fcw->synd_precoder = fcw->itstop; + /* + * These are all implicitly set + * fcw->synd_post = 0; + * fcw->so_en = 0; + * fcw->so_bypass_rm = 0; + * fcw->so_bypass_intlv = 0; + * fcw->dec_convllr = 0; + * fcw->hcout_convllr = 0; + * fcw->hcout_size1 = 0; + * fcw->so_it = 0; + * fcw->hcout_offset = 0; + * fcw->negstop_th = 0; + * fcw->negstop_it = 0; + * fcw->negstop_en = 0; + * fcw->gain_i = 1; + * fcw->gain_h = 1; + */ + if (fcw->hcout_en > 0) { + parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8) + * op->ldpc_dec.z_c - op->ldpc_dec.n_filler; + k0_p = (fcw->k0 > parity_offset) ? + fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; + ncb_p = fcw->ncb - op->ldpc_dec.n_filler; + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX); + harq_out_length = (uint16_t) fcw->hcin_size0; + harq_out_length = RTE_MAX(harq_out_length, l); + /* Cannot exceed the pruned Ncb circular buffer */ + harq_out_length = RTE_MIN(harq_out_length, ncb_p); + /* Alignment on next 64B */ + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64); + fcw->hcout_size0 = harq_out_length; + fcw->hcout_size1 = 0; + fcw->hcout_offset = 0; + harq_layout[harq_index].offset = fcw->hcout_offset; + harq_layout[harq_index].size0 = fcw->hcout_size0; + } else { + fcw->hcout_size0 = 0; + fcw->hcout_size1 = 0; + fcw->hcout_offset = 0; + } +} + +static inline void +acc10x_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, + union acc100_harq_layout_data *harq_layout, struct acc100_queue *q) +{ + if (is_acc100(q)) + return acc100_fcw_ld_fill(op, fcw, harq_layout); + else + return acc101_fcw_ld_fill(op, fcw, harq_layout); +} + + /** * Fills descriptor with data pointers of one block type. * @@ -2960,7 +3100,7 @@ struct acc100_fcw_ld *fcw; uint32_t seg_total_left; fcw = &desc->req.fcw_ld; - acc100_fcw_ld_fill(op, fcw, harq_layout); + acc10x_fcw_ld_fill(op, fcw, harq_layout, q); /* Special handling when overusing mbuf */ if (fcw->rm_e < ACC100_MAX_E_MBUF) @@ -3027,7 +3167,7 @@ desc = q->ring_addr + desc_idx; uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET; union acc100_harq_layout_data *harq_layout = q->d->harq_layout; - acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout); + acc10x_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout, q); input = op->ldpc_dec.input.data; h_output_head = h_output = op->ldpc_dec.hard_output.data; @@ -4139,9 +4279,17 @@ dev->dequeue_ldpc_enc_ops = acc100_dequeue_ldpc_enc; dev->dequeue_ldpc_dec_ops = acc100_dequeue_ldpc_dec; - ((struct acc100_device *) dev->data->dev_private)->pf_device = - !strcmp(drv->driver.name, - RTE_STR(ACC100PF_DRIVER_NAME)); + if ((!strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME))) || + (!strcmp(drv->driver.name, RTE_STR(ACC100VF_DRIVER_NAME)))) { + ((struct acc100_device *) dev->data->dev_private)->pf_device = + !strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME)); + ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC100_VARIANT; + } else { + ((struct acc100_device *) dev->data->dev_private)->pf_device = + !strcmp(drv->driver.name, RTE_STR(ACC101PF_DRIVER_NAME)); + ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC101_VARIANT; + } + ((struct acc100_device *) dev->data->dev_private)->mmio_base = pci_dev->mem_resource[0].addr; @@ -4251,6 +4399,42 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) RTE_PMD_REGISTER_PCI(ACC100VF_DRIVER_NAME, acc100_pci_vf_driver); RTE_PMD_REGISTER_PCI_TABLE(ACC100VF_DRIVER_NAME, pci_id_acc100_vf_map); +/* ACC101 PCI PF address map */ +static struct rte_pci_id pci_id_acc101_pf_map[] = { + { + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_PF_DEVICE_ID) + }, + {.device_id = 0}, +}; + +/* ACC101 PCI VF address map */ +static struct rte_pci_id pci_id_acc101_vf_map[] = { + { + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_VF_DEVICE_ID) + }, + {.device_id = 0}, +}; + + +static struct rte_pci_driver acc101_pci_pf_driver = { + .probe = acc100_pci_probe, + .remove = acc100_pci_remove, + .id_table = pci_id_acc101_pf_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING +}; + +static struct rte_pci_driver acc101_pci_vf_driver = { + .probe = acc100_pci_probe, + .remove = acc100_pci_remove, + .id_table = pci_id_acc101_vf_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING +}; + +RTE_PMD_REGISTER_PCI(ACC101PF_DRIVER_NAME, acc101_pci_pf_driver); +RTE_PMD_REGISTER_PCI_TABLE(ACC101PF_DRIVER_NAME, pci_id_acc101_pf_map); +RTE_PMD_REGISTER_PCI(ACC101VF_DRIVER_NAME, acc101_pci_vf_driver); +RTE_PMD_REGISTER_PCI_TABLE(ACC101VF_DRIVER_NAME, pci_id_acc101_vf_map); + /* * Workaround implementation to fix the power on status of some 5GUL engines * This requires DMA permission if ported outside DPDK diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h index cbcece2..6438031 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.h +++ b/drivers/baseband/acc100/rte_acc100_pmd.h @@ -22,6 +22,9 @@ #define rte_bbdev_log_debug(fmt, ...) #endif +#define ACC100_VARIANT 0 +#define ACC101_VARIANT 1 + /* ACC100 PF and VF driver names */ #define ACC100PF_DRIVER_NAME intel_acc100_pf #define ACC100VF_DRIVER_NAME intel_acc100_vf @@ -67,6 +70,8 @@ #define ACC100_HARQ_LAYOUT (64*1024*1024) /* Assume offset for HARQ in memory */ #define ACC100_HARQ_OFFSET (32*1024) +#define ACC100_HARQ_OFFSET_SHIFT 15 +#define ACC100_HARQ_OFFSET_MASK 0x7ffffff /* Mask used to calculate an index in an Info Ring array (not a byte offset) */ #define ACC100_INFO_RING_MASK (ACC100_INFO_RING_NUM_ENTRIES-1) /* Number of Virtual Functions ACC100 supports */ @@ -590,6 +595,7 @@ struct acc100_device { uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS]; bool pf_device; /**< True if this is a PF ACC100 device */ bool configured; /**< True if this ACC100 device is configured */ + uint16_t device_variant; /**< Device variant */ }; /** diff --git a/drivers/baseband/acc100/rte_acc101_pmd.h b/drivers/baseband/acc100/rte_acc101_pmd.h new file mode 100644 index 0000000..1c57f63 --- /dev/null +++ b/drivers/baseband/acc100/rte_acc101_pmd.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Intel Corporation + */ + +/* ACC101 PF and VF driver names */ +#define ACC101PF_DRIVER_NAME intel_acc101_pf +#define ACC101VF_DRIVER_NAME intel_acc101_vf + +/* ACC101 PCI vendor & device IDs */ +#define RTE_ACC101_VENDOR_ID (0x8086) +#define RTE_ACC101_PF_DEVICE_ID (0x57c4) +#define RTE_ACC101_VF_DEVICE_ID (0x57c5) + +/* Define as 1 to use only a single FEC engine */ +#ifndef RTE_ACC101_SINGLE_FEC +#define RTE_ACC101_SINGLE_FEC 0 +#endif + +/* Values used in writing to the registers */ +#define ACC101_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */ + +/* Number of Virtual Functions ACC101 supports */ +#define ACC101_NUM_VFS 16 +#define ACC101_NUM_QGRPS 8 +#define ACC101_NUM_AQS 16 +/* All ACC101 Registers alignment are 32bits = 4B */ +#define ACC101_BYTES_IN_WORD 4 + +#define ACC101_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */ +#define ACC101_VF_ID_SHIFT 4 /* Queue Index Hierarchy */ +#define ACC101_VF_OFFSET_QOS 16 /* offset in Memory specific to QoS Mon */ +#define ACC101_TMPL_PRI_0 0x03020100 +#define ACC101_TMPL_PRI_1 0x07060504 +#define ACC101_TMPL_PRI_2 0x0b0a0908 +#define ACC101_TMPL_PRI_3 0x0f0e0d0c +#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4) + +#define ACC101_NUM_TMPL 32 +/* Mapping of signals for the available engines */ +#define ACC101_SIG_UL_5G 0 +#define ACC101_SIG_UL_5G_LAST 8 +#define ACC101_SIG_DL_5G 13 +#define ACC101_SIG_DL_5G_LAST 15 +#define ACC101_SIG_UL_4G 16 +#define ACC101_SIG_UL_4G_LAST 19 +#define ACC101_SIG_DL_4G 27 +#define ACC101_SIG_DL_4G_LAST 31 +#define ACC101_NUM_ACCS 5 +#define ACC101_PF_VAL 2 + +/* ACC101 Configuration */ +#define ACC101_CFG_DMA_ERROR 0x3D7 +#define ACC101_CFG_AXI_CACHE 0x11 +#define ACC101_CFG_QMGR_HI_P 0x0F0F +#define ACC101_CFG_PCI_AXI 0xC003 +#define ACC101_CFG_PCI_BRIDGE 0x40006033 +#define ACC101_ENGINE_OFFSET 0x1000 +#define ACC101_LONG_WAIT 1000 +#define ACC101_GPEX_AXIMAP_NUM 17 +#define ACC101_CLOCK_GATING_EN 0x30000 +#define ACC101_DMA_INBOUND 0x104 +/* DDR Size per VF - 512MB by default + * Can be increased up to 4 GB with single PF/VF + */ +#define ACC101_HARQ_DDR (512 * 1) From patchwork Mon May 16 20:48:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 111198 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 53DE9A00BE; Mon, 16 May 2022 22:56:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1D06C42B69; Mon, 16 May 2022 22:56:27 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 92EB840A7A for ; Mon, 16 May 2022 22:56:23 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652734583; x=1684270583; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=LiUUfjfBEjmiFNG7aHPYc8MZWfkGQqixkA+NjixpYEo=; b=anAWtvkOP+1bIObU3AU+2Fr++4vZR/6gIkdMfehqrSJQlL1gP0CPXO9B +bSxyuisTxVVjF5OzdLBGlKB4L0wKDlLEhTXjHOtPEwLkuIP2NGrFWu3J cee79Xl/3DaHK8SoU9hJvSJnNYevcgvqwzYXO6/YEJ37Ez9QBP2X6qphD bpU1vJwQF8btXGVZ2/I04qHu7mOk3bXtREpxiIfL7g5zc1HGriAhHkHpi 9ZR7kZELrSyx5Xln4/w0d2sHymWl81JhJnNL53OMqrKMtalEgb4O6R5lM gwEcRFzuinpn9UB7t/G8HjeOkRfz/TwlvDwmZIj0OUSF+7xBId0oTIsr6 Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10349"; a="251476094" X-IronPort-AV: E=Sophos;i="5.91,230,1647327600"; d="scan'208";a="251476094" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2022 13:56:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,230,1647327600"; d="scan'208";a="574199169" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by fmsmga007.fm.intel.com with ESMTP; 16 May 2022 13:56:21 -0700 From: Nicolas Chautru To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: thomas@monjalon.net, ray.kinsella@intel.com, bruce.richardson@intel.com, hemant.agrawal@nxp.com, hernan.vargas@intel.com, david.marchand@redhat.com, Nicolas Chautru Subject: [PATCH v3 2/4] baseband/acc100: modify validation code for ACC101 Date: Mon, 16 May 2022 13:48:31 -0700 Message-Id: <1652734113-124047-3-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1652734113-124047-1-git-send-email-nicolas.chautru@intel.com> References: <1651083423-33202-1-git-send-email-nicolas.chautru@intel.com> <1652734113-124047-1-git-send-email-nicolas.chautru@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The validation requirement is different for the two devices. Signed-off-by: Nicolas Chautru --- drivers/baseband/acc100/rte_acc100_pmd.c | 40 ++++++++++++++++++++++---------- 1 file changed, 28 insertions(+), 12 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index fca27ef..daf2ce0 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1293,6 +1293,14 @@ return (q->d->device_variant == ACC100_VARIANT); } +#ifdef RTE_LIBRTE_BBDEV_DEBUG +static inline bool +validate_op_required(struct acc100_queue *q) +{ + return is_acc100(q); +} +#endif + /* Fill in a frame control word for LDPC decoding. */ static inline void acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, @@ -2187,8 +2195,10 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validates turbo encoder parameters */ static inline int -validate_enc_op(struct rte_bbdev_enc_op *op) +validate_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q) { + if (!validate_op_required(q)) + return 0; struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc; struct rte_bbdev_op_enc_turbo_cb_params *cb = NULL; struct rte_bbdev_op_enc_turbo_tb_params *tb = NULL; @@ -2325,8 +2335,10 @@ static inline uint32_t hq_index(uint32_t offset) } /* Validates LDPC encoder parameters */ static inline int -validate_ldpc_enc_op(struct rte_bbdev_enc_op *op) +validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q) { + if (!validate_op_required(q)) + return 0; struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc; if (op->mempool == NULL) { @@ -2378,8 +2390,10 @@ static inline uint32_t hq_index(uint32_t offset) /* Validates LDPC decoder parameters */ static inline int -validate_ldpc_dec_op(struct rte_bbdev_dec_op *op) +validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q) { + if (!validate_op_required(q)) + return 0; struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec; if (op->mempool == NULL) { @@ -2434,7 +2448,7 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ - if (validate_enc_op(op) == -1) { + if (validate_enc_op(op, q) == -1) { rte_bbdev_log(ERR, "Turbo encoder validation failed"); return -EINVAL; } @@ -2488,7 +2502,7 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ - if (validate_ldpc_enc_op(ops[0]) == -1) { + if (validate_ldpc_enc_op(ops[0], q) == -1) { rte_bbdev_log(ERR, "LDPC encoder validation failed"); return -EINVAL; } @@ -2550,7 +2564,7 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ - if (validate_ldpc_enc_op(op) == -1) { + if (validate_ldpc_enc_op(op, q) == -1) { rte_bbdev_log(ERR, "LDPC encoder validation failed"); return -EINVAL; } @@ -2607,7 +2621,7 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ - if (validate_enc_op(op) == -1) { + if (validate_enc_op(op, q) == -1) { rte_bbdev_log(ERR, "Turbo encoder validation failed"); return -EINVAL; } @@ -2680,8 +2694,10 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validates turbo decoder parameters */ static inline int -validate_dec_op(struct rte_bbdev_dec_op *op) +validate_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q) { + if (!validate_op_required(q)) + return 0; struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec; struct rte_bbdev_op_dec_turbo_cb_params *cb = NULL; struct rte_bbdev_op_dec_turbo_tb_params *tb = NULL; @@ -2827,7 +2843,7 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ - if (validate_dec_op(op) == -1) { + if (validate_dec_op(op, q) == -1) { rte_bbdev_log(ERR, "Turbo decoder validation failed"); return -EINVAL; } @@ -3052,7 +3068,7 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ - if (validate_ldpc_dec_op(op) == -1) { + if (validate_ldpc_dec_op(op, q) == -1) { rte_bbdev_log(ERR, "LDPC decoder validation failed"); return -EINVAL; } @@ -3156,7 +3172,7 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ - if (validate_ldpc_dec_op(op) == -1) { + if (validate_ldpc_dec_op(op, q) == -1) { rte_bbdev_log(ERR, "LDPC decoder validation failed"); return -EINVAL; } @@ -3246,7 +3262,7 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ - if (validate_dec_op(op) == -1) { + if (validate_dec_op(op, q) == -1) { rte_bbdev_log(ERR, "Turbo decoder validation failed"); return -EINVAL; } From patchwork Mon May 16 20:48:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 111199 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 14C83A00BE; Mon, 16 May 2022 22:56:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EE42142B6E; Mon, 16 May 2022 22:56:27 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 0448E4068B for ; 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16 May 2022 13:56:21 -0700 From: Nicolas Chautru To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: thomas@monjalon.net, ray.kinsella@intel.com, bruce.richardson@intel.com, hemant.agrawal@nxp.com, hernan.vargas@intel.com, david.marchand@redhat.com, Nicolas Chautru Subject: [PATCH v3 3/4] baseband/acc100: configuration of ACC101 from PF Date: Mon, 16 May 2022 13:48:32 -0700 Message-Id: <1652734113-124047-4-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1652734113-124047-1-git-send-email-nicolas.chautru@intel.com> References: <1651083423-33202-1-git-send-email-nicolas.chautru@intel.com> <1652734113-124047-1-git-send-email-nicolas.chautru@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding companion function specific to ACC100 and it can be called from bbdev-test when running from PF. Signed-off-by: Nicolas Chautru --- app/test-bbdev/test_bbdev_perf.c | 22 ++- drivers/baseband/acc100/rte_acc100_cfg.h | 17 ++ drivers/baseband/acc100/rte_acc100_pmd.c | 302 +++++++++++++++++++++++++++++++ drivers/baseband/acc100/version.map | 2 +- 4 files changed, 336 insertions(+), 7 deletions(-) diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c index 0fa119a..b10b93d 100644 --- a/app/test-bbdev/test_bbdev_perf.c +++ b/app/test-bbdev/test_bbdev_perf.c @@ -63,6 +63,8 @@ #define ACC100_QMGR_INVALID_IDX -1 #define ACC100_QMGR_RR 1 #define ACC100_QOS_GBR 0 +#define ACC101PF_DRIVER_NAME ("intel_acc101_pf") +#define ACC101VF_DRIVER_NAME ("intel_acc101_vf") #endif #define OPS_CACHE_SIZE 256U @@ -711,11 +713,12 @@ typedef int (test_case_function)(struct active_device *ad, #endif #ifdef RTE_BASEBAND_ACC100 if ((get_init_device() == true) && - (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) { + ((!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME)) || + (!strcmp(info->drv.driver_name, ACC101PF_DRIVER_NAME)))) { struct rte_acc100_conf conf; unsigned int i; - printf("Configure ACC100 FEC Driver %s with default values\n", + printf("Configure ACC10X FEC Driver %s with default values\n", info->drv.driver_name); /* clear default configuration before initialization */ @@ -760,10 +763,17 @@ typedef int (test_case_function)(struct active_device *ad, conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH; /* setup PF with configuration information */ - ret = rte_acc100_configure(info->dev_name, &conf); - TEST_ASSERT_SUCCESS(ret, - "Failed to configure ACC100 PF for bbdev %s", - info->dev_name); + if (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME)) { + ret = rte_acc100_configure(info->dev_name, &conf); + TEST_ASSERT_SUCCESS(ret, + "Failed to configure ACC100 PF for bbdev %s", + info->dev_name); + } else { + ret = rte_acc101_configure(info->dev_name, &conf); + TEST_ASSERT_SUCCESS(ret, + "Failed to configure ACC101 PF for bbdev %s", + info->dev_name); + } } #endif /* Let's refresh this now this is configured */ diff --git a/drivers/baseband/acc100/rte_acc100_cfg.h b/drivers/baseband/acc100/rte_acc100_cfg.h index d233e42..2e3c43f 100644 --- a/drivers/baseband/acc100/rte_acc100_cfg.h +++ b/drivers/baseband/acc100/rte_acc100_cfg.h @@ -106,6 +106,23 @@ struct rte_acc100_conf { int rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf); +/** + * Configure a ACC101 device + * + * @param dev_name + * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0. + * It can also be retrieved for a bbdev device from the dev_name field in the + * rte_bbdev_info structure returned by rte_bbdev_info_get(). + * @param conf + * Configuration to apply to ACC101 HW. + * + * @return + * Zero on success, negative value on failure. + */ +__rte_experimental +int +rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf); + #ifdef __cplusplus } #endif diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index daf2ce0..b03cedc 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -4921,3 +4921,305 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name); return 0; } + + +/* Initial configuration of a ACC101 device prior to running configure() */ +int +rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf) +{ + rte_bbdev_log(INFO, "rte_acc101_configure"); + uint32_t value, address, status; + int qg_idx, template_idx, vf_idx, acc, i; + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name); + + /* Compile time checks */ + RTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256); + RTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256); + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24); + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32); + + if (bbdev == NULL) { + rte_bbdev_log(ERR, + "Invalid dev_name (%s), or device is not yet initialised", + dev_name); + return -ENODEV; + } + struct acc100_device *d = bbdev->data->dev_private; + + /* Store configuration */ + rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf)); + + /* PCIe Bridge configuration */ + acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC101_CFG_PCI_BRIDGE); + for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++) + acc100_reg_write(d, HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh + i * 16, 0); + + /* Prevent blocking AXI read on BRESP for AXI Write */ + address = HwPfPcieGpexAxiPioControl; + value = ACC101_CFG_PCI_AXI; + acc100_reg_write(d, address, value); + + /* Explicitly releasing AXI as this may be stopped after PF FLR/BME */ + usleep(2000); + acc100_reg_write(d, HWPfDmaAxiControl, 1); + + /* Set the default 5GDL DMA configuration */ + acc100_reg_write(d, HWPfDmaInboundDrainDataSize, ACC101_DMA_INBOUND); + + /* Enable granular dynamic clock gating */ + address = HWPfHiClkGateHystReg; + value = ACC101_CLOCK_GATING_EN; + acc100_reg_write(d, address, value); + + /* Set default descriptor signature */ + address = HWPfDmaDescriptorSignatuture; + value = 0; + acc100_reg_write(d, address, value); + + /* Enable the Error Detection in DMA */ + value = ACC101_CFG_DMA_ERROR; + address = HWPfDmaErrorDetectionEn; + acc100_reg_write(d, address, value); + + /* AXI Cache configuration */ + value = ACC101_CFG_AXI_CACHE; + address = HWPfDmaAxcacheReg; + acc100_reg_write(d, address, value); + + /* Default DMA Configuration (Qmgr Enabled) */ + address = HWPfDmaConfig0Reg; + value = 0; + acc100_reg_write(d, address, value); + address = HWPfDmaQmanen; + value = 0; + acc100_reg_write(d, address, value); + + /* Default RLIM/ALEN configuration */ + address = HWPfDmaConfig1Reg; + int alen_r = 0xF; + int alen_w = 0x7; + value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r; + acc100_reg_write(d, address, value); + + /* Configure DMA Qmanager addresses */ + address = HWPfDmaQmgrAddrReg; + value = HWPfQmgrEgressQueuesTemplate; + acc100_reg_write(d, address, value); + + /* ===== Qmgr Configuration ===== */ + /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */ + int totalQgs = conf->q_ul_4g.num_qgroups + + conf->q_ul_5g.num_qgroups + + conf->q_dl_4g.num_qgroups + + conf->q_dl_5g.num_qgroups; + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) { + address = HWPfQmgrDepthLog2Grp + + ACC101_BYTES_IN_WORD * qg_idx; + value = aqDepth(qg_idx, conf); + acc100_reg_write(d, address, value); + address = HWPfQmgrTholdGrp + + ACC101_BYTES_IN_WORD * qg_idx; + value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1)); + acc100_reg_write(d, address, value); + } + + /* Template Priority in incremental order */ + for (template_idx = 0; template_idx < ACC101_NUM_TMPL; + template_idx++) { + address = HWPfQmgrGrpTmplateReg0Indx + ACC101_BYTES_IN_WORD * template_idx; + value = ACC101_TMPL_PRI_0; + acc100_reg_write(d, address, value); + address = HWPfQmgrGrpTmplateReg1Indx + ACC101_BYTES_IN_WORD * template_idx; + value = ACC101_TMPL_PRI_1; + acc100_reg_write(d, address, value); + address = HWPfQmgrGrpTmplateReg2indx + ACC101_BYTES_IN_WORD * template_idx; + value = ACC101_TMPL_PRI_2; + acc100_reg_write(d, address, value); + address = HWPfQmgrGrpTmplateReg3Indx + ACC101_BYTES_IN_WORD * template_idx; + value = ACC101_TMPL_PRI_3; + acc100_reg_write(d, address, value); + } + + address = HWPfQmgrGrpPriority; + value = ACC101_CFG_QMGR_HI_P; + acc100_reg_write(d, address, value); + + /* Template Configuration */ + for (template_idx = 0; template_idx < ACC101_NUM_TMPL; + template_idx++) { + value = 0; + address = HWPfQmgrGrpTmplateReg4Indx + + ACC101_BYTES_IN_WORD * template_idx; + acc100_reg_write(d, address, value); + } + /* 4GUL */ + int numQgs = conf->q_ul_4g.num_qgroups; + int numQqsAcc = 0; + value = 0; + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++) + value |= (1 << qg_idx); + for (template_idx = ACC101_SIG_UL_4G; + template_idx <= ACC101_SIG_UL_4G_LAST; + template_idx++) { + address = HWPfQmgrGrpTmplateReg4Indx + + ACC101_BYTES_IN_WORD * template_idx; + acc100_reg_write(d, address, value); + } + /* 5GUL */ + numQqsAcc += numQgs; + numQgs = conf->q_ul_5g.num_qgroups; + value = 0; + int numEngines = 0; + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++) + value |= (1 << qg_idx); + for (template_idx = ACC101_SIG_UL_5G; + template_idx <= ACC101_SIG_UL_5G_LAST; + template_idx++) { + /* Check engine power-on status */ + address = HwPfFecUl5gIbDebugReg + + ACC101_ENGINE_OFFSET * template_idx; + status = (acc100_reg_read(d, address) >> 4) & 0xF; + address = HWPfQmgrGrpTmplateReg4Indx + + ACC101_BYTES_IN_WORD * template_idx; + if (status == 1) { + acc100_reg_write(d, address, value); + numEngines++; + } else + acc100_reg_write(d, address, 0); +#if RTE_ACC101_SINGLE_FEC == 1 + value = 0; +#endif + } + printf("Number of 5GUL engines %d\n", numEngines); + /* 4GDL */ + numQqsAcc += numQgs; + numQgs = conf->q_dl_4g.num_qgroups; + value = 0; + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++) + value |= (1 << qg_idx); + for (template_idx = ACC101_SIG_DL_4G; + template_idx <= ACC101_SIG_DL_4G_LAST; + template_idx++) { + address = HWPfQmgrGrpTmplateReg4Indx + + ACC101_BYTES_IN_WORD * template_idx; + acc100_reg_write(d, address, value); +#if RTE_ACC101_SINGLE_FEC == 1 + value = 0; +#endif + } + /* 5GDL */ + numQqsAcc += numQgs; + numQgs = conf->q_dl_5g.num_qgroups; + value = 0; + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++) + value |= (1 << qg_idx); + for (template_idx = ACC101_SIG_DL_5G; + template_idx <= ACC101_SIG_DL_5G_LAST; + template_idx++) { + address = HWPfQmgrGrpTmplateReg4Indx + + ACC101_BYTES_IN_WORD * template_idx; + acc100_reg_write(d, address, value); +#if RTE_ACC101_SINGLE_FEC == 1 + value = 0; +#endif + } + + /* Queue Group Function mapping */ + int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0}; + address = HWPfQmgrGrpFunction0; + value = 0; + for (qg_idx = 0; qg_idx < 8; qg_idx++) { + acc = accFromQgid(qg_idx, conf); + value |= qman_func_id[acc]<<(qg_idx * 4); + } + acc100_reg_write(d, address, value); + + /* Configuration of the Arbitration QGroup depth to 1 */ + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) { + address = HWPfQmgrArbQDepthGrp + + ACC101_BYTES_IN_WORD * qg_idx; + value = 0; + acc100_reg_write(d, address, value); + } + + /* Enabling AQueues through the Queue hierarchy*/ + for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) { + for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) { + value = 0; + if (vf_idx < conf->num_vf_bundles && + qg_idx < totalQgs) + value = (1 << aqNum(qg_idx, conf)) - 1; + address = HWPfQmgrAqEnableVf + + vf_idx * ACC101_BYTES_IN_WORD; + value += (qg_idx << 16); + acc100_reg_write(d, address, value); + } + } + + /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */ + uint32_t aram_address = 0; + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) { + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) { + address = HWPfQmgrVfBaseAddr + vf_idx + * ACC101_BYTES_IN_WORD + qg_idx + * ACC101_BYTES_IN_WORD * 64; + value = aram_address; + acc100_reg_write(d, address, value); + /* Offset ARAM Address for next memory bank + * - increment of 4B + */ + aram_address += aqNum(qg_idx, conf) * + (1 << aqDepth(qg_idx, conf)); + } + } + + if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) { + rte_bbdev_log(ERR, "ARAM Configuration not fitting %d %d\n", + aram_address, ACC101_WORDS_IN_ARAM_SIZE); + return -EINVAL; + } + + /* ==== HI Configuration ==== */ + + /* No Info Ring/MSI by default */ + acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0); + acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0); + acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF); + acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF); + /* Prevent Block on Transmit Error */ + address = HWPfHiBlockTransmitOnErrorEn; + value = 0; + acc100_reg_write(d, address, value); + /* Prevents to drop MSI */ + address = HWPfHiMsiDropEnableReg; + value = 0; + acc100_reg_write(d, address, value); + /* Set the PF Mode register */ + address = HWPfHiPfMode; + value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0; + acc100_reg_write(d, address, value); + /* Explicitly releasing AXI after PF Mode and 2 ms */ + usleep(2000); + acc100_reg_write(d, HWPfDmaAxiControl, 1); + + /* QoS overflow init */ + value = 1; + address = HWPfQosmonAEvalOverflow0; + acc100_reg_write(d, address, value); + address = HWPfQosmonBEvalOverflow0; + acc100_reg_write(d, address, value); + + /* HARQ DDR Configuration */ + unsigned int ddrSizeInMb = ACC101_HARQ_DDR; + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) { + address = HWPfDmaVfDdrBaseRw + vf_idx + * 0x10; + value = ((vf_idx * (ddrSizeInMb / 64)) << 16) + + (ddrSizeInMb - 1); + acc100_reg_write(d, address, value); + } + usleep(ACC101_LONG_WAIT); + + rte_bbdev_log_debug("PF TIP configuration complete for %s", dev_name); + return 0; +} diff --git a/drivers/baseband/acc100/version.map b/drivers/baseband/acc100/version.map index 40604c7..37b850f 100644 --- a/drivers/baseband/acc100/version.map +++ b/drivers/baseband/acc100/version.map @@ -6,5 +6,5 @@ EXPERIMENTAL { global: rte_acc100_configure; - + rte_acc101_configure; }; From patchwork Mon May 16 20:48:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 111200 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7952EA00BE; Mon, 16 May 2022 22:56:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DEF8E42B74; Mon, 16 May 2022 22:56:28 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 5C3D440E03 for ; Mon, 16 May 2022 22:56:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652734584; x=1684270584; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=9ocSml247WhQo0uFH9foT4ozYs8yTN6kx18Ws2L8Rh4=; b=IrY1hi1beQdUpSLuNWjUSTTmum83Tfsj8IWpaI7kSAnSwesXELcP1EtT +WWXemhd2IBvLrh6AxL7qnSYkkAykDkQvczw4N3Da809CXvU4m/mdvjoX LfS2/fqjuS0raK9nf1DTHuID38qIOrN5ty8MNI1Ba93izyM5W+2Somz5V 6ki1DMkwynVp8QqtLa9nyzoVrpWCN9h5ouE/F5T59I7xQZBvx+dZtUwx2 lAEzpci1QcBx77ECTb1vwnrbOOmuILBgWMYh5tduVzTbd+dI4scs8SO3I p7j+zpomOtWoA0nhkZEOXyz4ospplgfkSNVmtY2diMU0/hXSj7OWoj9aI w==; X-IronPort-AV: E=McAfee;i="6400,9594,10349"; a="251476096" X-IronPort-AV: E=Sophos;i="5.91,230,1647327600"; d="scan'208";a="251476096" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2022 13:56:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,230,1647327600"; d="scan'208";a="574199177" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by fmsmga007.fm.intel.com with ESMTP; 16 May 2022 13:56:21 -0700 From: Nicolas Chautru To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: thomas@monjalon.net, ray.kinsella@intel.com, bruce.richardson@intel.com, hemant.agrawal@nxp.com, hernan.vargas@intel.com, david.marchand@redhat.com, Nicolas Chautru Subject: [PATCH v3 4/4] baseband/acc100: add protection for some negative scenario Date: Mon, 16 May 2022 13:48:33 -0700 Message-Id: <1652734113-124047-5-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1652734113-124047-1-git-send-email-nicolas.chautru@intel.com> References: <1651083423-33202-1-git-send-email-nicolas.chautru@intel.com> <1652734113-124047-1-git-send-email-nicolas.chautru@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Catch exception in PMD in case of invalid input parameter. Signed-off-by: Nicolas Chautru --- drivers/baseband/acc100/rte_acc100_pmd.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index b03cedc..b59c9d7 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1237,6 +1237,8 @@ return (bg == 1 ? ACC100_K0_3_1 : ACC100_K0_3_2) * z_c; } /* LBRM case - includes a division by N */ + if (unlikely(z_c == 0)) + return 0; if (rv_index == 1) return (((bg == 1 ? ACC100_K0_1_1 : ACC100_K0_1_2) * n_cb) / n) * z_c; @@ -1912,6 +1914,10 @@ static inline uint32_t hq_index(uint32_t offset) /* Soft output */ if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_SOFT_OUTPUT)) { + if (op->turbo_dec.soft_output.data == 0) { + rte_bbdev_log(ERR, "Soft output is not defined"); + return -1; + } if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_EQUALIZER)) *s_out_length = e;