From patchwork Tue May 24 08:42:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harman Kalra X-Patchwork-Id: 111709 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 81901A04FF; Tue, 24 May 2022 10:42:55 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 724314067C; Tue, 24 May 2022 10:42:55 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 74FB040A84 for ; Tue, 24 May 2022 10:42:53 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24O7iwf3017461 for ; Tue, 24 May 2022 01:42:52 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=x4LDKxWBGQN0zKv3ZNDTZHoxk36vSoLkpSPUNc6PZ0U=; b=X+IbmG+5FrSl3Tmq86oih36RKQQL5g960qFwb95UuDe7wNNz60n7njgARumxkSvWx2um ROyJUZPxskbnO98n6mF34TcDFBQOBg6LTr2VG8XeDWChdfRisPxQ8mvoS/5dMePWlb/c BzDPsEYacy80jo+9AKUDFcF+3qA5upWVOVv6HJAuOM4Lo8cqgjaqLJMpyfsiDxrc+UxM /9JiRoA07/mvwCENnZOl9q936qzrLklhe2adzokopJaP8x7OZAQsuxdw3O+NZ3LtOb+A 5uSYIAznRW5DfsCAIMHgwnQhAYK1S9GQ33hy3rZs6q2TjREcOLti8OjPAJXuz2xrXPzF qQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3g6ykm1r4q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 24 May 2022 01:42:52 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 24 May 2022 01:42:50 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 24 May 2022 01:42:50 -0700 Received: from localhost.localdomain (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id CDB4C3F709B; Tue, 24 May 2022 01:42:48 -0700 (PDT) From: Harman Kalra To: , Jerin Jacob CC: Harman Kalra , Pavan Nikhilesh Subject: [PATCH v3 01/11] event/octeontx: fix SSO fastpath Date: Tue, 24 May 2022 14:12:25 +0530 Message-ID: <20220524084235.17796-1-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220517173941.189330-2-hkalra@marvell.com> References: <20220517173941.189330-2-hkalra@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: dI_e2adyHnAXE9ydSJB1QqR1C3FXi6xT X-Proofpoint-ORIG-GUID: dI_e2adyHnAXE9ydSJB1QqR1C3FXi6xT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-24_05,2022-05-23_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Segmentation fault is observed as soon as any dpdk application with ethdev event is launched. Handling the event types appropriately. Also fixing sub event type violation as in OCTEONTX event device we use sub_event_type to store the ethernet port identifier when we receive work from OCTEONTX ethernet device. This violates the event device spec as sub_event_type should be 0 in the initial receive stage. Set sub_event_type to 0 after copying the port id in single workslot mode. Fixes: 8dc6c2f12ecf ("crypto/octeontx: add crypto adapter data path") Signed-off-by: Harman Kalra Signed-off-by: Pavan Nikhilesh --- V3: * fixing sub event type violation V2: * Seperated out a generic patch from the series drivers/event/octeontx/ssovf_worker.h | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/event/octeontx/ssovf_worker.h b/drivers/event/octeontx/ssovf_worker.h index e6ee292688..57be476394 100644 --- a/drivers/event/octeontx/ssovf_worker.h +++ b/drivers/event/octeontx/ssovf_worker.h @@ -179,16 +179,22 @@ ssows_get_work(struct ssows *ws, struct rte_event *ev, const uint16_t flag) ev->event = sched_type_queue | (get_work0 & 0xffffffff); if (get_work1) { - if (ev->event_type == RTE_EVENT_TYPE_ETHDEV) - get_work1 = (uintptr_t)ssovf_octeontx_wqe_to_pkt( - get_work1, (ev->event >> 20) & 0x7F, flag, - ws->lookup_mem); - else if (ev->event_type == RTE_EVENT_TYPE_CRYPTODEV) + if (ev->event_type == RTE_EVENT_TYPE_ETHDEV) { + uint16_t port = (ev->event >> 20) & 0x7F; + + ev->sub_event_type = 0; + ev->mbuf = ssovf_octeontx_wqe_to_pkt( + get_work1, port, flag, ws->lookup_mem); + } else if (ev->event_type == RTE_EVENT_TYPE_CRYPTODEV) { get_work1 = otx_crypto_adapter_dequeue(get_work1); - ev->u64 = get_work1; - } else if (unlikely((get_work0 & 0xFFFFFFFF) == 0xFFFFFFFF)) { - ssovf_octeontx_wqe_free(get_work1); - return 0; + ev->u64 = get_work1; + } else { + if (unlikely((get_work0 & 0xFFFFFFFF) == 0xFFFFFFFF)) { + ssovf_octeontx_wqe_free(get_work1); + return 0; + } + ev->u64 = get_work1; + } } return !!get_work1; From patchwork Tue May 24 08:42:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harman Kalra X-Patchwork-Id: 111710 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E6E1DA04FF; Tue, 24 May 2022 10:43:02 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9148942670; Tue, 24 May 2022 10:42:57 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 475AE42670 for ; Tue, 24 May 2022 10:42:56 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24NNBLeo022514 for ; Tue, 24 May 2022 01:42:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=ElwPjVtyFcwVCbU/ZRUmtthq2glHiwt7Vpfrsusm+bo=; b=YZJELzqHfIyzrA7UgHrzunW3/LkLpvbNDLBQCZDgApdFcwZDPEl7cvb+9fi8XVceLD7n QHGm7VSblT37UbVbe6jWtqzYDeOrrgSPNXEQmomwrYI3n6kQjBIyo/fT2Mf8uAnLaSsT +rdKtYwRfpdGdKX3+Vo7LJrSIZ2c92Xh+bSq6LW9O8/w9gseaNEFjCWUuUp8x67LSuzN jBmAVorRGCUBW7aipu4DcdNlPfGr2pH7ctubf0YwLRb7+4sM4uqlhbti0VMPuD3fYIWI olkZCSKq6E+PvdbUwJbkKn8n+8EuK0def0YmG6rMYAWBPz9eMKsYtc5QZDjloAVOu7aZ AA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3g8kqjhrta-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 24 May 2022 01:42:55 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 24 May 2022 01:42:53 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 24 May 2022 01:42:53 -0700 Received: from localhost.localdomain (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id 9DCC63F7043; Tue, 24 May 2022 01:42:52 -0700 (PDT) From: Harman Kalra To: , Harman Kalra Subject: [PATCH v3 02/11] net/octeontx: fix port close Date: Tue, 24 May 2022 14:12:26 +0530 Message-ID: <20220524084235.17796-2-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220524084235.17796-1-hkalra@marvell.com> References: <20220517173941.189330-2-hkalra@marvell.com> <20220524084235.17796-1-hkalra@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: NUOB3zuEEiQ0pLPaR6T8FCk1747r8bfr X-Proofpoint-GUID: NUOB3zuEEiQ0pLPaR6T8FCk1747r8bfr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-24_06,2022-05-23_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Segmentation fault has been observed while closing the ethernet port. Reason for the segfault is, eth port close also shuts down event device while other ethernet port is still using the event device. Fixes: da6c687471a3 ("net/octeontx: add start and stop support") Signed-off-by: Harman Kalra --- drivers/net/octeontx/octeontx_ethdev.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/net/octeontx/octeontx_ethdev.c b/drivers/net/octeontx/octeontx_ethdev.c index f5ea9de8ef..6469fd0a96 100644 --- a/drivers/net/octeontx/octeontx_ethdev.c +++ b/drivers/net/octeontx/octeontx_ethdev.c @@ -26,6 +26,11 @@ #include "octeontx_rxtx.h" #include "octeontx_logs.h" +/* Useful in stopping/closing event device if no of + * eth ports are using it. + */ +uint16_t evdev_refcnt; + struct evdev_priv_data { OFFLOAD_FLAGS; /*Sequence should not be changed */ } __rte_cache_aligned; @@ -491,7 +496,11 @@ octeontx_dev_close(struct rte_eth_dev *dev) if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; - rte_event_dev_close(nic->evdev); + /* Stopping/closing event device once all eth ports are closed. */ + if (__atomic_sub_fetch(&evdev_refcnt, 1, __ATOMIC_ACQUIRE) == 0) { + rte_event_dev_stop(nic->evdev); + rte_event_dev_close(nic->evdev); + } octeontx_dev_flow_ctrl_fini(dev); @@ -671,8 +680,6 @@ octeontx_dev_stop(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); - rte_event_dev_stop(nic->evdev); - ret = octeontx_port_stop(nic); if (ret < 0) { octeontx_log_err("failed to req stop port %d res=%d", @@ -1333,6 +1340,7 @@ octeontx_create(struct rte_vdev_device *dev, int port, uint8_t evdev, nic->pko_vfid = pko_vfid; nic->port_id = port; nic->evdev = evdev; + __atomic_add_fetch(&evdev_refcnt, 1, __ATOMIC_ACQUIRE); res = octeontx_port_open(nic); if (res < 0) @@ -1582,6 +1590,7 @@ octeontx_probe(struct rte_vdev_device *dev) } } + __atomic_store_n(&evdev_refcnt, 0, __ATOMIC_RELEASE); /* * Do 1:1 links for ports & queues. All queues would be mapped to * one port. If there are more ports than queues, then some ports From patchwork Tue May 24 08:42:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harman Kalra X-Patchwork-Id: 111711 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B1DF8A04FF; Tue, 24 May 2022 10:43:08 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 81CAD41104; Tue, 24 May 2022 10:43:00 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 0DA4D400D6 for ; Tue, 24 May 2022 10:42:58 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24NNBSVk022568 for ; Tue, 24 May 2022 01:42:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=r49QqWDG9tuMlxHgGDujMnx2/mZ90RYBguqJDtbvli4=; b=Bgfm091baEJCbEeCHfs9gno9kG9hwpocQoQrbESroLJfktbeC+JMN2/ExPyDV5yxkaHj wIVE504j0Kj6jariuemQT9vl8VTZ6C64roL8Bi5oVOsWJYmRW3PHp/DLg1x4SJu8zjaq DAfivXLsnxffnP/JGXnuKdmRKYBDtuU/3uKE+6aOoCqj+QeKp+Uo94nBOqE50s1dJf2d G0+FFw8k50BoFeGuzxp7kMi6zcAKT9C1Ijklwg+4o73skkc99k/Nlb14QURvDzAyuPuy S1U1lG2PsjXs81Vd/+PAZ4uEEugOg+Jz4vpSak24i7abwI9AfQT3iBTr02HRPXslj2Dp fw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3g8kqjhrtk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 24 May 2022 01:42:58 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 24 May 2022 01:42:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 24 May 2022 01:42:56 -0700 Received: from localhost.localdomain (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id 496E83F709F; Tue, 24 May 2022 01:42:55 -0700 (PDT) From: Harman Kalra To: , Harman Kalra Subject: [PATCH v3 03/11] net/octeontx: setting link attributes Date: Tue, 24 May 2022 14:12:27 +0530 Message-ID: <20220524084235.17796-3-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220524084235.17796-1-hkalra@marvell.com> References: <20220517173941.189330-2-hkalra@marvell.com> <20220524084235.17796-1-hkalra@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: xXIC8BQgPxnuCT7OEJlrlXyO34ZRCBKV X-Proofpoint-GUID: xXIC8BQgPxnuCT7OEJlrlXyO34ZRCBKV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-24_06,2022-05-23_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding support to configure link attributes like speed, duplex, negotiation. Signed-off-by: Harman Kalra --- drivers/net/octeontx/base/octeontx_bgx.c | 19 ++++++ drivers/net/octeontx/base/octeontx_bgx.h | 12 ++++ drivers/net/octeontx/octeontx_ethdev.c | 80 ++++++++++++++++++++++-- 3 files changed, 105 insertions(+), 6 deletions(-) diff --git a/drivers/net/octeontx/base/octeontx_bgx.c b/drivers/net/octeontx/base/octeontx_bgx.c index ac856ff86d..1c6fa05ebc 100644 --- a/drivers/net/octeontx/base/octeontx_bgx.c +++ b/drivers/net/octeontx/base/octeontx_bgx.c @@ -376,3 +376,22 @@ int octeontx_bgx_port_flow_ctrl_cfg(int port, done: return 0; } + +int octeontx_bgx_port_change_mode(int port, + octeontx_mbox_bgx_port_change_mode_t *cfg) +{ + int len = sizeof(octeontx_mbox_bgx_port_change_mode_t), res; + octeontx_mbox_bgx_port_change_mode_t conf; + struct octeontx_mbox_hdr hdr; + + hdr.coproc = OCTEONTX_BGX_COPROC; + hdr.msg = MBOX_BGX_PORT_CHANGE_MODE; + hdr.vfid = port; + + memcpy(&conf, cfg, len); + res = octeontx_mbox_send(&hdr, &conf, len, NULL, 0); + if (res < 0) + return -EACCES; + + return res; +} diff --git a/drivers/net/octeontx/base/octeontx_bgx.h b/drivers/net/octeontx/base/octeontx_bgx.h index d126a0b7fc..e4cfa3e73a 100644 --- a/drivers/net/octeontx/base/octeontx_bgx.h +++ b/drivers/net/octeontx/base/octeontx_bgx.h @@ -37,6 +37,7 @@ #define MBOX_BGX_PORT_GET_FIFO_CFG 18 #define MBOX_BGX_PORT_FLOW_CTRL_CFG 19 #define MBOX_BGX_PORT_SET_LINK_STATE 20 +#define MBOX_BGX_PORT_CHANGE_MODE 21 /* BGX port configuration parameters: */ typedef struct octeontx_mbox_bgx_port_conf { @@ -143,6 +144,15 @@ typedef struct octeontx_mbox_bgx_port_fc_cfg { bgx_port_fc_t fc_cfg; } octeontx_mbox_bgx_port_fc_cfg_t; +/* BGX change mode */ +typedef struct octeontx_mbox_bgx_port_change_mode { + uint16_t padding; + uint8_t qlm_mode; + bool autoneg; + uint8_t duplex; + uint32_t speed; +} octeontx_mbox_bgx_port_change_mode_t; + int octeontx_bgx_port_open(int port, octeontx_mbox_bgx_port_conf_t *conf); int octeontx_bgx_port_close(int port); int octeontx_bgx_port_start(int port); @@ -163,6 +173,8 @@ int octeontx_bgx_port_get_fifo_cfg(int port, octeontx_mbox_bgx_port_fifo_cfg_t *cfg); int octeontx_bgx_port_flow_ctrl_cfg(int port, octeontx_mbox_bgx_port_fc_cfg_t *cfg); +int octeontx_bgx_port_change_mode(int port, + octeontx_mbox_bgx_port_change_mode_t *cfg); #endif /* __OCTEONTX_BGX_H__ */ diff --git a/drivers/net/octeontx/octeontx_ethdev.c b/drivers/net/octeontx/octeontx_ethdev.c index 6469fd0a96..9b13e22089 100644 --- a/drivers/net/octeontx/octeontx_ethdev.c +++ b/drivers/net/octeontx/octeontx_ethdev.c @@ -31,6 +31,9 @@ */ uint16_t evdev_refcnt; +#define OCTEONTX_QLM_MODE_SGMII 7 +#define OCTEONTX_QLM_MODE_XFI 12 + struct evdev_priv_data { OFFLOAD_FLAGS; /*Sequence should not be changed */ } __rte_cache_aligned; @@ -50,7 +53,8 @@ enum octeontx_link_speed { OCTEONTX_LINK_SPEED_40G_R, OCTEONTX_LINK_SPEED_RESERVE1, OCTEONTX_LINK_SPEED_QSGMII, - OCTEONTX_LINK_SPEED_RESERVE2 + OCTEONTX_LINK_SPEED_RESERVE2, + OCTEONTX_LINK_SPEED_UNKNOWN = 255 }; RTE_LOG_REGISTER_SUFFIX(otx_net_logtype_mbox, mbox, NOTICE); @@ -139,6 +143,7 @@ octeontx_port_open(struct octeontx_nic *nic) nic->mcast_mode = bgx_port_conf.mcast_mode; nic->speed = bgx_port_conf.mode; + nic->duplex = RTE_ETH_LINK_FULL_DUPLEX; memset(&fifo_cfg, 0x0, sizeof(fifo_cfg)); res = octeontx_bgx_port_get_fifo_cfg(nic->port_id, &fifo_cfg); @@ -171,6 +176,67 @@ octeontx_link_status_print(struct rte_eth_dev *eth_dev, (int)(eth_dev->data->port_id)); } +static inline uint32_t +octeontx_parse_link_speeds(uint32_t link_speeds) +{ + uint32_t link_speed = OCTEONTX_LINK_SPEED_UNKNOWN; + + if (link_speeds & RTE_ETH_LINK_SPEED_40G) + link_speed = OCTEONTX_LINK_SPEED_40G_R; + + if (link_speeds & RTE_ETH_LINK_SPEED_10G) { + link_speed = OCTEONTX_LINK_SPEED_XAUI; + link_speed |= OCTEONTX_LINK_SPEED_RXAUI; + link_speed |= OCTEONTX_LINK_SPEED_10G_R; + } + + if (link_speeds & RTE_ETH_LINK_SPEED_5G) + link_speed = OCTEONTX_LINK_SPEED_QSGMII; + + if (link_speeds & RTE_ETH_LINK_SPEED_1G) + link_speed = OCTEONTX_LINK_SPEED_SGMII; + + return link_speed; +} + +static inline uint8_t +octeontx_parse_eth_link_duplex(uint32_t link_speeds) +{ + if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) || + (link_speeds & RTE_ETH_LINK_SPEED_100M_HD)) + return RTE_ETH_LINK_HALF_DUPLEX; + else + return RTE_ETH_LINK_FULL_DUPLEX; +} + +static int +octeontx_apply_link_speed(struct rte_eth_dev *dev) +{ + struct octeontx_nic *nic = octeontx_pmd_priv(dev); + struct rte_eth_conf *conf = &dev->data->dev_conf; + octeontx_mbox_bgx_port_change_mode_t cfg; + + if (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) + return 0; + + cfg.speed = octeontx_parse_link_speeds(conf->link_speeds); + cfg.autoneg = (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) ? 1 : 0; + cfg.duplex = octeontx_parse_eth_link_duplex(conf->link_speeds); + cfg.qlm_mode = ((conf->link_speeds & RTE_ETH_LINK_SPEED_1G) ? + OCTEONTX_QLM_MODE_SGMII : + (conf->link_speeds & RTE_ETH_LINK_SPEED_10G) ? + OCTEONTX_QLM_MODE_XFI : 0); + + if (cfg.speed != OCTEONTX_LINK_SPEED_UNKNOWN && + (cfg.speed != nic->speed || cfg.duplex != nic->duplex)) { + nic->speed = cfg.speed; + nic->duplex = cfg.duplex; + return octeontx_bgx_port_change_mode(nic->port_id, &cfg); + } else { + return 0; + } +} + static void octeontx_link_status_update(struct octeontx_nic *nic, struct rte_eth_link *link) @@ -440,11 +506,6 @@ octeontx_dev_configure(struct rte_eth_dev *dev) txmode->offloads |= RTE_ETH_TX_OFFLOAD_MT_LOCKFREE; } - if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { - octeontx_log_err("setting link speed/duplex not supported"); - return -EINVAL; - } - if (conf->dcb_capability_en) { octeontx_log_err("DCB enable not supported"); return -EINVAL; @@ -621,6 +682,13 @@ octeontx_dev_start(struct rte_eth_dev *dev) goto error; } + /* Apply new link configurations if changed */ + ret = octeontx_apply_link_speed(dev); + if (ret) { + octeontx_log_err("Failed to set link configuration: %d", ret); + goto error; + } + /* * Tx start */ From patchwork Tue May 24 08:42:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harman Kalra X-Patchwork-Id: 111712 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 06FD4A04FF; Tue, 24 May 2022 10:43:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6FF154280B; Tue, 24 May 2022 10:43:03 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 77F124280B for ; Tue, 24 May 2022 10:43:01 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24NNBSVl022568 for ; Tue, 24 May 2022 01:43:00 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=jOy7EubK7vNenOa6roLFVdCH4P87nvUoC7Ok1WOMyCo=; b=HWvZ7hXzmsAppB19geZexvS+wMRZepNKwJj5wd7KiIuU6fj5OmvKidI/7U+oz2g8q4lh fKFF5tbEE5NDQ8sNrkqLyonDSrcNSpFDl/tIhVKPfj8uftdklTNk9Br7Q5wjGmxDxE6U KS82GDjMaCimFtMd9k3QDkqbg3icH4kYe0AairTosqX5vLeav5pl3WNNmZ0B+Wqj347h 6UMIWRMx0qVBqvNLymxkL7GT9e8QgJ2GPRZEVM3xH+gOxQsq6R3HNHrvzijfIjoU9iI1 gruHYDkNKtaSZIbWDUkNVsHdT1nfrD5hOfaMclwbWOCI1ceE3/lue62AiBqtnW+M0uWz ew== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3g8kqjhrtr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 24 May 2022 01:43:00 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 24 May 2022 01:42:58 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 24 May 2022 01:42:59 -0700 Received: from localhost.localdomain (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id E3CB13F709B; Tue, 24 May 2022 01:42:57 -0700 (PDT) From: Harman Kalra To: , Harman Kalra Subject: [PATCH v3 04/11] net/octeontx: handle port reconfiguration Date: Tue, 24 May 2022 14:12:28 +0530 Message-ID: <20220524084235.17796-4-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220524084235.17796-1-hkalra@marvell.com> References: <20220517173941.189330-2-hkalra@marvell.com> <20220524084235.17796-1-hkalra@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: pwZX92FdXzyAjUsJoSC84ofZlGFhk2U5 X-Proofpoint-GUID: pwZX92FdXzyAjUsJoSC84ofZlGFhk2U5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-24_06,2022-05-23_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding support for port reconfiguration as user may require to do so on a running system. Signed-off-by: Harman Kalra --- drivers/net/octeontx/octeontx_ethdev.c | 38 +++++++++++++++----------- drivers/net/octeontx/octeontx_ethdev.h | 1 + 2 files changed, 23 insertions(+), 16 deletions(-) diff --git a/drivers/net/octeontx/octeontx_ethdev.c b/drivers/net/octeontx/octeontx_ethdev.c index 9b13e22089..9351fcb5c7 100644 --- a/drivers/net/octeontx/octeontx_ethdev.c +++ b/drivers/net/octeontx/octeontx_ethdev.c @@ -518,30 +518,34 @@ octeontx_dev_configure(struct rte_eth_dev *dev) nic->num_tx_queues = dev->data->nb_tx_queues; - ret = octeontx_pko_channel_open(nic->pko_vfid * PKO_VF_NUM_DQ, - nic->num_tx_queues, - nic->base_ochan); - if (ret) { - octeontx_log_err("failed to open channel %d no-of-txq %d", - nic->base_ochan, nic->num_tx_queues); - return -EFAULT; - } + if (!nic->reconfigure) { + ret = octeontx_pko_channel_open(nic->pko_vfid * PKO_VF_NUM_DQ, + nic->num_tx_queues, + nic->base_ochan); + if (ret) { + octeontx_log_err("failed to open channel %d no-of-txq %d", + nic->base_ochan, nic->num_tx_queues); + return -EFAULT; + } - ret = octeontx_dev_vlan_offload_init(dev); - if (ret) { - octeontx_log_err("failed to initialize vlan offload"); - return -EFAULT; - } + ret = octeontx_dev_vlan_offload_init(dev); + if (ret) { + octeontx_log_err("failed to initialize vlan offload"); + return -EFAULT; + } - nic->pki.classifier_enable = false; - nic->pki.hash_enable = true; - nic->pki.initialized = false; + nic->pki.classifier_enable = false; + nic->pki.hash_enable = true; + nic->pki.initialized = false; + } nic->rx_offloads |= rxmode->offloads; nic->tx_offloads |= txmode->offloads; nic->rx_offload_flags |= octeontx_rx_offload_flags(dev); nic->tx_offload_flags |= octeontx_tx_offload_flags(dev); + nic->reconfigure = true; + return 0; } @@ -583,6 +587,7 @@ octeontx_dev_close(struct rte_eth_dev *dev) } octeontx_port_close(nic); + nic->reconfigure = false; return 0; } @@ -1431,6 +1436,7 @@ octeontx_create(struct rte_vdev_device *dev, int port, uint8_t evdev, nic->ev_queues = 1; nic->ev_ports = 1; nic->print_flag = -1; + nic->reconfigure = false; data->dev_link.link_status = RTE_ETH_LINK_DOWN; data->dev_started = 0; diff --git a/drivers/net/octeontx/octeontx_ethdev.h b/drivers/net/octeontx/octeontx_ethdev.h index c493fa7a03..7e04faddb8 100644 --- a/drivers/net/octeontx/octeontx_ethdev.h +++ b/drivers/net/octeontx/octeontx_ethdev.h @@ -144,6 +144,7 @@ struct octeontx_nic { struct octeontx_vlan_info vlan_info; int print_flag; struct octeontx_fc_info fc; + bool reconfigure; } __rte_cache_aligned; struct octeontx_txq { From patchwork Tue May 24 08:42:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harman Kalra X-Patchwork-Id: 111713 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 447ADA04FF; Tue, 24 May 2022 10:43:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 65DB640A84; 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Tue, 24 May 2022 01:43:04 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 24 May 2022 01:43:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 24 May 2022 01:43:01 -0700 Received: from localhost.localdomain (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id 9F1823F709F; Tue, 24 May 2022 01:43:00 -0700 (PDT) From: Harman Kalra To: , Jerin Jacob , Maciej Czekaj CC: Hanumanth Pothula Subject: [PATCH v3 05/11] net/thunderx: implement polling of link state change Date: Tue, 24 May 2022 14:12:29 +0530 Message-ID: <20220524084235.17796-5-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220524084235.17796-1-hkalra@marvell.com> References: <20220517173941.189330-2-hkalra@marvell.com> <20220524084235.17796-1-hkalra@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 90W3NYG8iwniZ5KjJPLBYOGFQLq8go07 X-Proofpoint-GUID: 90W3NYG8iwniZ5KjJPLBYOGFQLq8go07 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-24_06,2022-05-23_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Hanumanth Pothula Moving the logic of link polling to VF from PF. Now VF is supposed to poll for the link status, rather PF alerting VF about any link change. Signed-off-by: Hanumanth Pothula --- drivers/net/thunderx/base/nicvf_mbox.c | 9 ++++++++ drivers/net/thunderx/base/nicvf_mbox.h | 1 + drivers/net/thunderx/nicvf_ethdev.c | 32 ++++++++++++++------------ drivers/net/thunderx/nicvf_ethdev.h | 10 ++++---- 4 files changed, 33 insertions(+), 19 deletions(-) diff --git a/drivers/net/thunderx/base/nicvf_mbox.c b/drivers/net/thunderx/base/nicvf_mbox.c index d7209c0083..281027ccce 100644 --- a/drivers/net/thunderx/base/nicvf_mbox.c +++ b/drivers/net/thunderx/base/nicvf_mbox.c @@ -440,3 +440,12 @@ nicvf_mbox_cfg_done(struct nicvf *nic) mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE; nicvf_mbox_send_async_msg_to_pf(nic, &mbx); } + +void +nicvf_mbox_link_change(struct nicvf *nic) +{ + struct nic_mbx mbx = { .msg = { 0 } }; + + mbx.msg.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE; + nicvf_mbox_send_async_msg_to_pf(nic, &mbx); +} diff --git a/drivers/net/thunderx/base/nicvf_mbox.h b/drivers/net/thunderx/base/nicvf_mbox.h index d0b294362c..490bed206b 100644 --- a/drivers/net/thunderx/base/nicvf_mbox.h +++ b/drivers/net/thunderx/base/nicvf_mbox.h @@ -222,5 +222,6 @@ int nicvf_mbox_reset_stat_counters(struct nicvf *nic, uint16_t rx_stat_mask, int nicvf_mbox_set_link_up_down(struct nicvf *nic, bool enable); void nicvf_mbox_shutdown(struct nicvf *nic); void nicvf_mbox_cfg_done(struct nicvf *nic); +void nicvf_mbox_link_change(struct nicvf *nic); #endif /* __THUNDERX_NICVF_MBOX__ */ diff --git a/drivers/net/thunderx/nicvf_ethdev.c b/drivers/net/thunderx/nicvf_ethdev.c index fc334cf734..addbd53735 100644 --- a/drivers/net/thunderx/nicvf_ethdev.c +++ b/drivers/net/thunderx/nicvf_ethdev.c @@ -71,6 +71,9 @@ nicvf_link_status_update(struct nicvf *nic, link->link_autoneg = RTE_ETH_LINK_AUTONEG; } +/*Poll for link status change by sending NIC_MBOX_MSG_BGX_LINK_CHANGE msg + * periodically to PF. + */ static void nicvf_interrupt(void *arg) { @@ -78,7 +81,10 @@ nicvf_interrupt(void *arg) struct nicvf *nic = nicvf_pmd_priv(dev); struct rte_eth_link link; - if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) { + rte_eth_linkstatus_get(dev, &link); + + nicvf_mbox_link_change(nic); + if (nic->link_up != link.link_status) { if (dev->data->dev_conf.intr_conf.lsc) { nicvf_link_status_update(nic, &link); rte_eth_linkstatus_set(dev, &link); @@ -89,7 +95,7 @@ nicvf_interrupt(void *arg) } } - rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, + rte_eal_alarm_set(NICVF_INTR_LINK_POLL_INTERVAL_MS * 1000, nicvf_interrupt, dev); } @@ -1841,7 +1847,6 @@ nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup) static int nicvf_dev_close(struct rte_eth_dev *dev) { - size_t i; struct nicvf *nic = nicvf_pmd_priv(dev); PMD_INIT_FUNC_TRACE(); @@ -1850,13 +1855,7 @@ nicvf_dev_close(struct rte_eth_dev *dev) nicvf_dev_stop_cleanup(dev, true); nicvf_periodic_alarm_stop(nicvf_interrupt, dev); - - for (i = 0; i < nic->sqs_count; i++) { - if (!nic->snicvf[i]) - continue; - - nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]); - } + nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic); rte_intr_instance_free(nic->intr_handle); @@ -2169,6 +2168,14 @@ nicvf_eth_dev_init(struct rte_eth_dev *eth_dev) nicvf_disable_all_interrupts(nic); + /* To read mbox messages */ + ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic); + if (ret) { + PMD_INIT_LOG(ERR, "Failed to start period alarm"); + goto fail; + } + + /* To poll link status change*/ ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev); if (ret) { PMD_INIT_LOG(ERR, "Failed to start period alarm"); @@ -2203,11 +2210,6 @@ nicvf_eth_dev_init(struct rte_eth_dev *eth_dev) eth_dev->data->dev_private = NULL; nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); - ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic); - if (ret) { - PMD_INIT_LOG(ERR, "Failed to start period alarm"); - goto fail; - } /* Detach port by returning positive error number */ return ENOTSUP; diff --git a/drivers/net/thunderx/nicvf_ethdev.h b/drivers/net/thunderx/nicvf_ethdev.h index cb474e26b8..a947b55fd4 100644 --- a/drivers/net/thunderx/nicvf_ethdev.h +++ b/drivers/net/thunderx/nicvf_ethdev.h @@ -10,10 +10,12 @@ #define THUNDERX_NICVF_PMD_VERSION "2.0" #define THUNDERX_REG_BYTES 8 -#define NICVF_INTR_POLL_INTERVAL_MS 50 -#define NICVF_HALF_DUPLEX 0x00 -#define NICVF_FULL_DUPLEX 0x01 -#define NICVF_UNKNOWN_DUPLEX 0xff +#define NICVF_INTR_POLL_INTERVAL_MS 50 +/* Poll for link state for every 2 sec */ +#define NICVF_INTR_LINK_POLL_INTERVAL_MS 2000 +#define NICVF_HALF_DUPLEX 0x00 +#define NICVF_FULL_DUPLEX 0x01 +#define NICVF_UNKNOWN_DUPLEX 0xff #define NICVF_RSS_OFFLOAD_PASS1 ( \ RTE_ETH_RSS_PORT | \ From patchwork Tue May 24 08:42:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harman Kalra X-Patchwork-Id: 111714 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 285FFA04FF; Tue, 24 May 2022 10:43:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 61B2742B6C; Tue, 24 May 2022 10:43:09 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id D8C5E42B6C for ; Tue, 24 May 2022 10:43:07 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24NNBPA1022543 for ; Tue, 24 May 2022 01:43:07 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; 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Tue, 24 May 2022 01:43:03 -0700 (PDT) From: Harman Kalra To: , Jerin Jacob , Maciej Czekaj CC: Hanumanth Pothula Subject: [PATCH v3 06/11] net/thunderx: reset Rx DMAC control register Date: Tue, 24 May 2022 14:12:30 +0530 Message-ID: <20220524084235.17796-6-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220524084235.17796-1-hkalra@marvell.com> References: <20220517173941.189330-2-hkalra@marvell.com> <20220524084235.17796-1-hkalra@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: teEtD9Hih4glaC24SzM5uNYmTuGjGyV6 X-Proofpoint-GUID: teEtD9Hih4glaC24SzM5uNYmTuGjGyV6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-24_06,2022-05-23_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Hanumanth Pothula During initialization, reset RX DMAC control register by sending mbox message NIC_MBOX_MSG_RESET_XCAST to PF. Signed-off-by: Hanumanth Pothula --- drivers/net/thunderx/base/nicvf_mbox.c | 9 +++++++++ drivers/net/thunderx/base/nicvf_mbox.h | 2 ++ drivers/net/thunderx/nicvf_ethdev.c | 3 +++ 3 files changed, 14 insertions(+) diff --git a/drivers/net/thunderx/base/nicvf_mbox.c b/drivers/net/thunderx/base/nicvf_mbox.c index 281027ccce..275e593286 100644 --- a/drivers/net/thunderx/base/nicvf_mbox.c +++ b/drivers/net/thunderx/base/nicvf_mbox.c @@ -449,3 +449,12 @@ nicvf_mbox_link_change(struct nicvf *nic) mbx.msg.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE; nicvf_mbox_send_async_msg_to_pf(nic, &mbx); } + +void +nicvf_mbox_reset_xcast(struct nicvf *nic) +{ + struct nic_mbx mbx = { .msg = { 0 } }; + + mbx.msg.msg = NIC_MBOX_MSG_RESET_XCAST; + nicvf_mbox_send_msg_to_pf(nic, &mbx); +} diff --git a/drivers/net/thunderx/base/nicvf_mbox.h b/drivers/net/thunderx/base/nicvf_mbox.h index 490bed206b..044220a2cd 100644 --- a/drivers/net/thunderx/base/nicvf_mbox.h +++ b/drivers/net/thunderx/base/nicvf_mbox.h @@ -43,6 +43,7 @@ #define NIC_MBOX_MSG_SET_LINK 0x21 /* Set link up/down */ #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */ #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */ +#define NIC_MBOX_MSG_RESET_XCAST 0xF2 /* Reset DCAM filtering mode */ #define NIC_MBOX_MSG_MAX 0x100 /* Maximum number of messages */ /* Get vNIC VF configuration */ @@ -223,5 +224,6 @@ int nicvf_mbox_set_link_up_down(struct nicvf *nic, bool enable); void nicvf_mbox_shutdown(struct nicvf *nic); void nicvf_mbox_cfg_done(struct nicvf *nic); void nicvf_mbox_link_change(struct nicvf *nic); +void nicvf_mbox_reset_xcast(struct nicvf *nic); #endif /* __THUNDERX_NICVF_MBOX__ */ diff --git a/drivers/net/thunderx/nicvf_ethdev.c b/drivers/net/thunderx/nicvf_ethdev.c index addbd53735..1e268d9b0f 100644 --- a/drivers/net/thunderx/nicvf_ethdev.c +++ b/drivers/net/thunderx/nicvf_ethdev.c @@ -2196,6 +2196,9 @@ nicvf_eth_dev_init(struct rte_eth_dev *eth_dev) ); } + /* To make sure RX DMAC register is set to default value (0x3) */ + nicvf_mbox_reset_xcast(nic); + ret = nicvf_base_init(nic); if (ret) { PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init"); From patchwork Tue May 24 08:42:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harman Kalra X-Patchwork-Id: 111715 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2CCACA04FF; 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Tue, 24 May 2022 01:43:10 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 24 May 2022 01:43:08 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 24 May 2022 01:43:08 -0700 Received: from localhost.localdomain (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id D64AA3F709B; Tue, 24 May 2022 01:43:06 -0700 (PDT) From: Harman Kalra To: , Jerin Jacob , Maciej Czekaj CC: Harman Kalra Subject: [PATCH v3 07/11] net/thunderx: setting link attributes Date: Tue, 24 May 2022 14:12:31 +0530 Message-ID: <20220524084235.17796-7-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220524084235.17796-1-hkalra@marvell.com> References: <20220517173941.189330-2-hkalra@marvell.com> <20220524084235.17796-1-hkalra@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ZjIHxfUzWXasYd41VXiTtSFKer0cfDMR X-Proofpoint-ORIG-GUID: ZjIHxfUzWXasYd41VXiTtSFKer0cfDMR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-24_05,2022-05-23_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding support to configure link attributes like speed, duplex, negotiation. Signed-off-by: Harman Kalra --- drivers/net/thunderx/base/nicvf_mbox.c | 16 +++++ drivers/net/thunderx/base/nicvf_mbox.h | 14 ++++ drivers/net/thunderx/nicvf_ethdev.c | 88 ++++++++++++++++++++++++-- drivers/net/thunderx/nicvf_struct.h | 9 +++ 4 files changed, 122 insertions(+), 5 deletions(-) diff --git a/drivers/net/thunderx/base/nicvf_mbox.c b/drivers/net/thunderx/base/nicvf_mbox.c index 275e593286..352b85d9e2 100644 --- a/drivers/net/thunderx/base/nicvf_mbox.c +++ b/drivers/net/thunderx/base/nicvf_mbox.c @@ -423,6 +423,22 @@ nicvf_mbox_set_link_up_down(struct nicvf *nic, bool enable) mbx.lbk.enable = enable; return nicvf_mbox_send_msg_to_pf(nic, &mbx); } + + +int +nicvf_mbox_change_mode(struct nicvf *nic, struct change_link_mode *cfg) +{ + struct nic_mbx mbx = { .msg = { 0 } }; + + mbx.mode.msg = NIC_MBOX_MSG_CHANGE_MODE; + mbx.mode.vf_id = nic->vf_id; + mbx.mode.speed = cfg->speed; + mbx.mode.duplex = cfg->duplex; + mbx.mode.autoneg = cfg->autoneg; + mbx.mode.qlm_mode = cfg->qlm_mode; + return nicvf_mbox_send_msg_to_pf(nic, &mbx); +} + void nicvf_mbox_shutdown(struct nicvf *nic) { diff --git a/drivers/net/thunderx/base/nicvf_mbox.h b/drivers/net/thunderx/base/nicvf_mbox.h index 044220a2cd..322c8159cb 100644 --- a/drivers/net/thunderx/base/nicvf_mbox.h +++ b/drivers/net/thunderx/base/nicvf_mbox.h @@ -41,6 +41,7 @@ #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */ #define NIC_MBOX_MSG_RESET_STAT_COUNTER 0x17 /* Reset statistics counters */ #define NIC_MBOX_MSG_SET_LINK 0x21 /* Set link up/down */ +#define NIC_MBOX_MSG_CHANGE_MODE 0x22 /* Change mode */ #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */ #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */ #define NIC_MBOX_MSG_RESET_XCAST 0xF2 /* Reset DCAM filtering mode */ @@ -178,6 +179,17 @@ struct set_link_state { bool enable; }; +/* Change link mode */ +struct change_link_mode_msg { + uint8_t msg; + uint8_t vf_id; + uint8_t qlm_mode; + bool autoneg; + uint8_t duplex; + uint32_t speed; + +}; + struct nic_mbx { /* 128 bit shared memory between PF and each VF */ union { @@ -196,6 +208,7 @@ union { struct set_loopback lbk; struct reset_stat_cfg reset_stat; struct set_link_state set_link; + struct change_link_mode_msg mode; }; }; @@ -225,5 +238,6 @@ void nicvf_mbox_shutdown(struct nicvf *nic); void nicvf_mbox_cfg_done(struct nicvf *nic); void nicvf_mbox_link_change(struct nicvf *nic); void nicvf_mbox_reset_xcast(struct nicvf *nic); +int nicvf_mbox_change_mode(struct nicvf *nic, struct change_link_mode *cfg); #endif /* __THUNDERX_NICVF_MBOX__ */ diff --git a/drivers/net/thunderx/nicvf_ethdev.c b/drivers/net/thunderx/nicvf_ethdev.c index 1e268d9b0f..0f79b02172 100644 --- a/drivers/net/thunderx/nicvf_ethdev.c +++ b/drivers/net/thunderx/nicvf_ethdev.c @@ -55,6 +55,82 @@ RTE_LOG_REGISTER_SUFFIX(nicvf_logtype_mbox, mbox, NOTICE); RTE_LOG_REGISTER_SUFFIX(nicvf_logtype_init, init, NOTICE); RTE_LOG_REGISTER_SUFFIX(nicvf_logtype_driver, driver, NOTICE); +#define NICVF_QLM_MODE_SGMII 7 +#define NICVF_QLM_MODE_XFI 12 + +enum nicvf_link_speed { + NICVF_LINK_SPEED_SGMII, + NICVF_LINK_SPEED_XAUI, + NICVF_LINK_SPEED_RXAUI, + NICVF_LINK_SPEED_10G_R, + NICVF_LINK_SPEED_40G_R, + NICVF_LINK_SPEED_RESERVE1, + NICVF_LINK_SPEED_QSGMII, + NICVF_LINK_SPEED_RESERVE2, + NICVF_LINK_SPEED_UNKNOWN = 255 +}; + +static inline uint32_t +nicvf_parse_link_speeds(uint32_t link_speeds) +{ + uint32_t link_speed = NICVF_LINK_SPEED_UNKNOWN; + + if (link_speeds & RTE_ETH_LINK_SPEED_40G) + link_speed = NICVF_LINK_SPEED_40G_R; + + if (link_speeds & RTE_ETH_LINK_SPEED_10G) { + link_speed = NICVF_LINK_SPEED_XAUI; + link_speed |= NICVF_LINK_SPEED_RXAUI; + link_speed |= NICVF_LINK_SPEED_10G_R; + } + + if (link_speeds & RTE_ETH_LINK_SPEED_5G) + link_speed = NICVF_LINK_SPEED_QSGMII; + + if (link_speeds & RTE_ETH_LINK_SPEED_1G) + link_speed = NICVF_LINK_SPEED_SGMII; + + return link_speed; +} + +static inline uint8_t +nicvf_parse_eth_link_duplex(uint32_t link_speeds) +{ + if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) || + (link_speeds & RTE_ETH_LINK_SPEED_100M_HD)) + return RTE_ETH_LINK_HALF_DUPLEX; + else + return RTE_ETH_LINK_FULL_DUPLEX; +} + +static int +nicvf_apply_link_speed(struct rte_eth_dev *dev) +{ + struct nicvf *nic = nicvf_pmd_priv(dev); + struct rte_eth_conf *conf = &dev->data->dev_conf; + struct change_link_mode cfg; + if (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) + /* TODO: Handle this case */ + return 0; + + cfg.speed = nicvf_parse_link_speeds(conf->link_speeds); + cfg.autoneg = (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) ? 1 : 0; + cfg.duplex = nicvf_parse_eth_link_duplex(conf->link_speeds); + cfg.qlm_mode = ((conf->link_speeds & RTE_ETH_LINK_SPEED_1G) ? + NICVF_QLM_MODE_SGMII : + (conf->link_speeds & RTE_ETH_LINK_SPEED_10G) ? + NICVF_QLM_MODE_XFI : 0); + + if (cfg.speed != NICVF_LINK_SPEED_UNKNOWN && + (cfg.speed != nic->speed || cfg.duplex != nic->duplex)) { + nic->speed = cfg.speed; + nic->duplex = cfg.duplex; + return nicvf_mbox_change_mode(nic, &cfg); + } else { + return 0; + } +} + static void nicvf_link_status_update(struct nicvf *nic, struct rte_eth_link *link) @@ -1728,6 +1804,13 @@ nicvf_dev_start(struct rte_eth_dev *dev) return -EBUSY; } + /* Apply new link configurations if changed */ + ret = nicvf_apply_link_speed(dev); + if (ret) { + PMD_INIT_LOG(ERR, "Failed to set link configuration\n"); + return ret; + } + ret = nicvf_vf_start(dev, nic, rbdrsz); if (ret != 0) return ret; @@ -1921,11 +2004,6 @@ nicvf_dev_configure(struct rte_eth_dev *dev) return -EINVAL; } - if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { - PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported"); - return -EINVAL; - } - if (conf->dcb_capability_en) { PMD_INIT_LOG(INFO, "DCB enable not supported"); return -EINVAL; diff --git a/drivers/net/thunderx/nicvf_struct.h b/drivers/net/thunderx/nicvf_struct.h index c7ea13313e..13cf8feeb1 100644 --- a/drivers/net/thunderx/nicvf_struct.h +++ b/drivers/net/thunderx/nicvf_struct.h @@ -113,4 +113,13 @@ struct nicvf { struct nicvf *snicvf[MAX_SQS_PER_VF]; } __rte_cache_aligned; +struct change_link_mode { + bool enable; + uint8_t qlm_mode; + bool autoneg; + uint8_t duplex; + uint32_t speed; + +}; + #endif /* _THUNDERX_NICVF_STRUCT_H */ From patchwork Tue May 24 08:42:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harman Kalra X-Patchwork-Id: 111716 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8B767A04FF; Tue, 24 May 2022 10:43:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 963CF42B74; Tue, 24 May 2022 10:43:16 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 69C6C400D6 for ; Tue, 24 May 2022 10:43:13 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24NNBIli022495 for ; Tue, 24 May 2022 01:43:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=WRK71imUJqtV8MoDM64xYjMofiiJ2L8Jafm+mAwcy/E=; b=MTJSwHbFtrLV7ClivcIT+OxKnV0QEt9r7vq3LXTZqcZFXcQE9dwlyb0e7AfN6jzYauP0 jSRaA911+neG7Kuga7Etj8JlTFD6T5OosOwCQOCIy7mVicmIg7pqQSgSJ1wqov3HZ6uE pyP2oBCV1rPFcMtaHXNJWM0QObIBO0PZXfm2uUSMuD7trlPQmia5ilKMH0yxT2/TUNQr dxa9yFG1LdKqvLrkYAjHHyKD9lmRXeEHTVURgtbI+9VcmdssFZ8lKDbCwiW2Q7uRzdPL wO/lLH/MvhD7+JMob01xmUtrxCp0/LTWHxa28ZZI6hxTiGak9MT6DFj/iHj9tCUvdy9E Nw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3g8kqjhrv6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 24 May 2022 01:43:12 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 24 May 2022 01:43:10 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 24 May 2022 01:43:11 -0700 Received: from localhost.localdomain (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id D6BE53F709B; Tue, 24 May 2022 01:43:09 -0700 (PDT) From: Harman Kalra To: , Harman Kalra Subject: [PATCH v3 08/11] net/octeontx: implement xstats Date: Tue, 24 May 2022 14:12:32 +0530 Message-ID: <20220524084235.17796-8-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220524084235.17796-1-hkalra@marvell.com> References: <20220517173941.189330-2-hkalra@marvell.com> <20220524084235.17796-1-hkalra@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: kT7FXZEYG9jalwShK8KNBhNda2KxQl3u X-Proofpoint-GUID: kT7FXZEYG9jalwShK8KNBhNda2KxQl3u X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-24_06,2022-05-23_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding support for xstats eth operations. Signed-off-by: Harman Kalra --- drivers/net/octeontx/base/octeontx_bgx.c | 17 +++ drivers/net/octeontx/base/octeontx_bgx.h | 3 + drivers/net/octeontx/octeontx_ethdev.c | 126 +++++++++++++++++++++++ drivers/net/octeontx/octeontx_stats.h | 41 ++++++++ 4 files changed, 187 insertions(+) create mode 100644 drivers/net/octeontx/octeontx_stats.h diff --git a/drivers/net/octeontx/base/octeontx_bgx.c b/drivers/net/octeontx/base/octeontx_bgx.c index 1c6fa05ebc..81a8cbecaf 100644 --- a/drivers/net/octeontx/base/octeontx_bgx.c +++ b/drivers/net/octeontx/base/octeontx_bgx.c @@ -144,6 +144,23 @@ octeontx_bgx_port_status(int port, octeontx_mbox_bgx_port_status_t *stat) return res; } +int +octeontx_bgx_port_xstats(int port, octeontx_mbox_bgx_port_stats_t *stats) +{ + struct octeontx_mbox_hdr hdr; + int len = sizeof(octeontx_mbox_bgx_port_stats_t); + int res; + + hdr.coproc = OCTEONTX_BGX_COPROC; + hdr.msg = MBOX_BGX_PORT_GET_STATS; + hdr.vfid = port; + + res = octeontx_mbox_send(&hdr, NULL, 0, stats, len); + if (res < 0) + return -EACCES; + return res; +} + int octeontx_bgx_port_stats(int port, octeontx_mbox_bgx_port_stats_t *stats) { diff --git a/drivers/net/octeontx/base/octeontx_bgx.h b/drivers/net/octeontx/base/octeontx_bgx.h index e4cfa3e73a..c5662202ac 100644 --- a/drivers/net/octeontx/base/octeontx_bgx.h +++ b/drivers/net/octeontx/base/octeontx_bgx.h @@ -117,6 +117,8 @@ typedef struct octeontx_mbox_bgx_port_stats { uint64_t rx_oversize_errors; uint64_t rx_fragmented_errors; uint64_t rx_jabber_errors; + uint64_t rx_pause_packets; + uint64_t tx_pause_packets; } octeontx_mbox_bgx_port_stats_t; struct octeontx_mbox_bgx_port_mac_filter { @@ -161,6 +163,7 @@ int octeontx_bgx_port_get_config(int port, octeontx_mbox_bgx_port_conf_t *conf); int octeontx_bgx_port_status(int port, octeontx_mbox_bgx_port_status_t *stat); int octeontx_bgx_port_stats(int port, octeontx_mbox_bgx_port_stats_t *stats); int octeontx_bgx_port_stats_clr(int port); +int octeontx_bgx_port_xstats(int port, octeontx_mbox_bgx_port_stats_t *stats); int octeontx_bgx_port_link_status(int port); int octeontx_bgx_port_promisc_set(int port, int en); int octeontx_bgx_port_mac_set(int port, uint8_t *mac_addr); diff --git a/drivers/net/octeontx/octeontx_ethdev.c b/drivers/net/octeontx/octeontx_ethdev.c index 9351fcb5c7..c15014bdde 100644 --- a/drivers/net/octeontx/octeontx_ethdev.c +++ b/drivers/net/octeontx/octeontx_ethdev.c @@ -25,6 +25,7 @@ #include "octeontx_ethdev.h" #include "octeontx_rxtx.h" #include "octeontx_logs.h" +#include "octeontx_stats.h" /* Useful in stopping/closing event device if no of * eth ports are using it. @@ -846,6 +847,127 @@ octeontx_dev_link_update(struct rte_eth_dev *dev, return rte_eth_linkstatus_set(dev, &link); } +static inline int octeontx_dev_total_xstat(void) +{ + return NUM_BGX_XSTAT; +} + +static int +octeontx_port_xstats(struct octeontx_nic *nic, struct rte_eth_xstat *xstats, + unsigned int n) +{ + octeontx_mbox_bgx_port_stats_t bgx_stats; + int stat_cnt, res, si, i; + + res = octeontx_bgx_port_xstats(nic->port_id, &bgx_stats); + if (res < 0) { + octeontx_log_err("failed to get port stats %d", nic->port_id); + return res; + } + + si = 0; + /* Fill BGX stats */ + stat_cnt = (n > NUM_BGX_XSTAT) ? NUM_BGX_XSTAT : n; + n = n - stat_cnt; + for (i = 0; i < stat_cnt; i++) { + xstats[si].id = si; + xstats[si].value = *(uint64_t *)(((char *)&bgx_stats) + + octeontx_bgx_xstats[i].soffset); + si++; + } + /*TODO: Similarly fill rest of HW stats */ + + return si; +} + +static int +octeontx_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, + uint64_t *stat_val, unsigned int n) +{ + unsigned int i, xstat_cnt = octeontx_dev_total_xstat(); + struct octeontx_nic *nic = octeontx_pmd_priv(dev); + struct rte_eth_xstat xstats[xstat_cnt]; + + octeontx_port_xstats(nic, xstats, xstat_cnt); + for (i = 0; i < n; i++) { + if (ids[i] >= xstat_cnt) { + PMD_INIT_LOG(ERR, "out of range id value"); + return -1; + } + stat_val[i] = xstats[ids[i]].value; + } + return n; +} + +static int +octeontx_dev_xstats_get_names(struct rte_eth_dev *dev __rte_unused, + struct rte_eth_xstat_name *xstats_names, + unsigned int size) +{ + int stat_cnt, si, i; + + if (xstats_names) { + si = 0; + /* Fill BGX stats */ + stat_cnt = (size > NUM_BGX_XSTAT) ? NUM_BGX_XSTAT : size; + size = size - stat_cnt; + for (i = 0; i < stat_cnt; i++) { + strlcpy(xstats_names[si].name, + octeontx_bgx_xstats[i].sname, + sizeof(xstats_names[si].name)); + si++; + } + /*TODO: Similarly fill rest of HW stats */ + return si; + } else { + return octeontx_dev_total_xstat(); + } +} + +static void build_xstat_names(struct rte_eth_xstat_name *xstat_names) +{ + unsigned int i; + + for (i = 0; i < NUM_BGX_XSTAT; i++) { + strlcpy(xstat_names[i].name, octeontx_bgx_xstats[i].sname, + RTE_ETH_XSTATS_NAME_SIZE); + } +} + +static int +octeontx_dev_xstats_get_names_by_id(struct rte_eth_dev *dev __rte_unused, + const uint64_t *ids, + struct rte_eth_xstat_name *stat_names, + unsigned int n) +{ + unsigned int i, xstat_cnt = octeontx_dev_total_xstat(); + struct rte_eth_xstat_name xstat_names[xstat_cnt]; + + build_xstat_names(xstat_names); + for (i = 0; i < n; i++) { + if (ids[i] >= xstat_cnt) { + PMD_INIT_LOG(ERR, "out of range id value"); + return -1; + } + strlcpy(stat_names[i].name, xstat_names[ids[i]].name, + sizeof(stat_names[i].name)); + } + /*TODO: Similarly fill rest of HW stats */ + + return n; +} + +static int +octeontx_dev_xstats_get(struct rte_eth_dev *dev, + struct rte_eth_xstat *xstats, + unsigned int n) +{ + struct octeontx_nic *nic = octeontx_pmd_priv(dev); + + PMD_INIT_FUNC_TRACE(); + return octeontx_port_xstats(nic, xstats, n); +} + static int octeontx_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) { @@ -1354,6 +1476,10 @@ static const struct eth_dev_ops octeontx_dev_ops = { .pool_ops_supported = octeontx_pool_ops, .flow_ctrl_get = octeontx_dev_flow_ctrl_get, .flow_ctrl_set = octeontx_dev_flow_ctrl_set, + .xstats_get = octeontx_dev_xstats_get, + .xstats_get_by_id = octeontx_dev_xstats_get_by_id, + .xstats_get_names = octeontx_dev_xstats_get_names, + .xstats_get_names_by_id = octeontx_dev_xstats_get_names_by_id, }; /* Create Ethdev interface per BGX LMAC ports */ diff --git a/drivers/net/octeontx/octeontx_stats.h b/drivers/net/octeontx/octeontx_stats.h new file mode 100644 index 0000000000..95e03a993d --- /dev/null +++ b/drivers/net/octeontx/octeontx_stats.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#ifndef __OCTEONTX_STATS_H__ +#define __OCTEONTX_STATS_H__ + +#define BGX_XSTAT(stat) \ + {#stat, offsetof(octeontx_mbox_bgx_port_stats_t, stat)} +struct octeontx_xstats { + char sname[RTE_ETH_XSTATS_NAME_SIZE]; + uint32_t soffset; +}; + +struct octeontx_xstats octeontx_bgx_xstats[] = { + BGX_XSTAT(rx_packets), + BGX_XSTAT(tx_packets), + BGX_XSTAT(rx_broadcast_packets), + BGX_XSTAT(multicast), + BGX_XSTAT(tx_multicast_packets), + BGX_XSTAT(tx_broadcast_packets), + BGX_XSTAT(rx_undersized_errors), + BGX_XSTAT(rx_oversize_errors), + BGX_XSTAT(rx_jabber_errors), + BGX_XSTAT(rx_crc_errors), + BGX_XSTAT(collisions), + BGX_XSTAT(tx_1_to_64_packets), + BGX_XSTAT(tx_65_to_127_packets), + BGX_XSTAT(tx_128_to_255_packets), + BGX_XSTAT(tx_256_to_511_packets), + BGX_XSTAT(tx_512_to_1023_packets), + BGX_XSTAT(tx_1024_to_1522_packets), + BGX_XSTAT(tx_1523_to_max_packets), + BGX_XSTAT(rx_fragmented_errors), + BGX_XSTAT(rx_pause_packets), + BGX_XSTAT(tx_pause_packets), +}; + +#define NUM_BGX_XSTAT \ + (sizeof(octeontx_bgx_xstats) / sizeof(struct octeontx_xstats)) +#endif /* __OCTEONTX_STATS_H__ */ From patchwork Tue May 24 08:42:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harman Kalra X-Patchwork-Id: 111717 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9A27BA04FF; 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Tue, 24 May 2022 01:43:15 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 24 May 2022 01:43:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 24 May 2022 01:43:14 -0700 Received: from localhost.localdomain (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id B2F753F709F; Tue, 24 May 2022 01:43:12 -0700 (PDT) From: Harman Kalra To: , Harman Kalra Subject: [PATCH v3 09/11] net/octeontx: support allmulticast Date: Tue, 24 May 2022 14:12:33 +0530 Message-ID: <20220524084235.17796-9-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220524084235.17796-1-hkalra@marvell.com> References: <20220517173941.189330-2-hkalra@marvell.com> <20220524084235.17796-1-hkalra@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 9zvkmT_cDYrsoPJlL5GfINJqi5Sy4y2_ X-Proofpoint-GUID: 9zvkmT_cDYrsoPJlL5GfINJqi5Sy4y2_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-24_06,2022-05-23_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implement allmulticast operations for octeontx driver: rte_eth_allmulticast_enable()/rte_eth_allmulticast_disable(). Signed-off-by: Harman Kalra --- drivers/net/octeontx/base/octeontx_bgx.c | 19 ++++++++++ drivers/net/octeontx/base/octeontx_bgx.h | 1 + drivers/net/octeontx/octeontx_ethdev.c | 46 ++++++++++++++++++++++++ 3 files changed, 66 insertions(+) diff --git a/drivers/net/octeontx/base/octeontx_bgx.c b/drivers/net/octeontx/base/octeontx_bgx.c index 81a8cbecaf..1eacecbccc 100644 --- a/drivers/net/octeontx/base/octeontx_bgx.c +++ b/drivers/net/octeontx/base/octeontx_bgx.c @@ -144,6 +144,25 @@ octeontx_bgx_port_status(int port, octeontx_mbox_bgx_port_status_t *stat) return res; } +int +octeontx_bgx_port_multicast_set(int port, int en) +{ + struct octeontx_mbox_hdr hdr; + uint8_t prom; + int res; + + hdr.coproc = OCTEONTX_BGX_COPROC; + hdr.msg = MBOX_BGX_PORT_SET_MCAST; + hdr.vfid = port; + prom = en ? 1 : 0; + + res = octeontx_mbox_send(&hdr, &prom, sizeof(prom), NULL, 0); + if (res < 0) + return -EACCES; + + return res; +} + int octeontx_bgx_port_xstats(int port, octeontx_mbox_bgx_port_stats_t *stats) { diff --git a/drivers/net/octeontx/base/octeontx_bgx.h b/drivers/net/octeontx/base/octeontx_bgx.h index c5662202ac..3213d04e99 100644 --- a/drivers/net/octeontx/base/octeontx_bgx.h +++ b/drivers/net/octeontx/base/octeontx_bgx.h @@ -166,6 +166,7 @@ int octeontx_bgx_port_stats_clr(int port); int octeontx_bgx_port_xstats(int port, octeontx_mbox_bgx_port_stats_t *stats); int octeontx_bgx_port_link_status(int port); int octeontx_bgx_port_promisc_set(int port, int en); +int octeontx_bgx_port_multicast_set(int port, int en); int octeontx_bgx_port_mac_set(int port, uint8_t *mac_addr); int octeontx_bgx_port_mac_add(int port, uint8_t *mac_addr, int index); int octeontx_bgx_port_mac_del(int port, uint32_t index); diff --git a/drivers/net/octeontx/octeontx_ethdev.c b/drivers/net/octeontx/octeontx_ethdev.c index c15014bdde..3aca53fb98 100644 --- a/drivers/net/octeontx/octeontx_ethdev.c +++ b/drivers/net/octeontx/octeontx_ethdev.c @@ -847,6 +847,50 @@ octeontx_dev_link_update(struct rte_eth_dev *dev, return rte_eth_linkstatus_set(dev, &link); } +static int +octeontx_port_mcast_set(struct octeontx_nic *nic, int en) +{ + struct rte_eth_dev *dev; + int res; + + res = 0; + PMD_INIT_FUNC_TRACE(); + dev = nic->dev; + + res = octeontx_bgx_port_multicast_set(nic->port_id, en); + if (res < 0) { + octeontx_log_err("failed to set multicast mode %d", + nic->port_id); + return res; + } + + /* Set proper flag for the mode */ + dev->data->all_multicast = (en != 0) ? 1 : 0; + + octeontx_log_dbg("port %d : multicast mode %s", + nic->port_id, en ? "set" : "unset"); + + return 0; +} + +static int +octeontx_allmulticast_enable(struct rte_eth_dev *dev) +{ + struct octeontx_nic *nic = octeontx_pmd_priv(dev); + + PMD_INIT_FUNC_TRACE(); + return octeontx_port_mcast_set(nic, 1); +} + +static int +octeontx_allmulticast_disable(struct rte_eth_dev *dev) +{ + struct octeontx_nic *nic = octeontx_pmd_priv(dev); + + PMD_INIT_FUNC_TRACE(); + return octeontx_port_mcast_set(nic, 0); +} + static inline int octeontx_dev_total_xstat(void) { return NUM_BGX_XSTAT; @@ -1480,6 +1524,8 @@ static const struct eth_dev_ops octeontx_dev_ops = { .xstats_get_by_id = octeontx_dev_xstats_get_by_id, .xstats_get_names = octeontx_dev_xstats_get_names, .xstats_get_names_by_id = octeontx_dev_xstats_get_names_by_id, + .allmulticast_enable = octeontx_allmulticast_enable, + .allmulticast_disable = octeontx_allmulticast_disable, }; /* Create Ethdev interface per BGX LMAC ports */ From patchwork Tue May 24 08:42:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harman Kalra X-Patchwork-Id: 111718 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0D489A04FF; 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Tue, 24 May 2022 01:43:20 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 24 May 2022 01:43:18 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 24 May 2022 01:43:18 -0700 Received: from localhost.localdomain (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id 1600C3F70CA; Tue, 24 May 2022 01:43:15 -0700 (PDT) From: Harman Kalra To: , Jerin Jacob , Maciej Czekaj CC: Harman Kalra Subject: [PATCH v3 10/11] net/thunderx: device attach from secondary Date: Tue, 24 May 2022 14:12:34 +0530 Message-ID: <20220524084235.17796-10-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220524084235.17796-1-hkalra@marvell.com> References: <20220517173941.189330-2-hkalra@marvell.com> <20220524084235.17796-1-hkalra@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: _Qj4neeIwKrcYINzCDZfWAZepf7IkX45 X-Proofpoint-GUID: _Qj4neeIwKrcYINzCDZfWAZepf7IkX45 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-24_06,2022-05-23_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding support for device hotplugging - attach and detach from secondary Signed-off-by: Harman Kalra --- drivers/net/thunderx/base/nicvf_mbox.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/net/thunderx/base/nicvf_mbox.c b/drivers/net/thunderx/base/nicvf_mbox.c index 352b85d9e2..5993eec4e6 100644 --- a/drivers/net/thunderx/base/nicvf_mbox.c +++ b/drivers/net/thunderx/base/nicvf_mbox.c @@ -85,6 +85,17 @@ nicvf_mbox_send_msg_to_pf(struct nicvf *nic, struct nic_mbx *mbx) nicvf_smp_wmb(); nicvf_mbox_send_msg_to_pf_raw(nic, mbx); + + /* Handling case if mbox is called inside interrupt context, + * Eg if hotplug attach/detach request is initiated from + * secondary and primary handles the request in interrupt + * context as part of multprocess framework. + */ + if (rte_thread_is_intr()) { + nicvf_delay_us(NICVF_MBOX_PF_RESPONSE_DELAY_US); + nicvf_reg_poll_interrupts(nic); + } + /* Give some time to get PF response */ nicvf_delay_us(NICVF_MBOX_PF_RESPONSE_DELAY_US); timeout = NIC_MBOX_MSG_TIMEOUT; @@ -100,10 +111,10 @@ nicvf_mbox_send_msg_to_pf(struct nicvf *nic, struct nic_mbx *mbx) nicvf_delay_us(NICVF_MBOX_PF_RESPONSE_DELAY_US); timeout -= sleep; } - nicvf_log_error("PF didn't ack to msg 0x%02x %s VF%d (%d/%d)", - mbx->msg.msg, nicvf_mbox_msg_str(mbx->msg.msg), - nic->vf_id, i, retry); } + nicvf_log_error("PF didn't ack to msg 0x%02x %s VF%d (%d/%d)", + mbx->msg.msg, nicvf_mbox_msg_str(mbx->msg.msg), + nic->vf_id, i, retry); return -EBUSY; } From patchwork Tue May 24 08:42:35 2022 Content-Type: text/plain; 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Tue, 24 May 2022 01:43:18 -0700 (PDT) From: Harman Kalra To: , Jerin Jacob , Maciej Czekaj CC: Hanumanth Pothula Subject: [PATCH v3 11/11] net/thunderx: populate max and min MTU values Date: Tue, 24 May 2022 14:12:35 +0530 Message-ID: <20220524084235.17796-11-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220524084235.17796-1-hkalra@marvell.com> References: <20220517173941.189330-2-hkalra@marvell.com> <20220524084235.17796-1-hkalra@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: febWBxU3JoAf4qgtthUNSuBJji_UEY50 X-Proofpoint-GUID: febWBxU3JoAf4qgtthUNSuBJji_UEY50 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-24_06,2022-05-23_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Hanumanth Pothula Populate maximum and minimum MTU values while retrieving device information. Signed-off-by: Hanumanth Pothula --- drivers/net/thunderx/nicvf_ethdev.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/thunderx/nicvf_ethdev.c b/drivers/net/thunderx/nicvf_ethdev.c index 0f79b02172..262c024560 100644 --- a/drivers/net/thunderx/nicvf_ethdev.c +++ b/drivers/net/thunderx/nicvf_ethdev.c @@ -1479,6 +1479,10 @@ nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->max_mac_addrs = 1; dev_info->max_vfs = pci_dev->max_vfs; + dev_info->max_mtu = dev_info->max_rx_pktlen - + (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN); + dev_info->min_mtu = dev_info->min_rx_bufsize - NIC_HW_L2_OVERHEAD; + dev_info->rx_offload_capa = NICVF_RX_OFFLOAD_CAPA; dev_info->tx_offload_capa = NICVF_TX_OFFLOAD_CAPA; dev_info->rx_queue_offload_capa = NICVF_RX_OFFLOAD_CAPA;