From patchwork Sun Jun 19 03:21:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shun Hao X-Patchwork-Id: 113075 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 15E67A034C; Sun, 19 Jun 2022 05:21:58 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6D129410EC; Sun, 19 Jun 2022 05:21:55 +0200 (CEST) Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1anam02on2065.outbound.protection.outlook.com [40.107.96.65]) by mails.dpdk.org (Postfix) with ESMTP id 245E940E28; Sun, 19 Jun 2022 05:21:54 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Ids96F79WZWRJTwSf0fj93JYD4OUXfzIfUXWz11Q+6Y9UnAgo3aGID+mfc33wmz2PmwXqKkZv5thY/00s1URPkHGtzi/CELfdmFaQgO0U0zM5m8Q2sCjLDMUvj+T8wmi55+4+y2MYwByMoLtRz2Dx9zkFu+GCVLA/uVdVSi4NU0YssYNRqaItlT7l+xSmeeef5vTXP4lh7yxNzOBeAOXxWN3S86gCbE3VSEd3lJ5tlLzJQiW+AK8l81WxnpQa5kz6Ismle9XSEmIMxiM9HsIRECc7Nt6vAzOH0vk6v53hR5PzdhTIqZsxmvNfUJ7TVLMK5WP/1zIdEuvujd/kq1B6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QK8fpibdby2jxrL8N2S5uxVp0plk+o/TYbfd4M9cjjc=; b=fAbcePKCPWomqnGT1yzqBbJJvUI5gkYNiKNHtFkDxkz6ChKOH8q8XwIPheZFAsSDt9bmi/q0D5uJc3oxVTXr9qf3tJVdLCWbP2v2toUWToT/iIaF7zxADxjRIp7YWs7Pf6I2AzpYsYBqqKyy2woHhBhQmnE1Zm3SLb7H/+BETL3Gy4C4jesEZ9ArdVPmytRA89H5nIiSniRQNui5e44hMdWKXSDAZGbiG/bVO3NpkKFhMnkYbGBQRoTIuinVMu9yby+axL0YeIwqxOTdMR7DgK/D7d3310seYu2D6t2RoBLF3tTB2yh3BnG+YCPw/3rpgFZQWXNRYrSBjIU8FvDPSQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QK8fpibdby2jxrL8N2S5uxVp0plk+o/TYbfd4M9cjjc=; b=Hn8+2jkif6/i3ZACjOxQBxjng29YqowIVmuAPLIFqSWJiabvzXnfMteBaCzkG0Q1m3cH6TXydXo3pAY5naRTSBO1cufruUtY/NHUJu7F+LCtskTqVDxy3Ua2PnV0tqXTdL38hR/2V2E0NF1Scqt1F2M4NRX7Tl69usCTt9F1QRdococYNz78WmRtV44jQcHzX6LS8yamnw12fr5DFd1A8C/HyCKHU1aR6cjkfATJhKw3a11subBiN2OKJTq37vcIn7NMuSB5dmoAwRL5m+kxxBjdMAp5U7C+lB461o4LTr3jcBdRc1aJgCbI9rRILDmmcYRmx4/5kyyiLo7rkIl3Mg== Received: from CO2PR05CA0081.namprd05.prod.outlook.com (2603:10b6:102:2::49) by PH7PR12MB6540.namprd12.prod.outlook.com (2603:10b6:510:213::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5353.15; Sun, 19 Jun 2022 03:21:51 +0000 Received: from CO1NAM11FT019.eop-nam11.prod.protection.outlook.com (2603:10b6:102:2:cafe::84) by CO2PR05CA0081.outlook.office365.com (2603:10b6:102:2::49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5373.13 via Frontend Transport; Sun, 19 Jun 2022 03:21:51 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.236) by CO1NAM11FT019.mail.protection.outlook.com (10.13.175.57) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5353.14 via Frontend Transport; Sun, 19 Jun 2022 03:21:50 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Sun, 19 Jun 2022 03:21:50 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 18 Jun 2022 20:21:47 -0700 From: Shun Hao To: , , , "Xueming Li" CC: , , Subject: [PATCH v1 1/2] net/mlx5: add limitation for E-Switch Manager match Date: Sun, 19 Jun 2022 06:21:27 +0300 Message-ID: <20220619032128.24588-2-shunh@nvidia.com> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20220619032128.24588-1-shunh@nvidia.com> References: <20220619032128.24588-1-shunh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e1f04bbb-38c8-41c2-0ea8-08da51a2d9da X-MS-TrafficTypeDiagnostic: PH7PR12MB6540:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PgX0gE5Nbwxk6k5wukbEGPd7ZCvkFAONamHeJyCWnJZwGBr1r024tJ4HGQE8Bcz8O4AlYQ8wINw9ZKj04U2b0AAUPuEFckFfhxaLh5Vgr8mBw8scSoXE5EJ6qe6ZPISmGrRybf3sPlB++IuLZOslVg5eA8/Fz3OYXz1j1k8NB1QjYkSdGc9W/z21Mxk9JOCsGCdOhF+DC+bCSvjii5hge3t5xuTi+cdnImosCCfreG50kn/mk28o1aFjy1vCahHz/6jFGPV0kJdJmlc8Jif7AZNct5ussM1+hIiYBI1fe8GlNYTtNm4YeQ+5z10ZoDqmS9YNDVq2QgRu5f2Nect/Zf3ckpGYFeTx4wdX/x0vKMAbeYaBqpUnFrceMNm1EAN9PjFHhk3f9N64Roir/Nhk+NIg6c4bGhP5uJHAI7YeEeHscgs/kmQMBXknUJIUSoJTX7omspRpc0di/4Md6FdKPOdrtoCQYKfAqOsRHtdEkOieEWsLVAizPzBsQgvrmE+SngXs1MzKupP+ZNw0uwu+ljFuwceRAonZPvELJ9u8Sb0Qu11K7zumuNwB/VBgjVC5J7Z+4ZcaA8xcMH68LU9aEjxuWTLoAdsvaTb9zAvZgK/uyKE6Z65ybnTwSHO2iGI32gBXHKiqUakfIlEZcP7D94m2pmAonIR966EK3DlakNjyPi7BLnM1pY4m3xqlXhpf2YVOrSctHPDMytU9F0Sqtw== X-Forefront-Antispam-Report: CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230016)(4636009)(40470700004)(46966006)(36840700001)(70206006)(70586007)(4326008)(8676002)(83380400001)(426003)(450100002)(186003)(336012)(16526019)(498600001)(47076005)(2906002)(6286002)(26005)(8936002)(40460700003)(2616005)(86362001)(5660300002)(1076003)(6666004)(7696005)(36860700001)(316002)(54906003)(110136005)(6636002)(81166007)(36756003)(55016003)(356005)(82310400005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2022 03:21:50.6751 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e1f04bbb-38c8-41c2-0ea8-08da51a2d9da X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6540 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For BF with old FW which doesn't expose the E-Switch Manager vport ID, E-Switch Manager port matching works correctly only when BF is in embedded CPU mode. This patch adds the limitation description. Fixes: a564038699f9 ("net/mlx5: support E-Switch manager egress traffic match") Cc: stable@dpdk.org Signed-off-by: Shun Hao Acked-by: Matan Azard --- doc/guides/nics/mlx5.rst | 4 ++++ drivers/net/mlx5/mlx5_flow.h | 4 ++++ drivers/net/mlx5/mlx5_flow_dv.c | 10 ++++++++-- 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 1b66b2bc33..f10e112d27 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -534,6 +534,10 @@ Limitations - When configuring host shaper with MLX5_HOST_SHAPER_FLAG_AVAIL_THRESH_TRIGGERED flag set, only rates 0 and 100Mbps are supported. +- E-Switch Manager matching: + + - For Bluefield with old FW which doesn't expose the E-Switch Manager vport ID in the capability, matching E-Switch Manager should be used only in Bluefield embedded CPU mode. + Statistics ---------- diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index f00c033fc5..7300390070 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -2076,4 +2076,8 @@ int flow_dv_action_query(struct rte_eth_dev *dev, size_t flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type); int flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf, size_t *size, struct rte_flow_error *error); + +#define MLX5_PF_VPORT_ID 0 +#define MLX5_ECPF_VPORT_ID 0xFFFE + #endif /* RTE_PMD_MLX5_FLOW_H_ */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 65b02b20ce..09f662bdcf 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -99,6 +99,7 @@ flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev) struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_common_device *cdev = priv->sh->cdev; + /* New FW exposes E-Switch Manager vport ID, can use it directly. */ if (cdev->config.hca_attr.esw_mgr_vport_id_valid) return (int16_t)cdev->config.hca_attr.esw_mgr_vport_id; @@ -108,9 +109,14 @@ flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev) case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF: case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF: case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF: - return (int16_t)0xfffe; + /* + * In old FW which doesn't expose the E-Switch Manager vport ID in the capability, + * only the BF embedded CPUs control the E-Switch Manager port. Hence, + * ECPF vport ID is selected and not the host port (0) in any BF case. + */ + return (int16_t)MLX5_ECPF_VPORT_ID; default: - return 0; + return MLX5_PF_VPORT_ID; } } From patchwork Sun Jun 19 03:21:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shun Hao X-Patchwork-Id: 113076 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 269C4A034C; Sun, 19 Jun 2022 05:22:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B60ED4280E; Sun, 19 Jun 2022 05:21:58 +0200 (CEST) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2046.outbound.protection.outlook.com [40.107.220.46]) by mails.dpdk.org (Postfix) with ESMTP id 26EF8427F9; Sun, 19 Jun 2022 05:21:57 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=M9kXGbVXwY1bAE/nQU9g/cPq01jQ/0VLeUecb1lglJDDCcymzvIb/Wliu/VDO+i6cMlBNYf3Nd7YAP5FRVcliWaKQG+qGgTeSoWwOh26IFRM1nNW9TLVCD1tinW14sqbemaOZ3iV5fZkyQukRYAIqwj5q8WTVqZcG8Ioi7DbNbJgheYGLx5ntMDPAZKuNsZLvvKHbMwENS2M6N3uSdbCC56jRAsrDIr1u66OZ81WgVfcEzUYYjRt7WNQY+YM5etomXADL/+ssVlqoRrZ6+Lz0rn5X2fqMIOFdFF+H/shlsYot8pQcbKspjmwYvuJw+t3SD1OKff+IagqpzmnfRin2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=XzRqP0Oz7jEjwefHIxXTuTEch79W1RFaeX60Kgkp7bE=; b=RGq5Cpmf2PbmJSfytQH4K2czH02ehP3szdt51pVZ6hqMHcmifBfeeDBDDHCtDMCX7onMf7OpQUd4VMrQ1EqKrlXAZkl25w7URj0mLnkGeYKEjahIy9oa5+VoSuQ9ApSa0KT2sKPvDotOoZXzEGfRR4pmSiFtJpEqujtXl6KCybwoJP2AVG5lhSHJVma11D73AF2naim6wuUE7wdG1UU4ypULQwyv9PuaD60IUT2riQf+JwJmWBRqCWmCtdtA1McKMgOljEMmd46HH0cKJko58ncRmc2bntnhD8YGjuF9EVhkmtvesgHShLb2r9xExFakaWZL0YkkdzSUbBCL0JcnaA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XzRqP0Oz7jEjwefHIxXTuTEch79W1RFaeX60Kgkp7bE=; b=miTRQ/KUjzQ6Rimb26VX/U+KX7j+hGrgd3yEw+BKvQs9sZkeMt7I18SRIj08zRWVTVjCgJ/Id1CtjlH4zE45WYRdJNSrRbVbAVICTYxpEjOZVzjjtah8omSTeSiQyx6oJY5DyEP5lOdxBVBBc87O/ip/8QuxBBy/trF+bzIAh9zMdBmfk7dnUZnKVTd3yDT4Q1buq0R2fZfxj4IMWPthJd0Zu1XJuqgxB481BX0yucvGLSfELcS6Xm+xlzHRueL3bBTpKqo98bOAnaS9iq6lrv71w8pdPX0x0N809yHZ5FxGxnUdAuaGQvZna9gg3GBAr0JPMnGfqdTeEzwxQM+yuA== Received: from DS7PR03CA0012.namprd03.prod.outlook.com (2603:10b6:5:3b8::17) by BL1PR12MB5222.namprd12.prod.outlook.com (2603:10b6:208:31e::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5353.15; Sun, 19 Jun 2022 03:21:54 +0000 Received: from DM6NAM11FT053.eop-nam11.prod.protection.outlook.com (2603:10b6:5:3b8:cafe::68) by DS7PR03CA0012.outlook.office365.com (2603:10b6:5:3b8::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5353.18 via Frontend Transport; Sun, 19 Jun 2022 03:21:54 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.235) by DM6NAM11FT053.mail.protection.outlook.com (10.13.173.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5353.14 via Frontend Transport; Sun, 19 Jun 2022 03:21:53 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Sun, 19 Jun 2022 03:21:53 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 18 Jun 2022 20:21:50 -0700 From: Shun Hao To: , , CC: , , Subject: [PATCH v1 2/2] net/mlx5: fix meter fail when used on E-Switch Manager Date: Sun, 19 Jun 2022 06:21:28 +0300 Message-ID: <20220619032128.24588-3-shunh@nvidia.com> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20220619032128.24588-1-shunh@nvidia.com> References: <20220619032128.24588-1-shunh@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e54bc531-ba23-4035-faa6-08da51a2dba3 X-MS-TrafficTypeDiagnostic: BL1PR12MB5222:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JJIlJZnlhP7ASKwxd5DmBqbMoeOtIUjV/jql8pSE6nBYMQew6AibL2pJqcdkg+rpgdoSW+q1aJ2uwbbex7+CfAX0d0FTbGnYq1v62STFA3DLX9f/XDGGvSC3+2eMjqqwkevh1LjQtbkkq8Voa/MUJa7mvWO7M0YnoKzgQqNqIcRnScdGjMGUchleakw2pfH852V9QvzBmfvvUkq25cUxru3I+QPw2C+r3EehBXXrCjq7ZRCduyf1GcaVlHBO+WJxXMBSRJJP3DbZWUF4oAwOWfKKgZN+8e43SZV7/0ZbXloOVkQhrmDk6hkUQzRDZK/9D121tkJb3QjWDA0YxVrm6IjJSiNb0UchCrPPYlG8x8IAGJT6Ahqoa9uo1r2aXMQGHqh8UONdWA6sB7FE9I+qULfbTTjqJ8q2ZCO9qqGMW9Z8SkF+TZ17DqGhdvvkQBUDnIL2CO6Mc76G6jGCacFEaS7FJyCprJOxIjEXbdwu0XvNqaSaVKtd5a/UT1sW/z4G2VANX3xYkC2KS2F01ffNsFW32Gkf6i07wcqceGfazr6Eg0aHe39uC+EEXRHx9fAoL92Y1/27cG2+mnOHiiGbRGC/OD4aREc3Vdr4nU6rT++Jee/e7IMrS4QDWc8JpDW1tMvl586JbaHb7SKhdXdtcYCmJLL8nd1eejRdqAVREmL6/8khyC07IltYf2Ide0bdAKz5ScU3Es0u9DZbn42Idg== X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230016)(4636009)(46966006)(40470700004)(36840700001)(5660300002)(26005)(426003)(2906002)(86362001)(110136005)(36860700001)(36756003)(81166007)(7696005)(450100002)(356005)(6286002)(6636002)(54906003)(498600001)(70586007)(1076003)(186003)(16526019)(336012)(8676002)(316002)(40460700003)(82310400005)(83380400001)(2616005)(55016003)(70206006)(6666004)(8936002)(47076005)(4326008)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2022 03:21:53.6605 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e54bc531-ba23-4035-faa6-08da51a2dba3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5222 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When meter is used by E-Switch Manager port, there's an error that cannot get correct port ID. This patch fixes this by using specific parsing process to get port ID for E-Switch Manager. Fixes: 3c481324baf3 ("net/mlx5: fix meter flow direction check") Cc: stable@dpdk.org Signed-off-by: Shun Hao Acked-by: Matan Azard --- drivers/net/mlx5/mlx5_flow.c | 93 ++++++++++++++++++++++++++++----- drivers/net/mlx5/mlx5_flow.h | 6 +++ drivers/net/mlx5/mlx5_flow_dv.c | 48 +++-------------- 3 files changed, 92 insertions(+), 55 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 090de0366b..cfcd884b82 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -5297,7 +5297,7 @@ flow_meter_split_prep(struct rte_eth_dev *dev, const struct rte_flow_item *orig_items = items; struct rte_flow_action *hw_mtr_action; struct rte_flow_action *action_pre_head = NULL; - int32_t flow_src_port = priv->representor_id; + uint16_t flow_src_port = priv->representor_id; bool mtr_first; uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0; uint8_t mtr_reg_bits = priv->mtr_reg_share ? @@ -5311,22 +5311,12 @@ flow_meter_split_prep(struct rte_eth_dev *dev, /* Prepare the suffix subflow items. */ tag_item = sfx_items++; for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { - struct mlx5_priv *port_priv; - const struct rte_flow_item_port_id *pid_v; int item_type = items->type; switch (item_type) { case RTE_FLOW_ITEM_TYPE_PORT_ID: - pid_v = items->spec; - MLX5_ASSERT(pid_v); - port_priv = mlx5_port_to_eswitch_info(pid_v->id, false); - if (!port_priv) - return rte_flow_error_set(error, - rte_errno, - RTE_FLOW_ERROR_TYPE_ITEM_SPEC, - pid_v, - "Failed to get port info."); - flow_src_port = port_priv->representor_id; + if (mlx5_flow_get_item_vport_id(dev, items, &flow_src_port, error)) + return -rte_errno; if (!fm->def_policy && wks->policy->is_hierarchy && flow_src_port != priv->representor_id) { if (flow_drv_mtr_hierarchy_rule_create(dev, @@ -10955,3 +10945,80 @@ mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, } return res; } + +/** + * Get the E-Switch Manager vport id. + * + * @param[in] dev + * Pointer to the Ethernet device structure. + * + * @return + * The vport id. + */ +int16_t mlx5_flow_get_esw_manager_vport_id(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_common_device *cdev = priv->sh->cdev; + + /* New FW exposes E-Switch Manager vport ID, can use it directly. */ + if (cdev->config.hca_attr.esw_mgr_vport_id_valid) + return (int16_t)cdev->config.hca_attr.esw_mgr_vport_id; + + if (priv->pci_dev == NULL) + return 0; + switch (priv->pci_dev->id.device_id) { + case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF: + case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF: + case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF: + /* + * In old FW which doesn't expose the E-Switch Manager vport ID in the capability, + * only the BF embedded CPUs control the E-Switch Manager port. Hence, + * ECPF vport ID is selected and not the host port (0) in any BF case. + */ + return (int16_t)MLX5_ECPF_VPORT_ID; + default: + return MLX5_PF_VPORT_ID; + } +} + +/** + * Parse item to get the vport id. + * + * @param[in] dev + * Pointer to the Ethernet device structure. + * @param[in] item + * The src port id match item. + * @param[out] vport_id + * Pointer to put the vport id. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int mlx5_flow_get_item_vport_id(struct rte_eth_dev *dev, + const struct rte_flow_item *item, + uint16_t *vport_id, + struct rte_flow_error *error) +{ + struct mlx5_priv *port_priv; + const struct rte_flow_item_port_id *pid_v; + + if (item->type != RTE_FLOW_ITEM_TYPE_PORT_ID) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + NULL, "Incorrect item type."); + pid_v = item->spec; + if (!pid_v) + return 0; + if (pid_v->id == MLX5_PORT_ESW_MGR) { + *vport_id = mlx5_flow_get_esw_manager_vport_id(dev); + } else { + port_priv = mlx5_port_to_eswitch_info(pid_v->id, false); + if (!port_priv) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + NULL, "Failed to get port info."); + *vport_id = port_priv->representor_id; + } + + return 0; +} diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 7300390070..4c233cd94a 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -2080,4 +2080,10 @@ int flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf, #define MLX5_PF_VPORT_ID 0 #define MLX5_ECPF_VPORT_ID 0xFFFE +int16_t mlx5_flow_get_esw_manager_vport_id(struct rte_eth_dev *dev); +int mlx5_flow_get_item_vport_id(struct rte_eth_dev *dev, + const struct rte_flow_item *item, + uint16_t *vport_id, + struct rte_flow_error *error); + #endif /* RTE_PMD_MLX5_FLOW_H_ */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 09f662bdcf..09349a021b 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -93,33 +93,6 @@ static int flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev, uint32_t rix_jump); -static int16_t -flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev) -{ - struct mlx5_priv *priv = dev->data->dev_private; - struct mlx5_common_device *cdev = priv->sh->cdev; - - /* New FW exposes E-Switch Manager vport ID, can use it directly. */ - if (cdev->config.hca_attr.esw_mgr_vport_id_valid) - return (int16_t)cdev->config.hca_attr.esw_mgr_vport_id; - - if (priv->pci_dev == NULL) - return 0; - switch (priv->pci_dev->id.device_id) { - case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF: - case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF: - case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF: - /* - * In old FW which doesn't expose the E-Switch Manager vport ID in the capability, - * only the BF embedded CPUs control the E-Switch Manager port. Hence, - * ECPF vport ID is selected and not the host port (0) in any BF case. - */ - return (int16_t)MLX5_ECPF_VPORT_ID; - default: - return MLX5_PF_VPORT_ID; - } -} - /** * Initialize flow attributes structure according to flow items' types. * @@ -5334,21 +5307,12 @@ mlx5_flow_validate_action_meter(struct rte_eth_dev *dev, */ struct mlx5_priv *policy_port_priv = mtr_policy->dev->data->dev_private; - int32_t flow_src_port = priv->representor_id; + uint16_t flow_src_port = priv->representor_id; if (port_id_item) { - const struct rte_flow_item_port_id *spec = - port_id_item->spec; - struct mlx5_priv *port_priv = - mlx5_port_to_eswitch_info(spec->id, - false); - if (!port_priv) - return rte_flow_error_set(error, - rte_errno, - RTE_FLOW_ERROR_TYPE_ITEM_SPEC, - spec, - "Failed to get port info."); - flow_src_port = port_priv->representor_id; + if (mlx5_flow_get_item_vport_id(dev, port_id_item, + &flow_src_port, error)) + return -rte_errno; } if (flow_src_port != policy_port_priv->representor_id) return rte_flow_error_set(error, @@ -10047,7 +10011,7 @@ flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher, if (pid_v && pid_v->id == MLX5_PORT_ESW_MGR) { flow_dv_translate_item_source_vport(matcher, key, - flow_dv_get_esw_manager_vport_id(dev), 0xffff); + mlx5_flow_get_esw_manager_vport_id(dev), 0xffff); return 0; } mask = pid_m ? pid_m->id : 0xffff; @@ -10118,7 +10082,7 @@ flow_dv_translate_item_represented_port(struct rte_eth_dev *dev, void *matcher, return 0; if (pid_v && pid_v->port_id == UINT16_MAX) { flow_dv_translate_item_source_vport(matcher, key, - flow_dv_get_esw_manager_vport_id(dev), UINT16_MAX); + mlx5_flow_get_esw_manager_vport_id(dev), UINT16_MAX); return 0; } mask = pid_m ? pid_m->port_id : UINT16_MAX;